diff options
author | Zhenhua Luo <b19537@freescale.com> | 2012-03-09 10:57:35 +0000 |
---|---|---|
committer | Matthew McClintock <msm@freescale.com> | 2012-03-13 12:41:42 -0500 |
commit | 122c5bfdad95930de96e191aafb0304fded007b2 (patch) | |
tree | ea66cb9147fed9ceacd9eacd5913b10bb64734a1 /recipes-devtools/gcc | |
parent | 4f2d99fbb0afd19376e404583700ee31428f7c2e (diff) | |
download | meta-fsl-ppc-122c5bfdad95930de96e191aafb0304fded007b2.tar.gz |
integrate fsl toolchain patches
binutils:
bin.e500mc_nop.patch
bin.e5500.patch
bin.e6500-2.patch
eglibc:
generate-supported.mk
glibc.e500mc_subspecies_of_powerpc_is_not_supported.patch
glibc.fixgcc4.6.patch
glibc.fix_prof.patch
glibc.fix_sqrt.patch
glibc.readv_proto.patch
glibc.undefined_static.patch
gcc:
gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch
gcc.fix_longversionstring.patch
gcc.rm_slow_tests.patch
gcc.fix_mingw32.patch
gcc.fix_cloogstatic2.patch
gcc.fix_build-with-cxx.patch
gcc.e6500-FSF46.patch
gcc.ld_unaligned-460.patch
gcc.local_unaligned_altivec.patch
gcc.soft_float-460.patch
gcc.case_values.patch
gcc.builtin_isel.patch
gcc.experimental_move.patch
gcc.widen_types-46.patch
gcc.extelim-v3.patch
gcc.e5500_mfocr.patch
gcc.opt-array-offset.patch
gcc.load_on_store_bypass-462.patch
gcc.fix_constvector.patch
gcc.fix_MTWX51204-dwarf-vector-reg.patch
gcc.fix_ira-loop-pressure.patch
optional_libstdc.patch
gcc.remove_CCUNSmode_reference.patch
gcc.check_path_validity.patch
gcc.fix_header_issue.patch
gcc.fix_SSIZE_MAX_undefine_issue.patch
gettext:
gettext.fix_testcase.patch
Signed-off-by: Zhenhua Luo <b19537@freescale.com>
Diffstat (limited to 'recipes-devtools/gcc')
36 files changed, 11536 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/files/gcc.builtin_isel.patch b/recipes-devtools/gcc/files/gcc.builtin_isel.patch new file mode 100644 index 0000000..10e5999 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.builtin_isel.patch | |||
@@ -0,0 +1,1059 @@ | |||
1 | diff -ruN gcc-4.6.0-orig/gcc/config/rs6000/rs6000-builtin.def gcc-4.6.0-new/gcc/config/rs6000/rs6000-builtin.def | ||
2 | --- gcc-4.6.0-orig/gcc/config/rs6000/rs6000-builtin.def 2011-02-21 15:38:21.000000000 -0600 | ||
3 | +++ gcc-4.6.0-new/gcc/config/rs6000/rs6000-builtin.def 2011-07-25 12:32:26.626006000 -0500 | ||
4 | @@ -750,6 +750,71 @@ | ||
5 | RS6000_BUILTIN(SPE_BUILTIN_MFSPEFSCR, RS6000_BTC_MISC) | ||
6 | RS6000_BUILTIN(SPE_BUILTIN_BRINC, RS6000_BTC_MISC) | ||
7 | |||
8 | +/* ISEL builtins. */ | ||
9 | +/* Generic versions that get resolved to specific builtins. */ | ||
10 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELEQ, RS6000_BTC_PURE) | ||
11 | +RS6000_BUILTIN_EQUATE(ISEL_BUILTIN_OVERLOADED_FIRST, | ||
12 | + RS6000_BUILTIN_ISELEQ) | ||
13 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELGT, RS6000_BTC_PURE) | ||
14 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELLT, RS6000_BTC_PURE) | ||
15 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELGTU, RS6000_BTC_PURE) | ||
16 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELLTU, RS6000_BTC_PURE) | ||
17 | +/* Same deal, but for 64-bit comparisons. */ | ||
18 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELEQD, RS6000_BTC_PURE) | ||
19 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELGTD, RS6000_BTC_PURE) | ||
20 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELLTD, RS6000_BTC_PURE) | ||
21 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELGTDU, RS6000_BTC_PURE) | ||
22 | +RS6000_BUILTIN(RS6000_BUILTIN_ISELLTDU, RS6000_BTC_PURE) | ||
23 | +RS6000_BUILTIN_EQUATE(ISEL_BUILTIN_OVERLOADED_LAST, | ||
24 | + RS6000_BUILTIN_ISELLTDU) | ||
25 | + | ||
26 | +/* Each set of arguments is polymorphic in selected arguments and return | ||
27 | + value. */ | ||
28 | +#undef RS6000_ISEL_BASE | ||
29 | +#define RS6000_ISEL_BASE(ARG, PRED, CMP) \ | ||
30 | + RS6000_BUILTIN(RS6000_BUILTIN_ISEL_##PRED##CMP##_##ARG##_SS, RS6000_BTC_PURE) \ | ||
31 | + RS6000_BUILTIN(RS6000_BUILTIN_ISEL_##PRED##CMP##_##ARG##_PP, RS6000_BTC_PURE) \ | ||
32 | + RS6000_BUILTIN(RS6000_BUILTIN_ISEL_##PRED##CMP##_##ARG##_UU, RS6000_BTC_PURE) | ||
33 | +#undef RS6000_ISEL_PTR_ARG | ||
34 | +#define RS6000_ISEL_PTR_ARG(PRED, CMP) RS6000_ISEL_BASE(PP, PRED, CMP) | ||
35 | +#undef RS6000_ISEL_SIGNED_ARG | ||
36 | +#define RS6000_ISEL_SIGNED_ARG(PRED, CMP) RS6000_ISEL_BASE(SS, PRED, CMP) | ||
37 | +#undef RS6000_ISEL_UNSIGNED_ARG | ||
38 | +#define RS6000_ISEL_UNSIGNED_ARG(PRED, CMP) RS6000_ISEL_BASE(UU, PRED, CMP) | ||
39 | + | ||
40 | +#undef RS6000_ISEL_EQ | ||
41 | +#define RS6000_ISEL_EQ(CMP) \ | ||
42 | + RS6000_ISEL_PTR_ARG(EQ, CMP) \ | ||
43 | + RS6000_ISEL_SIGNED_ARG(EQ, CMP) \ | ||
44 | + RS6000_ISEL_UNSIGNED_ARG(EQ, CMP) | ||
45 | + | ||
46 | +#undef RS6000_ISEL_LT | ||
47 | +#define RS6000_ISEL_LT(CMP) RS6000_ISEL_SIGNED_ARG(LT, CMP) | ||
48 | + | ||
49 | +#undef RS6000_ISEL_GT | ||
50 | +#define RS6000_ISEL_GT(CMP) RS6000_ISEL_SIGNED_ARG(GT, CMP) | ||
51 | + | ||
52 | +#undef RS6000_ISEL_LTU | ||
53 | +#define RS6000_ISEL_LTU(CMP) \ | ||
54 | + RS6000_ISEL_PTR_ARG(LTU, CMP) \ | ||
55 | + RS6000_ISEL_UNSIGNED_ARG(LTU, CMP) | ||
56 | + | ||
57 | +#undef RS6000_ISEL_GTU | ||
58 | +#define RS6000_ISEL_GTU(CMP) \ | ||
59 | + RS6000_ISEL_PTR_ARG(GTU, CMP) \ | ||
60 | + RS6000_ISEL_UNSIGNED_ARG(GTU, CMP) | ||
61 | + | ||
62 | +RS6000_ISEL_EQ(CMPW) | ||
63 | +RS6000_ISEL_LT(CMPW) | ||
64 | +RS6000_ISEL_GT(CMPW) | ||
65 | +RS6000_ISEL_LTU(CMPW) | ||
66 | +RS6000_ISEL_GTU(CMPW) | ||
67 | +RS6000_ISEL_EQ(CMPD) | ||
68 | +RS6000_ISEL_LT(CMPD) | ||
69 | +RS6000_ISEL_GT(CMPD) | ||
70 | +RS6000_ISEL_LTU(CMPD) | ||
71 | +RS6000_ISEL_GTU(CMPD) | ||
72 | + | ||
73 | /* PAIRED builtins. */ | ||
74 | RS6000_BUILTIN(PAIRED_BUILTIN_DIVV2SF3, RS6000_BTC_MISC) | ||
75 | RS6000_BUILTIN(PAIRED_BUILTIN_ABSV2SF2, RS6000_BTC_MISC) | ||
76 | diff -ruN gcc-4.6.0-orig/gcc/config/rs6000/rs6000.c gcc-4.6.0-new/gcc/config/rs6000/rs6000.c | ||
77 | --- gcc-4.6.0-orig/gcc/config/rs6000/rs6000.c 2011-03-15 07:57:37.000000000 -0500 | ||
78 | +++ gcc-4.6.0-new/gcc/config/rs6000/rs6000.c 2011-07-25 13:19:52.415921000 -0500 | ||
79 | @@ -12402,6 +12402,289 @@ | ||
80 | return target; | ||
81 | } | ||
82 | |||
83 | +/* isel builtins are a bit funny, because we want the user to be able to do: | ||
84 | + | ||
85 | + char *p, *q, *r; | ||
86 | + int x, y, z; | ||
87 | + unsigned int a, b, c; | ||
88 | + ... | ||
89 | + p = __builtin_iseleq (i, j, q, r); | ||
90 | + x = __builtin_iseleq (i, j, y, z); | ||
91 | + a = __builtin_iseleq (i, j, b, c); | ||
92 | + | ||
93 | + and, of course, i and j may be of several different types depending on the | ||
94 | + condition. | ||
95 | + | ||
96 | + We handle this by having generic builtins that | ||
97 | + TARGET_RESOLVE_OVERLOADED_BUILTIN takes and turns into calls to our | ||
98 | + specific builtins. */ | ||
99 | + | ||
100 | +/* Macros to help constructing the isel_builtin_desc arrays. | ||
101 | + These closely mirror the macros in rs6000-builtins.def. */ | ||
102 | +/* HACK: Use VOIDmode here as a constant approximation to Pmode and fix | ||
103 | + at runtime. We can't use Pmode because in biarch its definition is | ||
104 | + not constant. */ | ||
105 | +#define ISEL_Pmode VOIDmode | ||
106 | +#define ISEL_BASE(FLAGS, ARG, RESULT, PRED, CMP, MODE, RMODE) \ | ||
107 | + { NULL, FLAGS, RS6000_BUILTIN_ISEL_##PRED##CMP##_##ARG##_##RESULT, \ | ||
108 | + PRED, MODE, RMODE }, | ||
109 | +#define ISEL_P_RESULT(FLAGS, ARG, PRED, CMP, MODE, RMODE) \ | ||
110 | + ISEL_BASE (FLAGS | ISEL_FLAG_SEL_PTR, ARG, PP, PRED, \ | ||
111 | + CMP, MODE, ISEL_Pmode) | ||
112 | +#define ISEL_S_RESULT(FLAGS, ARG, PRED, CMP, MODE, RMODE) \ | ||
113 | + ISEL_BASE (FLAGS | ISEL_FLAG_SEL_SIGNED, ARG, SS, PRED, \ | ||
114 | + CMP, MODE, RMODE) | ||
115 | +#define ISEL_U_RESULT(FLAGS, ARG, PRED, CMP, MODE, RMODE) \ | ||
116 | + ISEL_BASE (FLAGS | ISEL_FLAG_SEL_UNSIGNED, ARG, UU, PRED, \ | ||
117 | + CMP, MODE, RMODE) | ||
118 | + | ||
119 | +#define ISEL_EXPAND_ARG(FLAG, ARG, PRED, CMP, MODE, RMODE) \ | ||
120 | + ISEL_P_RESULT (FLAG, ARG, PRED, CMP, MODE, RMODE) \ | ||
121 | + ISEL_S_RESULT (FLAG, ARG, PRED, CMP, MODE, RMODE) \ | ||
122 | + ISEL_U_RESULT (FLAG, ARG, PRED, CMP, MODE, RMODE) | ||
123 | +#define ISEL_PTR_ARG(PRED, CMP, MODE) \ | ||
124 | + ISEL_EXPAND_ARG (ISEL_FLAG_CMP_PTR, PP, PRED, CMP, ISEL_Pmode, MODE) | ||
125 | +#define ISEL_SIGNED_ARG(PRED, CMP, MODE) \ | ||
126 | + ISEL_EXPAND_ARG (ISEL_FLAG_CMP_SIGNED, SS, PRED, CMP, MODE, MODE) | ||
127 | +#define ISEL_UNSIGNED_ARG(PRED, CMP, MODE) \ | ||
128 | + ISEL_EXPAND_ARG (ISEL_FLAG_CMP_UNSIGNED, UU, PRED, CMP, MODE, MODE) | ||
129 | + | ||
130 | +#define ISEL_EQ(CMP, MODE) \ | ||
131 | + ISEL_PTR_ARG (EQ, CMP, MODE) \ | ||
132 | + ISEL_SIGNED_ARG (EQ, CMP, MODE) \ | ||
133 | + ISEL_UNSIGNED_ARG (EQ, CMP, MODE) | ||
134 | +#define ISEL_LT(CMP, MODE) ISEL_SIGNED_ARG (LT, CMP, MODE) | ||
135 | +#define ISEL_GT(CMP, MODE) ISEL_SIGNED_ARG (GT, CMP, MODE) | ||
136 | +#define ISEL_LTU(CMP, MODE) \ | ||
137 | + ISEL_PTR_ARG (LTU, CMP, MODE) \ | ||
138 | + ISEL_UNSIGNED_ARG (LTU, CMP, MODE) | ||
139 | +#define ISEL_GTU(CMP, MODE) \ | ||
140 | + ISEL_PTR_ARG (GTU, CMP, MODE) \ | ||
141 | + ISEL_UNSIGNED_ARG (GTU, CMP, MODE) | ||
142 | + | ||
143 | +const struct isel_builtin_desc builtin_iselw[32] = { | ||
144 | + ISEL_EQ (CMPW, SImode) | ||
145 | + ISEL_LT (CMPW, SImode) | ||
146 | + ISEL_GT (CMPW, SImode) | ||
147 | + ISEL_LTU (CMPW, SImode) | ||
148 | + ISEL_GTU (CMPW, SImode) | ||
149 | + { "__builtin_iseleq", 0, RS6000_BUILTIN_ISELEQ, EQ, SImode, SImode }, | ||
150 | + { "__builtin_isellt", 0, RS6000_BUILTIN_ISELLT, LT, SImode, SImode }, | ||
151 | + { "__builtin_iselgt", 0, RS6000_BUILTIN_ISELGT, GT, SImode, SImode }, | ||
152 | + { "__builtin_iselltu", 0, RS6000_BUILTIN_ISELLTU, LTU, SImode, SImode }, | ||
153 | + { "__builtin_iselgtu", 0, RS6000_BUILTIN_ISELGTU, GTU, SImode, SImode } | ||
154 | +}; | ||
155 | + | ||
156 | +const struct isel_builtin_desc builtin_iseld[32] = { | ||
157 | + ISEL_EQ (CMPD, DImode) | ||
158 | + ISEL_LT (CMPD, DImode) | ||
159 | + ISEL_GT (CMPD, DImode) | ||
160 | + ISEL_LTU (CMPD, DImode) | ||
161 | + ISEL_GTU (CMPD, DImode) | ||
162 | + { "__builtin_isel64eq", 0, RS6000_BUILTIN_ISELEQD, EQ, DImode, DImode }, | ||
163 | + { "__builtin_isel64lt", 0, RS6000_BUILTIN_ISELLTD, LT, DImode, DImode }, | ||
164 | + { "__builtin_isel64gt", 0, RS6000_BUILTIN_ISELGTD, GT, DImode, DImode }, | ||
165 | + { "__builtin_isel64ltu", 0, RS6000_BUILTIN_ISELLTDU, LTU, DImode, DImode }, | ||
166 | + { "__builtin_isel64gtu", 0, RS6000_BUILTIN_ISELGTDU, GTU, DImode, DImode } | ||
167 | +}; | ||
168 | + | ||
169 | +/* Return the mode which DESC uses for comparisons. */ | ||
170 | + | ||
171 | +static enum machine_mode | ||
172 | +isel_cmp_mode (const struct isel_builtin_desc *desc) | ||
173 | +{ | ||
174 | + enum machine_mode mode = (enum machine_mode) desc->cmp_mode; | ||
175 | + | ||
176 | + return (mode == VOIDmode ? Pmode : mode); | ||
177 | +} | ||
178 | + | ||
179 | +/* Return the mode in which DESC selects arguments. */ | ||
180 | + | ||
181 | +static enum machine_mode | ||
182 | +isel_sel_mode (const struct isel_builtin_desc *desc) | ||
183 | +{ | ||
184 | + enum machine_mode mode = (enum machine_mode) desc->sel_mode; | ||
185 | + | ||
186 | + return (mode == VOIDmode ? Pmode : mode); | ||
187 | +} | ||
188 | + | ||
189 | +/* Return a tree describing the arguments for DESC according to CMPP: | ||
190 | + true for comparison arguments, false for select arguments. */ | ||
191 | + | ||
192 | +static tree | ||
193 | +isel_argtype (const struct isel_builtin_desc *desc, bool cmpp) | ||
194 | +{ | ||
195 | + switch (desc->arg_flags & (cmpp | ||
196 | + ? ISEL_FLAG_CMP_MASK | ||
197 | + : ISEL_FLAG_SEL_MASK)) | ||
198 | + { | ||
199 | + case ISEL_FLAG_CMP_PTR: | ||
200 | + case ISEL_FLAG_SEL_PTR: | ||
201 | + return ptr_type_node; | ||
202 | + case ISEL_FLAG_CMP_SIGNED: | ||
203 | + return (isel_cmp_mode (desc) == SImode | ||
204 | + ? integer_type_node | ||
205 | + : long_integer_type_node); | ||
206 | + case ISEL_FLAG_SEL_SIGNED: | ||
207 | + return (isel_sel_mode (desc) == SImode | ||
208 | + ? integer_type_node | ||
209 | + : long_integer_type_node); | ||
210 | + case ISEL_FLAG_CMP_UNSIGNED: | ||
211 | + return (isel_cmp_mode (desc) == SImode | ||
212 | + ? unsigned_type_node | ||
213 | + : long_unsigned_type_node); | ||
214 | + case ISEL_FLAG_SEL_UNSIGNED: | ||
215 | + default: | ||
216 | + return (isel_sel_mode (desc) == SImode | ||
217 | + ? unsigned_type_node | ||
218 | + : long_unsigned_type_node); | ||
219 | + } | ||
220 | +} | ||
221 | + | ||
222 | +/* Return a mnemonic string describing the argument or result of FLAGS | ||
223 | + depending on CMPP. */ | ||
224 | + | ||
225 | +static const char * | ||
226 | +isel_strdesc (int flags, bool cmpp) | ||
227 | +{ | ||
228 | + switch (flags & (cmpp ? ISEL_FLAG_CMP_MASK : ISEL_FLAG_SEL_MASK)) | ||
229 | + { | ||
230 | + case ISEL_FLAG_CMP_PTR: | ||
231 | + case ISEL_FLAG_SEL_PTR: | ||
232 | + return "p"; | ||
233 | + case ISEL_FLAG_CMP_SIGNED: | ||
234 | + case ISEL_FLAG_SEL_SIGNED: | ||
235 | + return "s"; | ||
236 | + case ISEL_FLAG_CMP_UNSIGNED: | ||
237 | + case ISEL_FLAG_SEL_UNSIGNED: | ||
238 | + return "u"; | ||
239 | + default: | ||
240 | + gcc_unreachable (); | ||
241 | + } | ||
242 | +} | ||
243 | + | ||
244 | +/* Initialize N_DESC isel builtins from DESC. SIGNED_TYPE holds the | ||
245 | + basic type for signed variants of isel, UNSIGNED_TYPE the type for | ||
246 | + unsigned variants. */ | ||
247 | + | ||
248 | +static void | ||
249 | +rs6000_init_isel_builtins (const struct isel_builtin_desc *desc, int n_descs) | ||
250 | +{ | ||
251 | + int i; | ||
252 | + const char *is64 = (desc == &builtin_iselw[0] ? "32" : "64"); | ||
253 | + | ||
254 | + for (i = 0; i < n_descs; i++) | ||
255 | + { | ||
256 | + const struct isel_builtin_desc *d = &desc[i]; | ||
257 | + tree cmptype, seltype, ftype; | ||
258 | + | ||
259 | + cmptype = isel_argtype (d, true); | ||
260 | + seltype = isel_argtype (d, false); | ||
261 | + | ||
262 | + ftype = build_function_type_list (seltype, cmptype, cmptype, | ||
263 | + seltype, seltype, NULL_TREE); | ||
264 | + | ||
265 | + if (d->name) | ||
266 | + def_builtin (MASK_ISEL, d->name, ftype, d->code); | ||
267 | + else | ||
268 | + { | ||
269 | + char builtin_name[40]; | ||
270 | + | ||
271 | + sprintf (builtin_name, "__builtin_isel%s%s%s%s%s%s", | ||
272 | + is64, | ||
273 | + GET_RTX_NAME (d->cmp_code), | ||
274 | + GET_MODE_NAME (isel_cmp_mode (d)), | ||
275 | + isel_strdesc (d->arg_flags, true), | ||
276 | + isel_strdesc (d->arg_flags, false), | ||
277 | + GET_MODE_NAME (isel_sel_mode (d))); | ||
278 | + | ||
279 | + def_builtin (MASK_ISEL, ggc_strdup (builtin_name), ftype, d->code); | ||
280 | + } | ||
281 | + } | ||
282 | +} | ||
283 | + | ||
284 | +static rtx | ||
285 | +rs6000_expand_isel_builtin (const struct isel_builtin_desc *desc, | ||
286 | + int n_descs, tree exp, rtx target, int fcode) | ||
287 | +{ | ||
288 | + int i; | ||
289 | + | ||
290 | + for (i = 0; i < n_descs; i++) | ||
291 | + { | ||
292 | + const struct isel_builtin_desc *d = &desc[i]; | ||
293 | + | ||
294 | + if (fcode == (int) d->code) | ||
295 | + { | ||
296 | + int opidx; | ||
297 | + unsigned int j; | ||
298 | + rtx cmp; | ||
299 | + rtx operands[4]; | ||
300 | + enum insn_code icode; | ||
301 | + enum machine_mode opmode; | ||
302 | + enum machine_mode cmpmode = isel_cmp_mode (d); | ||
303 | + enum machine_mode selmode = isel_sel_mode (d); | ||
304 | + | ||
305 | + /* Determine underlying isel insn. */ | ||
306 | + switch (d->cmp_code) | ||
307 | + { | ||
308 | + case GTU: | ||
309 | + case LTU: | ||
310 | + icode = (Pmode == SImode | ||
311 | + ? CODE_FOR_isel_unsigned_si | ||
312 | + : CODE_FOR_isel_unsigned_di); | ||
313 | + break; | ||
314 | + default: | ||
315 | + icode = (Pmode == SImode | ||
316 | + ? CODE_FOR_isel_signed_si | ||
317 | + : CODE_FOR_isel_signed_di); | ||
318 | + break; | ||
319 | + } | ||
320 | + | ||
321 | + for (j = 0; j < ARRAY_SIZE (operands); j++) | ||
322 | + { | ||
323 | + tree arg = CALL_EXPR_ARG (exp, j); | ||
324 | + | ||
325 | + /* If we got invalid arguments, bail out before generating | ||
326 | + bad rtl. */ | ||
327 | + if (arg == error_mark_node) | ||
328 | + return const0_rtx; | ||
329 | + | ||
330 | + operands[j] = expand_normal (arg); | ||
331 | + | ||
332 | + /* Validate. */ | ||
333 | + /* HACK: The isel pattern doesn't actually consume all the | ||
334 | + operands to the builtin; it only consumes 2 and 3. The | ||
335 | + other two will be handed off to a compare | ||
336 | + insn. Unfortunately, said insn is not named, so we | ||
337 | + can't directly access its insn_data here. Fake it by | ||
338 | + validating operands 0 and 1 with the isel pattern; that | ||
339 | + should be good enough. */ | ||
340 | + opidx = (j < 2 ? 2 : j); | ||
341 | + opmode = (j < 2 ? cmpmode : selmode); | ||
342 | + if (! (*insn_data[icode].operand[opidx].predicate) (operands[j], | ||
343 | + opmode)) | ||
344 | + operands[j] = copy_to_mode_reg (opmode, operands[j]); | ||
345 | + } | ||
346 | + | ||
347 | + /* Validate target. */ | ||
348 | + if (target == NULL_RTX | ||
349 | + || GET_MODE (target) != selmode | ||
350 | + || ! (*insn_data[icode].operand[0].predicate) (target, selmode)) | ||
351 | + target = gen_reg_rtx (selmode); | ||
352 | + | ||
353 | + /* Generate comparison. */ | ||
354 | + cmp = gen_rtx_fmt_ee ((enum rtx_code)d->cmp_code, cmpmode, | ||
355 | + operands[0], operands[1]); | ||
356 | + | ||
357 | + rs6000_emit_int_cmove (target, cmp, operands[2], operands[3]); | ||
358 | + | ||
359 | + return target; | ||
360 | + } | ||
361 | + } | ||
362 | + | ||
363 | + return NULL_RTX; | ||
364 | +} | ||
365 | + | ||
366 | /* Expand an expression EXP that calls a built-in function, | ||
367 | with result going to TARGET if that's convenient | ||
368 | (and in mode MODE if that's convenient). | ||
369 | @@ -12520,6 +12803,24 @@ | ||
370 | if (success) | ||
371 | return ret; | ||
372 | } | ||
373 | + if (TARGET_ISEL) | ||
374 | + { | ||
375 | + ret = rs6000_expand_isel_builtin (builtin_iselw, | ||
376 | + ARRAY_SIZE (builtin_iselw), | ||
377 | + exp, target, fcode); | ||
378 | + | ||
379 | + if (ret != NULL_RTX) | ||
380 | + return ret; | ||
381 | + } | ||
382 | + if (TARGET_ISEL64) | ||
383 | + { | ||
384 | + ret = rs6000_expand_isel_builtin (builtin_iseld, | ||
385 | + ARRAY_SIZE (builtin_iseld), | ||
386 | + exp, target, fcode); | ||
387 | + | ||
388 | + if (ret != NULL_RTX) | ||
389 | + return ret; | ||
390 | + } | ||
391 | |||
392 | gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT); | ||
393 | |||
394 | @@ -12738,6 +13039,10 @@ | ||
395 | spe_init_builtins (); | ||
396 | if (TARGET_ALTIVEC) | ||
397 | altivec_init_builtins (); | ||
398 | + if (TARGET_ISEL) | ||
399 | + rs6000_init_isel_builtins (builtin_iselw, ARRAY_SIZE (builtin_iselw)); | ||
400 | + if (TARGET_ISEL64) | ||
401 | + rs6000_init_isel_builtins (builtin_iseld, ARRAY_SIZE (builtin_iseld)); | ||
402 | if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT || TARGET_VSX) | ||
403 | rs6000_common_init_builtins (); | ||
404 | if (TARGET_FRE) | ||
405 | diff -ruN gcc-4.6.0-orig/gcc/config/rs6000/rs6000-c.c gcc-4.6.0-new/gcc/config/rs6000/rs6000-c.c | ||
406 | --- gcc-4.6.0-orig/gcc/config/rs6000/rs6000-c.c 2011-02-02 23:42:19.000000000 -0600 | ||
407 | +++ gcc-4.6.0-new/gcc/config/rs6000/rs6000-c.c 2011-07-25 16:07:14.616209000 -0500 | ||
408 | @@ -3439,7 +3439,7 @@ | ||
409 | /* Implementation of the resolve_overloaded_builtin target hook, to | ||
410 | support Altivec's overloaded builtins. */ | ||
411 | |||
412 | -tree | ||
413 | +static tree | ||
414 | altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, | ||
415 | void *passed_arglist) | ||
416 | { | ||
417 | @@ -3770,3 +3770,148 @@ | ||
418 | error ("invalid parameter combination for AltiVec intrinsic"); | ||
419 | return error_mark_node; | ||
420 | } | ||
421 | + | ||
422 | +/* Return true if the pair of arguments in ARGS is acceptable according | ||
423 | + to DECLTYPES and FLAGS. CMPP determines whether this is for the | ||
424 | + comparison arguments. */ | ||
425 | + | ||
426 | +static bool | ||
427 | +isel_arguments_valid (tree *args, tree *decltypes, int flags, bool cmpp) | ||
428 | +{ | ||
429 | + tree type0 = TREE_TYPE (args[0]); | ||
430 | + tree type1 = TREE_TYPE (args[1]); | ||
431 | + tree decltype0 = decltypes[0]; | ||
432 | + tree decltype1 = decltypes[1]; | ||
433 | + | ||
434 | + switch (flags & (cmpp ? ISEL_FLAG_CMP_MASK : ISEL_FLAG_SEL_MASK)) | ||
435 | + { | ||
436 | + /* For pointer arguments and results, we just need to make sure | ||
437 | + we're receiving pointers, and they can be freely converted to | ||
438 | + and from void *. For pointer results, we also need to ensure | ||
439 | + that the types of the passed arguments are compatible: this is | ||
440 | + similar to what the ?: construct would need to ensure. */ | ||
441 | + case ISEL_FLAG_CMP_PTR: | ||
442 | + case ISEL_FLAG_SEL_PTR: | ||
443 | + { | ||
444 | + /* Results compatible with each other? */ | ||
445 | + if (!lang_hooks.types_compatible_p (type0, type1)) | ||
446 | + return false; | ||
447 | + | ||
448 | + return (POINTER_TYPE_P (type0) | ||
449 | + && POINTER_TYPE_P (type1)); | ||
450 | + } | ||
451 | + break; | ||
452 | + /* For signed and unsigned arguments and results, we just need to | ||
453 | + make sure that the argument types are compatible with the | ||
454 | + declared types; we can insert conversions to make everything | ||
455 | + match up. */ | ||
456 | + case ISEL_FLAG_CMP_SIGNED: | ||
457 | + case ISEL_FLAG_SEL_SIGNED: | ||
458 | + case ISEL_FLAG_CMP_UNSIGNED: | ||
459 | + case ISEL_FLAG_SEL_UNSIGNED: | ||
460 | + return (lang_hooks.types_compatible_p (type0, decltype0) | ||
461 | + && lang_hooks.types_compatible_p (type1, decltype1)); | ||
462 | + default: | ||
463 | + ; | ||
464 | + } | ||
465 | + | ||
466 | + gcc_unreachable (); | ||
467 | +} | ||
468 | + | ||
469 | +/* Determine if FNDECL is a generic isel intrinsic and if it can be | ||
470 | + resolved to a non-generic version with a proper type using the | ||
471 | + descriptions found in DESC. Return a call to the non-generic builtin | ||
472 | + if so. */ | ||
473 | + | ||
474 | +static tree | ||
475 | +rs6000_resolve_isel_builtin (location_t loc, tree fndecl, | ||
476 | + void *passed_arglist, | ||
477 | + const struct isel_builtin_desc *desc, | ||
478 | + int n_descs) | ||
479 | +{ | ||
480 | + VEC(tree,gc) *arglist = (VEC(tree,gc) *) passed_arglist; | ||
481 | + unsigned int nargs = VEC_length (tree, arglist); | ||
482 | + int i; | ||
483 | + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | ||
484 | + const struct isel_builtin_desc *generic = NULL; | ||
485 | + | ||
486 | + /* Is this even a builtin we care about? */ | ||
487 | + if (fcode < ISEL_BUILTIN_OVERLOADED_FIRST | ||
488 | + || fcode > ISEL_BUILTIN_OVERLOADED_LAST) | ||
489 | + return NULL_TREE; | ||
490 | + | ||
491 | + if (nargs != 4) | ||
492 | + { | ||
493 | + error ("isel intrinsics only accept 4 arguments"); | ||
494 | + return error_mark_node; | ||
495 | + } | ||
496 | + | ||
497 | + /* Find the generic builtin we're resolving. */ | ||
498 | + for (i = 0; i < n_descs; i++) | ||
499 | + if (desc[i].code == fcode) | ||
500 | + { | ||
501 | + generic = &desc[i]; | ||
502 | + break; | ||
503 | + } | ||
504 | + | ||
505 | + /* Happens if we're looking for a 64-bit builtin in the 32-bit | ||
506 | + descriptors. */ | ||
507 | + if (generic == NULL) | ||
508 | + return NULL_TREE; | ||
509 | + | ||
510 | + /* Try all the builtins whose comparison matches the generic one. */ | ||
511 | + for (i = 0; i < n_descs; i++) | ||
512 | + { | ||
513 | + const struct isel_builtin_desc *d = &desc[i]; | ||
514 | + int j; | ||
515 | + tree *argp = VEC_address (tree, arglist); | ||
516 | + tree impl_fndecl; | ||
517 | + tree decltypes[4], t; | ||
518 | + tree converted_args[4]; | ||
519 | + | ||
520 | + if (d == generic || d->cmp_code != generic->cmp_code) | ||
521 | + continue; | ||
522 | + | ||
523 | + impl_fndecl = rs6000_builtin_decls[d->code]; | ||
524 | + t = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl)); | ||
525 | + for (j = 0 ; t != void_list_node; j++, t = TREE_CHAIN (t)) | ||
526 | + decltypes[j] = TREE_VALUE (t); | ||
527 | + | ||
528 | + if (!isel_arguments_valid (argp, decltypes, d->arg_flags, true) | ||
529 | + || !isel_arguments_valid (argp+2, decltypes+2, d->arg_flags, false)) | ||
530 | + continue; | ||
531 | + | ||
532 | + /* We got here, we're ok. Build a new, resolved CALL_EXPR. */ | ||
533 | + for (j = 0; j < 4; j++) | ||
534 | + converted_args[j] = fold_convert (decltypes[j], argp[j]); | ||
535 | + | ||
536 | + return build_call_expr_loc (loc, impl_fndecl, 4, | ||
537 | + converted_args[0], converted_args[1], | ||
538 | + converted_args[2], converted_args[3]); | ||
539 | + } | ||
540 | + | ||
541 | + error ("invalid parameter combination for isel intrinsic"); | ||
542 | + return error_mark_node; | ||
543 | +} | ||
544 | + | ||
545 | +tree | ||
546 | +rs6000_resolve_overloaded_builtin (location_t loc, tree fndecl, void *arglist) | ||
547 | +{ | ||
548 | + tree t; | ||
549 | + | ||
550 | + t = altivec_resolve_overloaded_builtin (loc, fndecl, arglist); | ||
551 | + if (t) | ||
552 | + return t; | ||
553 | + | ||
554 | + t = rs6000_resolve_isel_builtin (loc, fndecl, arglist, | ||
555 | + builtin_iselw, ARRAY_SIZE (builtin_iselw)); | ||
556 | + if (t) | ||
557 | + return t; | ||
558 | + | ||
559 | + t = rs6000_resolve_isel_builtin (loc, fndecl, arglist, | ||
560 | + builtin_iseld, ARRAY_SIZE (builtin_iseld)); | ||
561 | + if (t) | ||
562 | + return t; | ||
563 | + | ||
564 | + return NULL_TREE; | ||
565 | +} | ||
566 | diff -ruN gcc-4.6.0-orig/gcc/config/rs6000/rs6000.h gcc-4.6.0-new/gcc/config/rs6000/rs6000.h | ||
567 | --- gcc-4.6.0-orig/gcc/config/rs6000/rs6000.h 2011-03-07 13:27:09.000000000 -0600 | ||
568 | +++ gcc-4.6.0-new/gcc/config/rs6000/rs6000.h 2011-07-25 16:07:04.045105000 -0500 | ||
569 | @@ -535,7 +535,7 @@ | ||
570 | #define REGISTER_TARGET_PRAGMAS() do { \ | ||
571 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | ||
572 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ | ||
573 | - targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ | ||
574 | + targetm.resolve_overloaded_builtin = rs6000_resolve_overloaded_builtin; \ | ||
575 | } while (0) | ||
576 | |||
577 | /* Target #defines. */ | ||
578 | @@ -2446,3 +2446,41 @@ | ||
579 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | ||
580 | extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | ||
581 | |||
582 | +/* Values for struct isel_builtin_desc.arg_flags. */ | ||
583 | +enum { | ||
584 | + ISEL_FLAG_CMP_PTR = 0x1, | ||
585 | + ISEL_FLAG_CMP_SIGNED = 0x2, | ||
586 | + ISEL_FLAG_CMP_UNSIGNED = 0x4, | ||
587 | + ISEL_FLAG_CMP_MASK = 0x7, | ||
588 | + ISEL_FLAG_SEL_PTR = 0x10, | ||
589 | + ISEL_FLAG_SEL_SIGNED = 0x20, | ||
590 | + ISEL_FLAG_SEL_UNSIGNED = 0x40, | ||
591 | + ISEL_FLAG_SEL_MASK = 0x70 | ||
592 | +}; | ||
593 | + | ||
594 | +struct isel_builtin_desc { | ||
595 | + /* Name of this builtin. NULL if we should construct it. */ | ||
596 | + const char *name; | ||
597 | + | ||
598 | + /* Flags for argument combinations accepted by the builtin. | ||
599 | + Zero if this builtin is a generic builtin, to be resolved later. */ | ||
600 | + int arg_flags; | ||
601 | + | ||
602 | + /* The code of the builtin. */ | ||
603 | + enum rs6000_builtins code; | ||
604 | + | ||
605 | + /* rtx_code and machine_mode are not available here; use ints instead. */ | ||
606 | + /* The comparison code the builtin uses. */ | ||
607 | + int cmp_code; | ||
608 | + | ||
609 | + /* The mode the builtin does comparisons in. */ | ||
610 | + int cmp_mode; | ||
611 | + | ||
612 | + /* The mode the builtin's selected arguments are in. | ||
613 | + Also happens to be its result mode. */ | ||
614 | + int sel_mode; | ||
615 | +}; | ||
616 | + | ||
617 | +/* Arrays describing isel builtins. */ | ||
618 | +extern const struct isel_builtin_desc builtin_iselw[32]; | ||
619 | +extern const struct isel_builtin_desc builtin_iseld[32]; | ||
620 | diff -ruN gcc-4.6.0-orig/gcc/config/rs6000/rs6000-protos.h gcc-4.6.0-new/gcc/config/rs6000/rs6000-protos.h | ||
621 | --- gcc-4.6.0-orig/gcc/config/rs6000/rs6000-protos.h 2011-03-15 07:57:37.000000000 -0500 | ||
622 | +++ gcc-4.6.0-new/gcc/config/rs6000/rs6000-protos.h 2011-07-25 16:07:50.484773000 -0500 | ||
623 | @@ -142,7 +142,7 @@ | ||
624 | unsigned int); | ||
625 | extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int, | ||
626 | unsigned int); | ||
627 | -extern tree altivec_resolve_overloaded_builtin (location_t, tree, void *); | ||
628 | +extern tree rs6000_resolve_overloaded_builtin (location_t, tree, void *); | ||
629 | extern rtx rs6000_libcall_value (enum machine_mode); | ||
630 | extern rtx rs6000_va_arg (tree, tree); | ||
631 | extern int function_ok_for_sibcall (tree); | ||
632 | diff -ruN gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel64.c gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel64.c | ||
633 | --- gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel64.c 1969-12-31 18:00:00.000000000 -0600 | ||
634 | +++ gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel64.c 2011-07-25 12:27:55.343932000 -0500 | ||
635 | @@ -0,0 +1,75 @@ | ||
636 | +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ | ||
637 | +/* { dg-options "-mcpu=e500mc64" } */ | ||
638 | + | ||
639 | +#include "builtin-isel.h" | ||
640 | + | ||
641 | +/* Equality comparisons. */ | ||
642 | + | ||
643 | +#undef FUNCTION_NAME | ||
644 | +#define FUNCTION_NAME isel64eq | ||
645 | + | ||
646 | +SIGNED64_PROTO | ||
647 | +{ | ||
648 | + L = ISEL_BUILTIN (x, y, a, b); | ||
649 | + U = ISEL_BUILTIN (x, y, (unsigned long) a, (unsigned long) b); | ||
650 | + r = ISEL_BUILTIN (x, y, p, q); | ||
651 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
652 | + L = ISEL_BUILTIN (p, q, a, b); | ||
653 | + /* Equality checks explicitly permit unsigned comparison operands. */ | ||
654 | + L = ISEL_BUILTIN ((unsigned long) x, (unsigned long) y, a, b); | ||
655 | + r = ISEL_BUILTIN ((unsigned long) x, (unsigned long) y, p, q); | ||
656 | +} | ||
657 | + | ||
658 | +/* less-than, greater-than. */ | ||
659 | + | ||
660 | +#undef FUNCTION_NAME | ||
661 | +#define FUNCTION_NAME isel64lt | ||
662 | + | ||
663 | +SIGNED64_PROTO | ||
664 | +{ | ||
665 | + L = ISEL_BUILTIN (x, y, a, b); | ||
666 | + U = ISEL_BUILTIN (x, y, (unsigned long) a, (unsigned long) b); | ||
667 | + r = ISEL_BUILTIN (x, y, p, q); | ||
668 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
669 | +} | ||
670 | + | ||
671 | +#undef FUNCTION_NAME | ||
672 | +#define FUNCTION_NAME isel64gt | ||
673 | + | ||
674 | +SIGNED64_PROTO | ||
675 | +{ | ||
676 | + L = ISEL_BUILTIN (x, y, a, b); | ||
677 | + U = ISEL_BUILTIN (x, y, (unsigned long) a, (unsigned long) b); | ||
678 | + r = ISEL_BUILTIN (x, y, p, q); | ||
679 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
680 | +} | ||
681 | + | ||
682 | +/* Unsigned variants. These permit unsigned and pointer operands for | ||
683 | + comparison only. */ | ||
684 | + | ||
685 | +#undef FUNCTION_NAME | ||
686 | +#define FUNCTION_NAME isel64ltu | ||
687 | + | ||
688 | +UNSIGNED64_PROTO | ||
689 | +{ | ||
690 | + L = ISEL_BUILTIN (x, y, a, b); | ||
691 | + U = ISEL_BUILTIN (x, y, (unsigned long) a, (unsigned long) b); | ||
692 | + r = ISEL_BUILTIN (x, y, p, q); | ||
693 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
694 | + L = ISEL_BUILTIN (p, q, a, b); | ||
695 | +} | ||
696 | + | ||
697 | +#undef FUNCTION_NAME | ||
698 | +#define FUNCTION_NAME isel64gtu | ||
699 | + | ||
700 | +UNSIGNED64_PROTO | ||
701 | +{ | ||
702 | + L = ISEL_BUILTIN (x, y, a, b); | ||
703 | + U = ISEL_BUILTIN (x, y, (unsigned long) a, (unsigned long) b); | ||
704 | + r = ISEL_BUILTIN (x, y, p, q); | ||
705 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
706 | + L = ISEL_BUILTIN (p, q, a, b); | ||
707 | +} | ||
708 | + | ||
709 | +/* Don't use bare isel, as that'll match function names and the like. */ | ||
710 | +/* { dg-final { scan-assembler-times "isel " 26 } } */ | ||
711 | diff -ruN gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel64-errors.c gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel64-errors.c | ||
712 | --- gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel64-errors.c 1969-12-31 18:00:00.000000000 -0600 | ||
713 | +++ gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel64-errors.c 2011-07-25 12:27:55.372965000 -0500 | ||
714 | @@ -0,0 +1,110 @@ | ||
715 | +/* Test rejection of invalid parameter combinations in isel builtins. */ | ||
716 | +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ | ||
717 | +/* { dg-options "-mcpu=e5500" } */ | ||
718 | + | ||
719 | +#include "builtin-isel.h" | ||
720 | + | ||
721 | + | ||
722 | +/* Equality comparisons. */ | ||
723 | + | ||
724 | +#undef FUNCTION_NAME | ||
725 | +#define FUNCTION_NAME isel64eq | ||
726 | + | ||
727 | +SIGNED64_PROTO | ||
728 | +{ | ||
729 | + /* Mismatches in argument type. */ | ||
730 | + ISEL_BUILTIN ((unsigned long) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
731 | + ISEL_BUILTIN (x, (unsigned long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
732 | + ISEL_BUILTIN ((long *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
733 | + ISEL_BUILTIN (p, (long *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
734 | + /* Mismatches in return type. */ | ||
735 | + ISEL_BUILTIN (x, y, (unsigned long) a, b); /* { dg-error "isel intrinsic" } */ | ||
736 | + ISEL_BUILTIN (x, y, a, (unsigned long) b); /* { dg-error "isel intrinsic" } */ | ||
737 | + ISEL_BUILTIN (x, y, (long *) p, q); /* { dg-error "isel intrinsic" } */ | ||
738 | + ISEL_BUILTIN (x, y, p, (long *) q); /* { dg-error "isel intrinsic" } */ | ||
739 | +} | ||
740 | + | ||
741 | +/* less-than, greater-than. */ | ||
742 | + | ||
743 | +#undef FUNCTION_NAME | ||
744 | +#define FUNCTION_NAME isel64lt | ||
745 | + | ||
746 | +SIGNED64_PROTO | ||
747 | +{ | ||
748 | + /* Unsigned comparison should be done with the *u variants. */ | ||
749 | + ISEL_BUILTIN ((unsigned long) x, (unsigned long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
750 | + /* So should pointer comparison. */ | ||
751 | + ISEL_BUILTIN (p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
752 | + /* Mismatches in argument type. */ | ||
753 | + ISEL_BUILTIN ((unsigned long) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
754 | + ISEL_BUILTIN (x, (unsigned long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
755 | + ISEL_BUILTIN ((long *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
756 | + ISEL_BUILTIN (p, (long *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
757 | + /* Mismatches in return type. */ | ||
758 | + ISEL_BUILTIN (x, y, (unsigned long) a, b); /* { dg-error "isel intrinsic" } */ | ||
759 | + ISEL_BUILTIN (x, y, a, (unsigned long) b); /* { dg-error "isel intrinsic" } */ | ||
760 | + ISEL_BUILTIN (x, y, (long *) p, q); /* { dg-error "isel intrinsic" } */ | ||
761 | + ISEL_BUILTIN (x, y, p, (long *) q); /* { dg-error "isel intrinsic" } */ | ||
762 | +} | ||
763 | + | ||
764 | +#undef FUNCTION_NAME | ||
765 | +#define FUNCTION_NAME isel64gt | ||
766 | + | ||
767 | +SIGNED64_PROTO | ||
768 | +{ | ||
769 | + /* Unsigned comparison should be done with the *u variants. */ | ||
770 | + ISEL_BUILTIN ((unsigned long) x, (unsigned long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
771 | + /* So should pointer comparison. */ | ||
772 | + ISEL_BUILTIN (p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
773 | + /* Mismatches in argument type. */ | ||
774 | + ISEL_BUILTIN ((unsigned long) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
775 | + ISEL_BUILTIN (x, (unsigned long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
776 | + ISEL_BUILTIN ((long *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
777 | + ISEL_BUILTIN (p, (long *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
778 | + /* Mismatches in return type. */ | ||
779 | + ISEL_BUILTIN (x, y, (unsigned long) a, b); /* { dg-error "isel intrinsic" } */ | ||
780 | + ISEL_BUILTIN (x, y, a, (unsigned long) b); /* { dg-error "isel intrinsic" } */ | ||
781 | + ISEL_BUILTIN (x, y, (long *) p, q); /* { dg-error "isel intrinsic" } */ | ||
782 | + ISEL_BUILTIN (x, y, p, (long *) q); /* { dg-error "isel intrinsic" } */ | ||
783 | +} | ||
784 | + | ||
785 | +/* Unsigned variants. These permit unsigned and pointer operands for | ||
786 | + comparison only. */ | ||
787 | + | ||
788 | +#undef FUNCTION_NAME | ||
789 | +#define FUNCTION_NAME isel64ltu | ||
790 | + | ||
791 | +UNSIGNED64_PROTO | ||
792 | +{ | ||
793 | + /* Signed comparison should be done with the signed variants. */ | ||
794 | + ISEL_BUILTIN ((long) x, (long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
795 | + /* Mismatches in argument type. */ | ||
796 | + ISEL_BUILTIN ((long) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
797 | + ISEL_BUILTIN (x, (long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
798 | + ISEL_BUILTIN ((long *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
799 | + ISEL_BUILTIN (p, (long *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
800 | + /* Mismatches in return type. */ | ||
801 | + ISEL_BUILTIN (x, y, (unsigned long) a, b); /* { dg-error "isel intrinsic" } */ | ||
802 | + ISEL_BUILTIN (x, y, a, (unsigned long) b); /* { dg-error "isel intrinsic" } */ | ||
803 | + ISEL_BUILTIN (x, y, (long *) p, q); /* { dg-error "isel intrinsic" } */ | ||
804 | + ISEL_BUILTIN (x, y, p, (long *) q); /* { dg-error "isel intrinsic" } */ | ||
805 | +} | ||
806 | + | ||
807 | +#undef FUNCTION_NAME | ||
808 | +#define FUNCTION_NAME isel64gtu | ||
809 | + | ||
810 | +UNSIGNED64_PROTO | ||
811 | +{ | ||
812 | + /* Signed comparison should be done with the signed variants. */ | ||
813 | + ISEL_BUILTIN ((long) x, (long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
814 | + /* Mismatches in argument type. */ | ||
815 | + ISEL_BUILTIN ((long) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
816 | + ISEL_BUILTIN (x, (long) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
817 | + ISEL_BUILTIN ((long *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
818 | + ISEL_BUILTIN (p, (long *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
819 | + /* Mismatches in return type. */ | ||
820 | + ISEL_BUILTIN (x, y, (unsigned long) a, b); /* { dg-error "isel intrinsic" } */ | ||
821 | + ISEL_BUILTIN (x, y, a, (unsigned long) b); /* { dg-error "isel intrinsic" } */ | ||
822 | + ISEL_BUILTIN (x, y, (long *) p, q); /* { dg-error "isel intrinsic" } */ | ||
823 | + ISEL_BUILTIN (x, y, p, (long *) q); /* { dg-error "isel intrinsic" } */ | ||
824 | +} | ||
825 | diff -ruN gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel.c gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel.c | ||
826 | --- gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel.c 1969-12-31 18:00:00.000000000 -0600 | ||
827 | +++ gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel.c 2011-07-25 12:27:55.405959000 -0500 | ||
828 | @@ -0,0 +1,81 @@ | ||
829 | +/* { dg-do compile } */ | ||
830 | +/* { dg-options "-mcpu=e500mc" } */ | ||
831 | + | ||
832 | +#include "builtin-isel.h" | ||
833 | + | ||
834 | +/* We're not being clever with the preprocessor here because DejaGNU | ||
835 | + will get confused. We do try to use it to eliminate what duplication | ||
836 | + we can. */ | ||
837 | + | ||
838 | +/* We check to see that the resolution permits polymorphic results. */ | ||
839 | + | ||
840 | +/* Equality comparisons. */ | ||
841 | + | ||
842 | +#undef FUNCTION_NAME | ||
843 | +#define FUNCTION_NAME iseleq | ||
844 | + | ||
845 | +SIGNED_PROTO | ||
846 | +{ | ||
847 | + i = ISEL_BUILTIN (x, y, a, b); | ||
848 | + u = ISEL_BUILTIN (x, y, (unsigned int) a, (unsigned int) b); | ||
849 | + r = ISEL_BUILTIN (x, y, p, q); | ||
850 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
851 | + i = ISEL_BUILTIN (p, q, a, b); | ||
852 | + /* Equality checks explicitly permit unsigned comparison operands. */ | ||
853 | + i = ISEL_BUILTIN ((unsigned int) x, (unsigned int) y, a, b); | ||
854 | + r = ISEL_BUILTIN ((unsigned int) x, (unsigned int) y, p, q); | ||
855 | +} | ||
856 | + | ||
857 | +/* less-than, greater-than. */ | ||
858 | + | ||
859 | +#undef FUNCTION_NAME | ||
860 | +#define FUNCTION_NAME isellt | ||
861 | + | ||
862 | +SIGNED_PROTO | ||
863 | +{ | ||
864 | + i = ISEL_BUILTIN (x, y, a, b); | ||
865 | + u = ISEL_BUILTIN (x, y, (unsigned int) a, (unsigned int) b); | ||
866 | + r = ISEL_BUILTIN (x, y, p, q); | ||
867 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
868 | +} | ||
869 | + | ||
870 | +#undef FUNCTION_NAME | ||
871 | +#define FUNCTION_NAME iselgt | ||
872 | + | ||
873 | +SIGNED_PROTO | ||
874 | +{ | ||
875 | + i = ISEL_BUILTIN (x, y, a, b); | ||
876 | + u = ISEL_BUILTIN (x, y, (unsigned int) a, (unsigned int) b); | ||
877 | + r = ISEL_BUILTIN (x, y, p, q); | ||
878 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
879 | +} | ||
880 | + | ||
881 | +/* Unsigned variants. These permit unsigned and pointer operands for | ||
882 | + comparison only. */ | ||
883 | + | ||
884 | +#undef FUNCTION_NAME | ||
885 | +#define FUNCTION_NAME iselltu | ||
886 | + | ||
887 | +UNSIGNED_PROTO | ||
888 | +{ | ||
889 | + i = ISEL_BUILTIN (x, y, a, b); | ||
890 | + u = ISEL_BUILTIN (x, y, (unsigned int) a, (unsigned int) b); | ||
891 | + r = ISEL_BUILTIN (x, y, p, q); | ||
892 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
893 | + i = ISEL_BUILTIN (p, q, a, b); | ||
894 | +} | ||
895 | + | ||
896 | +#undef FUNCTION_NAME | ||
897 | +#define FUNCTION_NAME iselgtu | ||
898 | + | ||
899 | +UNSIGNED_PROTO | ||
900 | +{ | ||
901 | + i = ISEL_BUILTIN (x, y, a, b); | ||
902 | + u = ISEL_BUILTIN (x, y, (unsigned int) a, (unsigned int) b); | ||
903 | + r = ISEL_BUILTIN (x, y, p, q); | ||
904 | + r = ISEL_BUILTIN (x, y, (char *) p, (char *) q); | ||
905 | + i = ISEL_BUILTIN (p, q, a, b); | ||
906 | +} | ||
907 | + | ||
908 | +/* Don't use bare isel, as that'll match function names and the like. */ | ||
909 | +/* { dg-final { scan-assembler-times "isel " 26 } } */ | ||
910 | diff -ruN gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel-errors.c gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel-errors.c | ||
911 | --- gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel-errors.c 1969-12-31 18:00:00.000000000 -0600 | ||
912 | +++ gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel-errors.c 2011-07-25 12:27:55.443938000 -0500 | ||
913 | @@ -0,0 +1,117 @@ | ||
914 | +/* Test rejection of invalid parameter combinations in isel builtins. */ | ||
915 | +/* { dg-do compile } */ | ||
916 | +/* { dg-options "-mcpu=e500mc" } */ | ||
917 | + | ||
918 | +#include "builtin-isel.h" | ||
919 | + | ||
920 | +/* We're not being clever with the preprocessor here because DejaGNU | ||
921 | + will get confused. We do try to use it to eliminate what duplication | ||
922 | + we can. */ | ||
923 | + | ||
924 | +/* We check basic resolution of each builtin. We also check to see that | ||
925 | + the resolution permits polymorphic results. Argument type mismatches | ||
926 | + and result type mismatches are not permitted, except where noted. */ | ||
927 | + | ||
928 | +/* Equality comparisons. */ | ||
929 | + | ||
930 | +#undef FUNCTION_NAME | ||
931 | +#define FUNCTION_NAME iseleq | ||
932 | + | ||
933 | +SIGNED_PROTO | ||
934 | +{ | ||
935 | + /* Mismatches in argument type. */ | ||
936 | + ISEL_BUILTIN ((unsigned int) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
937 | + ISEL_BUILTIN (x, (unsigned int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
938 | + ISEL_BUILTIN ((int *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
939 | + ISEL_BUILTIN (p, (int *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
940 | + /* Mismatches in return type. */ | ||
941 | + ISEL_BUILTIN (x, y, (unsigned int) a, b); /* { dg-error "isel intrinsic" } */ | ||
942 | + ISEL_BUILTIN (x, y, a, (unsigned int) b); /* { dg-error "isel intrinsic" } */ | ||
943 | + ISEL_BUILTIN (x, y, (int *) p, q); /* { dg-error "isel intrinsic" } */ | ||
944 | + ISEL_BUILTIN (x, y, p, (int *) q); /* { dg-error "isel intrinsic" } */ | ||
945 | +} | ||
946 | + | ||
947 | +/* less-than, greater-than. */ | ||
948 | + | ||
949 | +#undef FUNCTION_NAME | ||
950 | +#define FUNCTION_NAME isellt | ||
951 | + | ||
952 | +SIGNED_PROTO | ||
953 | +{ | ||
954 | + /* Unsigned comparison should be done with the *u variants. */ | ||
955 | + ISEL_BUILTIN ((unsigned int) x, (unsigned int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
956 | + /* So should pointer comparison. */ | ||
957 | + ISEL_BUILTIN (p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
958 | + /* Mismatches in argument type. */ | ||
959 | + ISEL_BUILTIN ((unsigned int) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
960 | + ISEL_BUILTIN (x, (unsigned int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
961 | + ISEL_BUILTIN ((int *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
962 | + ISEL_BUILTIN (p, (int *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
963 | + /* Mismatches in return type. */ | ||
964 | + ISEL_BUILTIN (x, y, (unsigned int) a, b); /* { dg-error "isel intrinsic" } */ | ||
965 | + ISEL_BUILTIN (x, y, a, (unsigned int) b); /* { dg-error "isel intrinsic" } */ | ||
966 | + ISEL_BUILTIN (x, y, (int *) p, q); /* { dg-error "isel intrinsic" } */ | ||
967 | + ISEL_BUILTIN (x, y, p, (int *) q); /* { dg-error "isel intrinsic" } */ | ||
968 | +} | ||
969 | + | ||
970 | +#undef FUNCTION_NAME | ||
971 | +#define FUNCTION_NAME iselgt | ||
972 | + | ||
973 | +SIGNED_PROTO | ||
974 | +{ | ||
975 | + /* Unsigned comparison should be done with the *u variants. */ | ||
976 | + ISEL_BUILTIN ((unsigned int) x, (unsigned int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
977 | + /* So should pointer comparison. */ | ||
978 | + ISEL_BUILTIN (p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
979 | + /* Mismatches in argument type. */ | ||
980 | + ISEL_BUILTIN ((unsigned int) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
981 | + ISEL_BUILTIN (x, (unsigned int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
982 | + ISEL_BUILTIN ((int *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
983 | + ISEL_BUILTIN (p, (int *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
984 | + /* Mismatches in return type. */ | ||
985 | + ISEL_BUILTIN (x, y, (unsigned int) a, b); /* { dg-error "isel intrinsic" } */ | ||
986 | + ISEL_BUILTIN (x, y, a, (unsigned int) b); /* { dg-error "isel intrinsic" } */ | ||
987 | + ISEL_BUILTIN (x, y, (int *) p, q); /* { dg-error "isel intrinsic" } */ | ||
988 | + ISEL_BUILTIN (x, y, p, (int *) q); /* { dg-error "isel intrinsic" } */ | ||
989 | +} | ||
990 | + | ||
991 | +/* Unsigned variants. These permit unsigned and pointer operands for | ||
992 | + comparison only. */ | ||
993 | + | ||
994 | +#undef FUNCTION_NAME | ||
995 | +#define FUNCTION_NAME iselltu | ||
996 | + | ||
997 | +UNSIGNED_PROTO | ||
998 | +{ | ||
999 | + /* Signed comparison should be done with the signed variants. */ | ||
1000 | + ISEL_BUILTIN ((int) x, (int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
1001 | + /* Mismatches in argument type. */ | ||
1002 | + ISEL_BUILTIN ((int) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
1003 | + ISEL_BUILTIN (x, (int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
1004 | + ISEL_BUILTIN ((int *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
1005 | + ISEL_BUILTIN (p, (int *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
1006 | + /* Mismatches in return type. */ | ||
1007 | + ISEL_BUILTIN (x, y, (unsigned int) a, b); /* { dg-error "isel intrinsic" } */ | ||
1008 | + ISEL_BUILTIN (x, y, a, (unsigned int) b); /* { dg-error "isel intrinsic" } */ | ||
1009 | + ISEL_BUILTIN (x, y, (int *) p, q); /* { dg-error "isel intrinsic" } */ | ||
1010 | + ISEL_BUILTIN (x, y, p, (int *) q); /* { dg-error "isel intrinsic" } */ | ||
1011 | +} | ||
1012 | + | ||
1013 | +#undef FUNCTION_NAME | ||
1014 | +#define FUNCTION_NAME iselgtu | ||
1015 | + | ||
1016 | +UNSIGNED_PROTO | ||
1017 | +{ | ||
1018 | + /* Signed comparison should be done with the signed variants. */ | ||
1019 | + ISEL_BUILTIN ((int) x, (int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
1020 | + /* Mismatches in argument type. */ | ||
1021 | + ISEL_BUILTIN ((int) x, y, a, b); /* { dg-error "isel intrinsic" } */ | ||
1022 | + ISEL_BUILTIN (x, (int) y, a, b); /* { dg-error "isel intrinsic" } */ | ||
1023 | + ISEL_BUILTIN ((int *) p, q, a, b); /* { dg-error "isel intrinsic" } */ | ||
1024 | + ISEL_BUILTIN (p, (int *) q, a, b); /* { dg-error "isel intrinsic" } */ | ||
1025 | + /* Mismatches in return type. */ | ||
1026 | + ISEL_BUILTIN (x, y, (unsigned int) a, b); /* { dg-error "isel intrinsic" } */ | ||
1027 | + ISEL_BUILTIN (x, y, a, (unsigned int) b); /* { dg-error "isel intrinsic" } */ | ||
1028 | + ISEL_BUILTIN (x, y, (int *) p, q); /* { dg-error "isel intrinsic" } */ | ||
1029 | + ISEL_BUILTIN (x, y, p, (int *) q); /* { dg-error "isel intrinsic" } */ | ||
1030 | +} | ||
1031 | diff -ruN gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel.h gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel.h | ||
1032 | --- gcc-4.6.0-orig/gcc/testsuite/gcc.target/powerpc/builtin-isel.h 1969-12-31 18:00:00.000000000 -0600 | ||
1033 | +++ gcc-4.6.0-new/gcc/testsuite/gcc.target/powerpc/builtin-isel.h 2011-07-25 12:27:55.483942000 -0500 | ||
1034 | @@ -0,0 +1,25 @@ | ||
1035 | +/* Common definitions for builtin isel testing. */ | ||
1036 | + | ||
1037 | +#define SIGNED_ARGLIST (int x, int y, int a, int b, void *p, void *q) | ||
1038 | +#define UNSIGNED_ARGLIST (unsigned int x, unsigned int y, \ | ||
1039 | + int a, int b, void *p, void *q) | ||
1040 | + | ||
1041 | +#define SIGNED_PROTO void FUNCTION_NAME SIGNED_ARGLIST | ||
1042 | +#define UNSIGNED_PROTO void FUNCTION_NAME UNSIGNED_ARGLIST | ||
1043 | + | ||
1044 | +#define SIGNED64_ARGLIST (long x, long y, long a, long b, void *p, void *q) | ||
1045 | +#define UNSIGNED64_ARGLIST (unsigned long x, unsigned long y, \ | ||
1046 | + long a, long b, void *p, void *q) | ||
1047 | + | ||
1048 | +#define SIGNED64_PROTO void FUNCTION_NAME SIGNED64_ARGLIST | ||
1049 | +#define UNSIGNED64_PROTO void FUNCTION_NAME UNSIGNED64_ARGLIST | ||
1050 | + | ||
1051 | +#define CONCAT2(X,Y) X##Y | ||
1052 | +#define CONCAT(X,Y) CONCAT2(X, Y) | ||
1053 | +#define ISEL_BUILTIN CONCAT(__builtin_, FUNCTION_NAME) | ||
1054 | + | ||
1055 | +volatile int i; | ||
1056 | +volatile unsigned int u; | ||
1057 | +volatile void *r; | ||
1058 | +volatile long L; | ||
1059 | +volatile unsigned long U; | ||
diff --git a/recipes-devtools/gcc/files/gcc.case_values.patch b/recipes-devtools/gcc/files/gcc.case_values.patch new file mode 100644 index 0000000..5be766d --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.case_values.patch | |||
@@ -0,0 +1,65 @@ | |||
1 | --- gcc-4.6.0/gcc/params.def-orig 2011-06-16 11:39:42.412634260 -0500 | ||
2 | +++ gcc-4.6.0/gcc/params.def 2011-06-16 11:41:29.457630886 -0500 | ||
3 | @@ -39,6 +39,11 @@ | ||
4 | |||
5 | Be sure to add an entry to invoke.texi summarizing the parameter. */ | ||
6 | |||
7 | +DEFPARAM (PARAM_CASE_VALUES_THRESHOLD, | ||
8 | + "case-values-threshold", | ||
9 | + "Minimum number of case statements for each a jump table will be used", | ||
10 | + 4, 4, 1000) | ||
11 | + | ||
12 | /* The threshold ratio between current and hottest structure counts. | ||
13 | We say that if the ratio of the current structure count, | ||
14 | calculated by profiling, to the hottest structure count | ||
15 | --- gcc-4.6.0/gcc/config/rs6000/rs6000.c-orig 2011-06-16 12:24:03.440630751 -0500 | ||
16 | +++ gcc-4.6.0/gcc/config/rs6000/rs6000.c 2011-06-16 12:24:51.450630163 -0500 | ||
17 | @@ -1282,6 +1282,7 @@ | ||
18 | struct cl_target_option *); | ||
19 | static bool rs6000_can_inline_p (tree, tree); | ||
20 | static void rs6000_set_current_function (tree); | ||
21 | +static unsigned int rs6000_case_values_threshold (void); | ||
22 | |||
23 | |||
24 | /* Default register names. */ | ||
25 | --- gcc-4.6.0/gcc/config/rs6000/rs6000.c-orig 2011-06-16 11:18:27.131631000 -0500 | ||
26 | +++ gcc-4.6.0/gcc/config/rs6000/rs6000.c 2011-06-16 11:38:15.225631714 -0500 | ||
27 | @@ -1704,6 +1704,9 @@ | ||
28 | #undef TARGET_SET_CURRENT_FUNCTION | ||
29 | #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function | ||
30 | |||
31 | +#undef TARGET_CASE_VALUES_THRESHOLD | ||
32 | +#define TARGET_CASE_VALUES_THRESHOLD rs6000_case_values_threshold | ||
33 | + | ||
34 | struct gcc_target targetm = TARGET_INITIALIZER; | ||
35 | |||
36 | |||
37 | @@ -28179,6 +28182,12 @@ | ||
38 | } | ||
39 | |||
40 | |||
41 | +static unsigned int | ||
42 | +rs6000_case_values_threshold (void) | ||
43 | +{ | ||
44 | + return PARAM_VALUE (PARAM_CASE_VALUES_THRESHOLD); | ||
45 | +} | ||
46 | + | ||
47 | /* Save the current options */ | ||
48 | |||
49 | static void | ||
50 | --- gcc-4.6.0/gcc/config/rs6000/rs6000.c-orig 2011-06-17 12:19:00.463631000 -0500 | ||
51 | +++ gcc-4.6.0/gcc/config/rs6000/rs6000.c 2011-06-17 12:06:28.904630840 -0500 | ||
52 | @@ -2906,6 +2906,13 @@ | ||
53 | if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32)) | ||
54 | rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32); | ||
55 | |||
56 | + if ((rs6000_cpu == PROCESSOR_PPC8540 | ||
57 | + || rs6000_cpu == PROCESSOR_PPCE500MC | ||
58 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
59 | + || rs6000_cpu == PROCESSOR_PPCE6500) | ||
60 | + && global_options_set.x_param_values[(int) PARAM_CASE_VALUES_THRESHOLD] != true) | ||
61 | + global_options.x_param_values[(int) PARAM_CASE_VALUES_THRESHOLD] = 8; | ||
62 | + | ||
63 | if (global_init_p) | ||
64 | { | ||
65 | /* If the appropriate debug option is enabled, replace the target hooks | ||
diff --git a/recipes-devtools/gcc/files/gcc.check_path_validity.patch b/recipes-devtools/gcc/files/gcc.check_path_validity.patch new file mode 100644 index 0000000..5d70a39 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.check_path_validity.patch | |||
@@ -0,0 +1,12 @@ | |||
1 | --- gcc-4_6-branch/gcc/Makefile.in.orig 2012-03-06 01:10:15.277196930 -0600 | ||
2 | +++ gcc-4_6-branch/gcc/Makefile.in 2012-03-06 01:10:54.083378912 -0600 | ||
3 | @@ -4170,6 +4170,9 @@ | ||
4 | else \ | ||
5 | set -e; for ml in `cat fixinc_list`; do \ | ||
6 | sysroot_headers_suffix=`echo $${ml} | sed -e 's/;.*$$//'`; \ | ||
7 | + if test "x$${sysroot_headers_suffix}" = "x"; then \ | ||
8 | + continue; \ | ||
9 | + fi; \ | ||
10 | multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \ | ||
11 | fix_dir=include-fixed$${multi_dir}; \ | ||
12 | if ! $(inhibit_libc) && test ! -d ${SYSTEM_HEADER_DIR}; then \ | ||
diff --git a/recipes-devtools/gcc/files/gcc.e5500_mfocr.patch b/recipes-devtools/gcc/files/gcc.e5500_mfocr.patch new file mode 100644 index 0000000..16b3538 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.e5500_mfocr.patch | |||
@@ -0,0 +1,181 @@ | |||
1 | # Problem: Although gcc is prepared to avoid "mfocr" instructions | ||
2 | (which takes 5 cycles in our parts and 2 cycles on IBM parts). This | ||
3 | instruction is used on the mentioned program. What is suspicious | ||
4 | about it, is that the code compiled for 32 bits does not use the | ||
5 | instruction. So, it could be a omission in the previous | ||
6 | implementation, or a bug, or a new opportunity. | ||
7 | # Reported by: Performance team (PARC) | ||
8 | # Owned by: Ping Hu | ||
9 | # Action: | ||
10 | * 'mfocr' flag problem: that 'mfocr' flag was uncorrectly set for E5500, | ||
11 | which caused the 'mfocr' instructions generated even on E5500. | ||
12 | * avoid generating 'mfcr' and 'mfocr' instructions: due to the fact | ||
13 | that both instructions are expensive on Freescale processors. | ||
14 | * A target specific flag, -mslow-mfocr, can be used to avoid generating | ||
15 | 'mfcr' and 'mfocr' instructions in 64-bit mode, thus restoring legacy | ||
16 | operations if desired. | ||
17 | |||
18 | diff -ruN gcc-4.6.2-clean/gcc/config/rs6000/rs6000.c gcc-4.6.2/gcc/config/rs6000/rs6000.c | ||
19 | --- gcc-4.6.2-clean/gcc/config/rs6000/rs6000.c 2011-11-22 11:11:47.479144000 -0600 | ||
20 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.c 2011-11-29 16:23:45.074279998 -0600 | ||
21 | @@ -1885,6 +1885,7 @@ | ||
22 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64} | ||
23 | }; | ||
24 | |||
25 | + | ||
26 | /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the | ||
27 | name is invalid. */ | ||
28 | |||
29 | @@ -2902,6 +2903,10 @@ | ||
30 | || rs6000_cpu == PROCESSOR_PPCE6500) | ||
31 | target_flags &= ~MASK_PPC_GPOPT; | ||
32 | |||
33 | + if (rs6000_cpu == PROCESSOR_PPCE5500) | ||
34 | + target_flags &= ~MASK_MFCRF; | ||
35 | + | ||
36 | + | ||
37 | /* store_one_arg depends on expand_block_move to handle at least the | ||
38 | size of reg_parm_stack_space. */ | ||
39 | if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32)) | ||
40 | diff -ruN gcc-4.6.2-clean/gcc/config/rs6000/rs6000.md gcc-4.6.2/gcc/config/rs6000/rs6000.md | ||
41 | --- gcc-4.6.2-clean/gcc/config/rs6000/rs6000.md 2011-11-22 11:11:47.036144001 -0600 | ||
42 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.md 2011-11-29 16:24:04.705280001 -0600 | ||
43 | @@ -215,6 +215,8 @@ | ||
44 | ; (one with a '.') will compare; and the size used for arithmetic carries. | ||
45 | (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) | ||
46 | |||
47 | +(define_mode_iterator P2 [(SI "TARGET_32BIT || TARGET_SLOW_MFOCR") (DI "TARGET_64BIT")]) | ||
48 | + | ||
49 | ; Any hardware-supported floating-point mode | ||
50 | (define_mode_iterator FP [ | ||
51 | (SF "TARGET_HARD_FLOAT | ||
52 | @@ -2208,9 +2210,9 @@ | ||
53 | |||
54 | (define_insn "" | ||
55 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | ||
56 | - (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) | ||
57 | + (compare:CC (neg:P2 (match_operand:P2 1 "gpc_reg_operand" "r,r")) | ||
58 | (const_int 0))) | ||
59 | - (clobber (match_scratch:P 2 "=r,r"))] | ||
60 | + (clobber (match_scratch:P2 2 "=r,r"))] | ||
61 | "" | ||
62 | "@ | ||
63 | neg. %2,%1 | ||
64 | @@ -2220,12 +2222,12 @@ | ||
65 | |||
66 | (define_split | ||
67 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | ||
68 | - (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) | ||
69 | + (compare:CC (neg:P2 (match_operand:P2 1 "gpc_reg_operand" "")) | ||
70 | (const_int 0))) | ||
71 | - (clobber (match_scratch:P 2 ""))] | ||
72 | + (clobber (match_scratch:P2 2 ""))] | ||
73 | "reload_completed" | ||
74 | [(set (match_dup 2) | ||
75 | - (neg:P (match_dup 1))) | ||
76 | + (neg:P2 (match_dup 1))) | ||
77 | (set (match_dup 0) | ||
78 | (compare:CC (match_dup 2) | ||
79 | (const_int 0)))] | ||
80 | @@ -2233,10 +2235,10 @@ | ||
81 | |||
82 | (define_insn "" | ||
83 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | ||
84 | - (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) | ||
85 | + (compare:CC (neg:P2 (match_operand:P2 1 "gpc_reg_operand" "r,r")) | ||
86 | (const_int 0))) | ||
87 | - (set (match_operand:P 0 "gpc_reg_operand" "=r,r") | ||
88 | - (neg:P (match_dup 1)))] | ||
89 | + (set (match_operand:P2 0 "gpc_reg_operand" "=r,r") | ||
90 | + (neg:P2 (match_dup 1)))] | ||
91 | "" | ||
92 | "@ | ||
93 | neg. %0,%1 | ||
94 | @@ -2246,13 +2248,13 @@ | ||
95 | |||
96 | (define_split | ||
97 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | ||
98 | - (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) | ||
99 | + (compare:CC (neg:P2 (match_operand:P2 1 "gpc_reg_operand" "")) | ||
100 | (const_int 0))) | ||
101 | - (set (match_operand:P 0 "gpc_reg_operand" "") | ||
102 | - (neg:P (match_dup 1)))] | ||
103 | + (set (match_operand:P2 0 "gpc_reg_operand" "") | ||
104 | + (neg:P2 (match_dup 1)))] | ||
105 | "reload_completed" | ||
106 | [(set (match_dup 0) | ||
107 | - (neg:P (match_dup 1))) | ||
108 | + (neg:P2 (match_dup 1))) | ||
109 | (set (match_dup 2) | ||
110 | (compare:CC (match_dup 0) | ||
111 | (const_int 0)))] | ||
112 | @@ -15286,31 +15288,31 @@ | ||
113 | [(set_attr "length" "12")]) | ||
114 | |||
115 | (define_insn_and_split "*gtu<mode>" | ||
116 | - [(set (match_operand:P 0 "gpc_reg_operand" "=r") | ||
117 | - (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") | ||
118 | - (match_operand:P 2 "reg_or_short_operand" "rI")))] | ||
119 | + [(set (match_operand:P2 0 "gpc_reg_operand" "=r") | ||
120 | + (gtu:P2 (match_operand:P2 1 "gpc_reg_operand" "r") | ||
121 | + (match_operand:P2 2 "reg_or_short_operand" "rI")))] | ||
122 | "" | ||
123 | "#" | ||
124 | "" | ||
125 | - [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) | ||
126 | - (set (match_dup 0) (neg:P (match_dup 0)))] | ||
127 | + [(set (match_dup 0) (neg:P2 (gtu:P2 (match_dup 1) (match_dup 2)))) | ||
128 | + (set (match_dup 0) (neg:P2 (match_dup 0)))] | ||
129 | "") | ||
130 | |||
131 | (define_insn_and_split "*gtu<mode>_compare" | ||
132 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | ||
133 | (compare:CC | ||
134 | - (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | ||
135 | - (match_operand:P 2 "reg_or_short_operand" "rI,rI")) | ||
136 | + (gtu:P2 (match_operand:P2 1 "gpc_reg_operand" "r,r") | ||
137 | + (match_operand:P2 2 "reg_or_short_operand" "rI,rI")) | ||
138 | (const_int 0))) | ||
139 | - (set (match_operand:P 0 "gpc_reg_operand" "=r,r") | ||
140 | - (gtu:P (match_dup 1) (match_dup 2)))] | ||
141 | + (set (match_operand:P2 0 "gpc_reg_operand" "=r,r") | ||
142 | + (gtu:P2 (match_dup 1) (match_dup 2)))] | ||
143 | "" | ||
144 | "#" | ||
145 | "" | ||
146 | - [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) | ||
147 | + [(set (match_dup 0) (neg:P2 (gtu:P2 (match_dup 1) (match_dup 2)))) | ||
148 | (parallel [(set (match_dup 3) | ||
149 | - (compare:CC (neg:P (match_dup 0)) (const_int 0))) | ||
150 | - (set (match_dup 0) (neg:P (match_dup 0)))])] | ||
151 | + (compare:CC (neg:P2 (match_dup 0)) (const_int 0))) | ||
152 | + (set (match_dup 0) (neg:P2 (match_dup 0)))])] | ||
153 | "") | ||
154 | |||
155 | (define_insn_and_split "*plus_gtu<mode>" | ||
156 | @@ -15345,9 +15347,9 @@ | ||
157 | "") | ||
158 | |||
159 | (define_insn "*neg_gtu<mode>" | ||
160 | - [(set (match_operand:P 0 "gpc_reg_operand" "=r") | ||
161 | - (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") | ||
162 | - (match_operand:P 2 "reg_or_short_operand" "rI"))))] | ||
163 | + [(set (match_operand:P2 0 "gpc_reg_operand" "=r") | ||
164 | + (neg:P2 (gtu:P2 (match_operand:P2 1 "gpc_reg_operand" "r") | ||
165 | + (match_operand:P2 2 "reg_or_short_operand" "rI"))))] | ||
166 | "" | ||
167 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" | ||
168 | [(set_attr "type" "two") | ||
169 | --- gcc-4.6.2-clean/gcc/config/rs6000/rs6000.opt 2011-11-22 11:11:47.480143999 -0600 | ||
170 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.opt 2011-11-29 16:24:16.322280634 -0600 | ||
171 | @@ -381,6 +381,10 @@ | ||
172 | Target | ||
173 | Generate SPE SIMD instructions on E500 | ||
174 | |||
175 | +mslow-mfocr | ||
176 | +Target Report Var(TARGET_SLOW_MFOCR) | ||
177 | +Generate slow mfocr instructions | ||
178 | + | ||
179 | mpaired | ||
180 | Target Var(rs6000_paired_float) Save | ||
181 | Generate PPC750CL paired-single instructions | ||
diff --git a/recipes-devtools/gcc/files/gcc.e6500-FSF46.patch b/recipes-devtools/gcc/files/gcc.e6500-FSF46.patch new file mode 100644 index 0000000..f9fa33d --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.e6500-FSF46.patch | |||
@@ -0,0 +1,4011 @@ | |||
1 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/altivec.h gcc-4.6.2/gcc/config/rs6000/altivec.h | ||
2 | --- gcc-4.6.2-orig/gcc/config/rs6000/altivec.h 2011-02-02 23:42:19.000000000 -0600 | ||
3 | +++ gcc-4.6.2/gcc/config/rs6000/altivec.h 2012-03-06 12:33:43.943038996 -0600 | ||
4 | @@ -322,6 +322,30 @@ | ||
5 | #define vec_vsx_st __builtin_vec_vsx_st | ||
6 | #endif | ||
7 | |||
8 | +#ifdef __ALTIVEC2__ | ||
9 | +/* New Altivec instructions */ | ||
10 | +#define vec_absd __builtin_vec_absd | ||
11 | +#define vec_lvexbx __builtin_vec_lvexbx | ||
12 | +#define vec_lvexhx __builtin_vec_lvexhx | ||
13 | +#define vec_lvexwx __builtin_vec_lvexwx | ||
14 | +#define vec_stvexbx __builtin_vec_stvexbx | ||
15 | +#define vec_stvexhx __builtin_vec_stvexhx | ||
16 | +#define vec_stvexwx __builtin_vec_stvexwx | ||
17 | +#define vec_lvswx __builtin_vec_lvswx | ||
18 | +#define vec_lvswxl __builtin_vec_lvswxl | ||
19 | +#define vec_stvswx __builtin_vec_stvswx | ||
20 | +#define vec_stvswxl __builtin_vec_stvswxl | ||
21 | +#define vec_lvsm __builtin_vec_lvsm | ||
22 | +#define vec_lvtlx __builtin_vec_lvtlx | ||
23 | +#define vec_lvtlxl __builtin_vec_lvtlxl | ||
24 | +#define vec_lvtrx __builtin_vec_lvtrx | ||
25 | +#define vec_lvtrxl __builtin_vec_lvtrxl | ||
26 | +#define vec_stvflx __builtin_vec_stvflx | ||
27 | +#define vec_stvflxl __builtin_vec_stvflxl | ||
28 | +#define vec_stvfrx __builtin_vec_stvfrx | ||
29 | +#define vec_stvfrxl __builtin_vec_stvfrxl | ||
30 | +#endif | ||
31 | + | ||
32 | /* Predicates. | ||
33 | For C++, we use templates in order to allow non-parenthesized arguments. | ||
34 | For C, instead, we use macros since non-parenthesized arguments were | ||
35 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/altivec.md gcc-4.6.2/gcc/config/rs6000/altivec.md | ||
36 | --- gcc-4.6.2-orig/gcc/config/rs6000/altivec.md 2011-07-08 15:10:18.000000000 -0500 | ||
37 | +++ gcc-4.6.2/gcc/config/rs6000/altivec.md 2012-03-06 12:24:35.058038999 -0600 | ||
38 | @@ -91,9 +91,11 @@ | ||
39 | (UNSPEC_LVSL 194) | ||
40 | (UNSPEC_LVSR 195) | ||
41 | (UNSPEC_LVE 196) | ||
42 | + (UNSPEC_LVEX 197) | ||
43 | (UNSPEC_STVX 201) | ||
44 | (UNSPEC_STVXL 202) | ||
45 | (UNSPEC_STVE 203) | ||
46 | + (UNSPEC_STVEX 204) | ||
47 | (UNSPEC_SET_VSCR 213) | ||
48 | (UNSPEC_GET_VRSAVE 214) | ||
49 | (UNSPEC_LVX 215) | ||
50 | @@ -123,6 +125,19 @@ | ||
51 | (UNSPEC_STVLXL 241) | ||
52 | (UNSPEC_STVRX 242) | ||
53 | (UNSPEC_STVRXL 243) | ||
54 | + (UNSPEC_LVTLX 244) | ||
55 | + (UNSPEC_LVTLXL 245) | ||
56 | + (UNSPEC_LVTRX 246) | ||
57 | + (UNSPEC_LVTRXL 247) | ||
58 | + (UNSPEC_STVFLX 248) | ||
59 | + (UNSPEC_STVFLXL 249) | ||
60 | + (UNSPEC_STVFRX 250) | ||
61 | + (UNSPEC_STVFRXL 251) | ||
62 | + (UNSPEC_LVSWX 252) | ||
63 | + (UNSPEC_LVSWXL 253) | ||
64 | + (UNSPEC_LVSM 254) | ||
65 | + (UNSPEC_STVSWX 255) | ||
66 | + (UNSPEC_STVSWXL 256) | ||
67 | (UNSPEC_VMULWHUB 308) | ||
68 | (UNSPEC_VMULWLUB 309) | ||
69 | (UNSPEC_VMULWHSB 310) | ||
70 | @@ -143,6 +158,9 @@ | ||
71 | (UNSPEC_VUPKLS_V4SF 325) | ||
72 | (UNSPEC_VUPKHU_V4SF 326) | ||
73 | (UNSPEC_VUPKLU_V4SF 327) | ||
74 | + (UNSPEC_VABSDUB 328) | ||
75 | + (UNSPEC_VABSDUH 329) | ||
76 | + (UNSPEC_VABSDUW 330) | ||
77 | ]) | ||
78 | |||
79 | (define_constants | ||
80 | @@ -323,6 +341,34 @@ | ||
81 | |||
82 | ;; Simple binary operations. | ||
83 | |||
84 | +;; absd | ||
85 | +(define_insn "altivec_vabsduw" | ||
86 | + [(set (match_operand:V4SI 0 "register_operand" "=v") | ||
87 | + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | ||
88 | + (match_operand:V4SI 2 "register_operand" "v")] | ||
89 | + UNSPEC_VABSDUW))] | ||
90 | + "TARGET_ALTIVEC2" | ||
91 | + "vabsduw %0,%1,%2" | ||
92 | + [(set_attr "type" "vecsimple")]) | ||
93 | + | ||
94 | +(define_insn "altivec_vabsduh" | ||
95 | + [(set (match_operand:V8HI 0 "register_operand" "=v") | ||
96 | + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | ||
97 | + (match_operand:V8HI 2 "register_operand" "v")] | ||
98 | + UNSPEC_VABSDUH))] | ||
99 | + "TARGET_ALTIVEC2" | ||
100 | + "vabsduh %0,%1,%2" | ||
101 | + [(set_attr "type" "vecsimple")]) | ||
102 | + | ||
103 | +(define_insn "altivec_vabsdub" | ||
104 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
105 | + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | ||
106 | + (match_operand:V16QI 2 "register_operand" "v")] | ||
107 | + UNSPEC_VABSDUB))] | ||
108 | + "TARGET_ALTIVEC2" | ||
109 | + "vabsdub %0,%1,%2" | ||
110 | + [(set_attr "type" "vecsimple")]) | ||
111 | + | ||
112 | ;; add | ||
113 | (define_insn "add<mode>3" | ||
114 | [(set (match_operand:VI 0 "register_operand" "=v") | ||
115 | @@ -1741,6 +1787,15 @@ | ||
116 | "lvewx %0,%y1" | ||
117 | [(set_attr "type" "vecload")]) | ||
118 | |||
119 | +(define_insn "altivec_lvex<VI_char>x" | ||
120 | + [(parallel | ||
121 | + [(set (match_operand:VI 0 "register_operand" "=v") | ||
122 | + (match_operand:VI 1 "memory_operand" "Z")) | ||
123 | + (unspec [(const_int 0)] UNSPEC_LVEX)])] | ||
124 | + "TARGET_ALTIVEC2" | ||
125 | + "lvex<VI_char>x %0,%y1" | ||
126 | + [(set_attr "type" "vecload")]) | ||
127 | + | ||
128 | (define_insn "altivec_lvxl" | ||
129 | [(parallel | ||
130 | [(set (match_operand:V4SI 0 "register_operand" "=v") | ||
131 | @@ -1791,6 +1846,13 @@ | ||
132 | "stvewx %1,%y0" | ||
133 | [(set_attr "type" "vecstore")]) | ||
134 | |||
135 | +(define_insn "altivec_stvex<VI_char>x" | ||
136 | + [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z") | ||
137 | + (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVEX))] | ||
138 | + "TARGET_ALTIVEC2" | ||
139 | + "stvex<VI_char>x %1,%y0" | ||
140 | + [(set_attr "type" "vecstore")]) | ||
141 | + | ||
142 | ;; Generate | ||
143 | ;; vspltis? SCRATCH0,0 | ||
144 | ;; vsubu?m SCRATCH2,SCRATCH1,%1 | ||
145 | @@ -2358,7 +2420,7 @@ | ||
146 | DONE; | ||
147 | }") | ||
148 | |||
149 | -;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL, | ||
150 | +;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX1, LVRXL, | ||
151 | ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell. | ||
152 | (define_insn "altivec_lvlx" | ||
153 | [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
154 | @@ -2394,8 +2456,8 @@ | ||
155 | |||
156 | (define_insn "altivec_stvlx" | ||
157 | [(parallel | ||
158 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
159 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
160 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
161 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
162 | (unspec [(const_int 0)] UNSPEC_STVLX)])] | ||
163 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
164 | "stvlx %1,%y0" | ||
165 | @@ -2403,8 +2465,8 @@ | ||
166 | |||
167 | (define_insn "altivec_stvlxl" | ||
168 | [(parallel | ||
169 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
170 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
171 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
172 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
173 | (unspec [(const_int 0)] UNSPEC_STVLXL)])] | ||
174 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
175 | "stvlxl %1,%y0" | ||
176 | @@ -2412,8 +2474,8 @@ | ||
177 | |||
178 | (define_insn "altivec_stvrx" | ||
179 | [(parallel | ||
180 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
181 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
182 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
183 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
184 | (unspec [(const_int 0)] UNSPEC_STVRX)])] | ||
185 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
186 | "stvrx %1,%y0" | ||
187 | @@ -2421,13 +2483,123 @@ | ||
188 | |||
189 | (define_insn "altivec_stvrxl" | ||
190 | [(parallel | ||
191 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
192 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
193 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
194 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
195 | (unspec [(const_int 0)] UNSPEC_STVRXL)])] | ||
196 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
197 | "stvrxl %1,%y0" | ||
198 | [(set_attr "type" "vecstore")]) | ||
199 | |||
200 | +(define_insn "altivec_lvtlx" | ||
201 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
202 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
203 | + UNSPEC_LVTLX))] | ||
204 | + "TARGET_ALTIVEC2" | ||
205 | + "lvtlx %0,%y1" | ||
206 | + [(set_attr "type" "vecload")]) | ||
207 | + | ||
208 | +(define_insn "altivec_lvtlxl" | ||
209 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
210 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
211 | + UNSPEC_LVTLXL))] | ||
212 | + "TARGET_ALTIVEC2" | ||
213 | + "lvtlxl %0,%y1" | ||
214 | + [(set_attr "type" "vecload")]) | ||
215 | + | ||
216 | +(define_insn "altivec_lvtrx" | ||
217 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
218 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
219 | + UNSPEC_LVTRX))] | ||
220 | + "TARGET_ALTIVEC2" | ||
221 | + "lvtrx %0,%y1" | ||
222 | + [(set_attr "type" "vecload")]) | ||
223 | + | ||
224 | +(define_insn "altivec_lvtrxl" | ||
225 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
226 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
227 | + UNSPEC_LVTRXL))] | ||
228 | + "TARGET_ALTIVEC2" | ||
229 | + "lvtrxl %0,%y1" | ||
230 | + [(set_attr "type" "vecload")]) | ||
231 | + | ||
232 | +(define_insn "altivec_stvflx" | ||
233 | + [(parallel | ||
234 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
235 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
236 | + (unspec [(const_int 0)] UNSPEC_STVFLX)])] | ||
237 | + "TARGET_ALTIVEC2" | ||
238 | + "stvflx %1,%y0" | ||
239 | + [(set_attr "type" "vecstore")]) | ||
240 | + | ||
241 | +(define_insn "altivec_stvflxl" | ||
242 | + [(parallel | ||
243 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
244 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
245 | + (unspec [(const_int 0)] UNSPEC_STVFLXL)])] | ||
246 | + "TARGET_ALTIVEC2" | ||
247 | + "stvflxl %1,%y0" | ||
248 | + [(set_attr "type" "vecstore")]) | ||
249 | + | ||
250 | +(define_insn "altivec_stvfrx" | ||
251 | + [(parallel | ||
252 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
253 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
254 | + (unspec [(const_int 0)] UNSPEC_STVFRX)])] | ||
255 | + "TARGET_ALTIVEC2" | ||
256 | + "stvfrx %1,%y0" | ||
257 | + [(set_attr "type" "vecstore")]) | ||
258 | + | ||
259 | +(define_insn "altivec_stvfrxl" | ||
260 | + [(parallel | ||
261 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
262 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
263 | + (unspec [(const_int 0)] UNSPEC_STVFRXL)])] | ||
264 | + "TARGET_ALTIVEC2" | ||
265 | + "stvfrxl %1,%y0" | ||
266 | + [(set_attr "type" "vecstore")]) | ||
267 | + | ||
268 | +(define_insn "altivec_lvswx" | ||
269 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
270 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
271 | + UNSPEC_LVSWX))] | ||
272 | + "TARGET_ALTIVEC2" | ||
273 | + "lvswx %0,%y1" | ||
274 | + [(set_attr "type" "vecload")]) | ||
275 | + | ||
276 | +(define_insn "altivec_lvswxl" | ||
277 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
278 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
279 | + UNSPEC_LVSWXL))] | ||
280 | + "TARGET_ALTIVEC2" | ||
281 | + "lvswxl %0,%y1" | ||
282 | + [(set_attr "type" "vecload")]) | ||
283 | + | ||
284 | +(define_insn "altivec_lvsm" | ||
285 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
286 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
287 | + UNSPEC_LVSM))] | ||
288 | + "TARGET_ALTIVEC2" | ||
289 | + "lvsm %0,%y1" | ||
290 | + [(set_attr "type" "vecload")]) | ||
291 | + | ||
292 | +(define_insn "altivec_stvswx" | ||
293 | + [(parallel | ||
294 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
295 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
296 | + (unspec [(const_int 0)] UNSPEC_STVSWX)])] | ||
297 | + "TARGET_ALTIVEC2" | ||
298 | + "stvswx %1,%y0" | ||
299 | + [(set_attr "type" "vecstore")]) | ||
300 | + | ||
301 | +(define_insn "altivec_stvswxl" | ||
302 | + [(parallel | ||
303 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
304 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
305 | + (unspec [(const_int 0)] UNSPEC_STVSWXL)])] | ||
306 | + "TARGET_ALTIVEC2" | ||
307 | + "stvswxl %1,%y0" | ||
308 | + [(set_attr "type" "vecstore")]) | ||
309 | + | ||
310 | (define_expand "vec_extract_evenv4si" | ||
311 | [(set (match_operand:V4SI 0 "register_operand" "") | ||
312 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") | ||
313 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/e5500.md gcc-4.6.2/gcc/config/rs6000/e5500.md | ||
314 | --- gcc-4.6.2-orig/gcc/config/rs6000/e5500.md 1969-12-31 18:00:00.000000000 -0600 | ||
315 | +++ gcc-4.6.2/gcc/config/rs6000/e5500.md 2012-03-06 12:16:07.590039001 -0600 | ||
316 | @@ -0,0 +1,176 @@ | ||
317 | +;; Pipeline description for Freescale PowerPC e5500 core. | ||
318 | +;; Copyright (C) 2011 Free Software Foundation, Inc. | ||
319 | +;; Contributed by Edmar Wienskoski (edmar@freescale.com) | ||
320 | +;; | ||
321 | +;; This file is part of GCC. | ||
322 | +;; | ||
323 | +;; GCC is free software; you can redistribute it and/or modify it | ||
324 | +;; under the terms of the GNU General Public License as published | ||
325 | +;; by the Free Software Foundation; either version 3, or (at your | ||
326 | +;; option) any later version. | ||
327 | +;; | ||
328 | +;; GCC is distributed in the hope that it will be useful, but WITHOUT | ||
329 | +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
330 | +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
331 | +;; License for more details. | ||
332 | +;; | ||
333 | +;; You should have received a copy of the GNU General Public License | ||
334 | +;; along with GCC; see the file COPYING3. If not see | ||
335 | +;; <http://www.gnu.org/licenses/>. | ||
336 | +;; | ||
337 | +;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU | ||
338 | +;; Max issue 3 insns/clock cycle (includes 1 branch) | ||
339 | + | ||
340 | +(define_automaton "e5500_most,e5500_long") | ||
341 | +(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most") | ||
342 | + | ||
343 | +;; SFX. | ||
344 | +(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most") | ||
345 | + | ||
346 | +;; CFX. | ||
347 | +(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most") | ||
348 | + | ||
349 | +;; Non-pipelined division. | ||
350 | +(define_cpu_unit "e5500_cfx_div" "e5500_long") | ||
351 | + | ||
352 | +;; LSU. | ||
353 | +(define_cpu_unit "e5500_lsu" "e5500_most") | ||
354 | + | ||
355 | +;; FPU. | ||
356 | +(define_cpu_unit "e5500_fpu" "e5500_long") | ||
357 | + | ||
358 | +;; BU. | ||
359 | +(define_cpu_unit "e5500_bu" "e5500_most") | ||
360 | + | ||
361 | +;; The following units are used to make the automata deterministic. | ||
362 | +(define_cpu_unit "present_e5500_decode_0" "e5500_most") | ||
363 | +(define_cpu_unit "present_e5500_sfx_0" "e5500_most") | ||
364 | +(presence_set "present_e5500_decode_0" "e5500_decode_0") | ||
365 | +(presence_set "present_e5500_sfx_0" "e5500_sfx_0") | ||
366 | + | ||
367 | +;; Some useful abbreviations. | ||
368 | +(define_reservation "e5500_decode" | ||
369 | + "e5500_decode_0|e5500_decode_1+present_e5500_decode_0") | ||
370 | +(define_reservation "e5500_sfx" | ||
371 | + "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0") | ||
372 | + | ||
373 | +;; SFX. | ||
374 | +(define_insn_reservation "e5500_sfx" 1 | ||
375 | + (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ | ||
376 | + shift,cntlz,exts") | ||
377 | + (eq_attr "cpu" "ppce5500")) | ||
378 | + "e5500_decode,e5500_sfx") | ||
379 | + | ||
380 | +(define_insn_reservation "e5500_sfx2" 2 | ||
381 | + (and (eq_attr "type" "cmp,compare,fast_compare,trap") | ||
382 | + (eq_attr "cpu" "ppce5500")) | ||
383 | + "e5500_decode,e5500_sfx") | ||
384 | + | ||
385 | +(define_insn_reservation "e5500_delayed" 2 | ||
386 | + (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt") | ||
387 | + (eq_attr "cpu" "ppce5500")) | ||
388 | + "e5500_decode,e5500_sfx*2") | ||
389 | + | ||
390 | +(define_insn_reservation "e5500_two" 2 | ||
391 | + (and (eq_attr "type" "two") | ||
392 | + (eq_attr "cpu" "ppce5500")) | ||
393 | + "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx") | ||
394 | + | ||
395 | +(define_insn_reservation "e5500_three" 3 | ||
396 | + (and (eq_attr "type" "three") | ||
397 | + (eq_attr "cpu" "ppce5500")) | ||
398 | + "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx") | ||
399 | + | ||
400 | +;; SFX - Mfcr. | ||
401 | +(define_insn_reservation "e5500_mfcr" 4 | ||
402 | + (and (eq_attr "type" "mfcr") | ||
403 | + (eq_attr "cpu" "ppce5500")) | ||
404 | + "e5500_decode,e5500_sfx_0*4") | ||
405 | + | ||
406 | +;; SFX - Mtcrf. | ||
407 | +(define_insn_reservation "e5500_mtcrf" 1 | ||
408 | + (and (eq_attr "type" "mtcr") | ||
409 | + (eq_attr "cpu" "ppce5500")) | ||
410 | + "e5500_decode,e5500_sfx_0") | ||
411 | + | ||
412 | +;; SFX - Mtjmpr. | ||
413 | +(define_insn_reservation "e5500_mtjmpr" 1 | ||
414 | + (and (eq_attr "type" "mtjmpr,mfjmpr") | ||
415 | + (eq_attr "cpu" "ppce5500")) | ||
416 | + "e5500_decode,e5500_sfx") | ||
417 | + | ||
418 | +;; CFX - Multiply. | ||
419 | +(define_insn_reservation "e5500_multiply" 4 | ||
420 | + (and (eq_attr "type" "imul") | ||
421 | + (eq_attr "cpu" "ppce5500")) | ||
422 | + "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1") | ||
423 | + | ||
424 | +(define_insn_reservation "e5500_multiply_i" 5 | ||
425 | + (and (eq_attr "type" "imul2,imul3,imul_compare") | ||
426 | + (eq_attr "cpu" "ppce5500")) | ||
427 | + "e5500_decode,e5500_cfx_stage0,\ | ||
428 | + e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1") | ||
429 | + | ||
430 | +;; CFX - Divide. | ||
431 | +(define_insn_reservation "e5500_divide" 16 | ||
432 | + (and (eq_attr "type" "idiv") | ||
433 | + (eq_attr "cpu" "ppce5500")) | ||
434 | + "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | ||
435 | + e5500_cfx_div*15") | ||
436 | + | ||
437 | +(define_insn_reservation "e5500_divide_d" 26 | ||
438 | + (and (eq_attr "type" "ldiv") | ||
439 | + (eq_attr "cpu" "ppce5500")) | ||
440 | + "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | ||
441 | + e5500_cfx_div*25") | ||
442 | + | ||
443 | +;; LSU - Loads. | ||
444 | +(define_insn_reservation "e5500_load" 3 | ||
445 | + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ | ||
446 | + load_l,sync") | ||
447 | + (eq_attr "cpu" "ppce5500")) | ||
448 | + "e5500_decode,e5500_lsu") | ||
449 | + | ||
450 | +(define_insn_reservation "e5500_fpload" 4 | ||
451 | + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | ||
452 | + (eq_attr "cpu" "ppce5500")) | ||
453 | + "e5500_decode,e5500_lsu") | ||
454 | + | ||
455 | +;; LSU - Stores. | ||
456 | +(define_insn_reservation "e5500_store" 3 | ||
457 | + (and (eq_attr "type" "store,store_ux,store_u,store_c") | ||
458 | + (eq_attr "cpu" "ppce5500")) | ||
459 | + "e5500_decode,e5500_lsu") | ||
460 | + | ||
461 | +(define_insn_reservation "e5500_fpstore" 3 | ||
462 | + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") | ||
463 | + (eq_attr "cpu" "ppce5500")) | ||
464 | + "e5500_decode,e5500_lsu") | ||
465 | + | ||
466 | +;; FP. | ||
467 | +(define_insn_reservation "e5500_float" 7 | ||
468 | + (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul") | ||
469 | + (eq_attr "cpu" "ppce5500")) | ||
470 | + "e5500_decode,e5500_fpu") | ||
471 | + | ||
472 | +(define_insn_reservation "e5500_sdiv" 20 | ||
473 | + (and (eq_attr "type" "sdiv") | ||
474 | + (eq_attr "cpu" "ppce5500")) | ||
475 | + "e5500_decode,e5500_fpu*20") | ||
476 | + | ||
477 | +(define_insn_reservation "e5500_ddiv" 35 | ||
478 | + (and (eq_attr "type" "ddiv") | ||
479 | + (eq_attr "cpu" "ppce5500")) | ||
480 | + "e5500_decode,e5500_fpu*35") | ||
481 | + | ||
482 | +;; BU. | ||
483 | +(define_insn_reservation "e5500_branch" 1 | ||
484 | + (and (eq_attr "type" "jmpreg,branch,isync") | ||
485 | + (eq_attr "cpu" "ppce5500")) | ||
486 | + "e5500_decode,e5500_bu") | ||
487 | + | ||
488 | +;; BU - CR logical. | ||
489 | +(define_insn_reservation "e5500_cr_logical" 1 | ||
490 | + (and (eq_attr "type" "cr_logical,delayed_cr") | ||
491 | + (eq_attr "cpu" "ppce5500")) | ||
492 | + "e5500_decode,e5500_bu") | ||
493 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/e6500.md gcc-4.6.2/gcc/config/rs6000/e6500.md | ||
494 | --- gcc-4.6.2-orig/gcc/config/rs6000/e6500.md 1969-12-31 18:00:00.000000000 -0600 | ||
495 | +++ gcc-4.6.2/gcc/config/rs6000/e6500.md 2012-03-06 12:16:25.573039002 -0600 | ||
496 | @@ -0,0 +1,213 @@ | ||
497 | +;; Pipeline description for Freescale PowerPC e6500 core. | ||
498 | +;; Copyright (C) 2011 Free Software Foundation, Inc. | ||
499 | +;; Contributed by Edmar Wienskoski (edmar@freescale.com) | ||
500 | +;; | ||
501 | +;; This file is part of GCC. | ||
502 | +;; | ||
503 | +;; GCC is free software; you can redistribute it and/or modify it | ||
504 | +;; under the terms of the GNU General Public License as published | ||
505 | +;; by the Free Software Foundation; either version 3, or (at your | ||
506 | +;; option) any later version. | ||
507 | +;; | ||
508 | +;; GCC is distributed in the hope that it will be useful, but WITHOUT | ||
509 | +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
510 | +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
511 | +;; License for more details. | ||
512 | +;; | ||
513 | +;; You should have received a copy of the GNU General Public License | ||
514 | +;; along with GCC; see the file COPYING3. If not see | ||
515 | +;; <http://www.gnu.org/licenses/>. | ||
516 | +;; | ||
517 | +;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM | ||
518 | +;; Max issue 3 insns/clock cycle (includes 1 branch) | ||
519 | + | ||
520 | +(define_automaton "e6500_most,e6500_long,e6500_vec") | ||
521 | +(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most") | ||
522 | + | ||
523 | +;; SFX. | ||
524 | +(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most") | ||
525 | + | ||
526 | +;; CFX. | ||
527 | +(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most") | ||
528 | + | ||
529 | +;; Non-pipelined division. | ||
530 | +(define_cpu_unit "e6500_cfx_div" "e6500_long") | ||
531 | + | ||
532 | +;; LSU. | ||
533 | +(define_cpu_unit "e6500_lsu" "e6500_most") | ||
534 | + | ||
535 | +;; FPU. | ||
536 | +(define_cpu_unit "e6500_fpu" "e6500_long") | ||
537 | + | ||
538 | +;; BU. | ||
539 | +(define_cpu_unit "e6500_bu" "e6500_most") | ||
540 | + | ||
541 | +;; Altivec unit | ||
542 | +(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec") | ||
543 | + | ||
544 | +;; The following units are used to make the automata deterministic. | ||
545 | +(define_cpu_unit "present_e6500_decode_0" "e6500_most") | ||
546 | +(define_cpu_unit "present_e6500_sfx_0" "e6500_most") | ||
547 | +(presence_set "present_e6500_decode_0" "e6500_decode_0") | ||
548 | +(presence_set "present_e6500_sfx_0" "e6500_sfx_0") | ||
549 | + | ||
550 | +;; Some useful abbreviations. | ||
551 | +(define_reservation "e6500_decode" | ||
552 | + "e6500_decode_0|e6500_decode_1+present_e6500_decode_0") | ||
553 | +(define_reservation "e6500_sfx" | ||
554 | + "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0") | ||
555 | + | ||
556 | +;; SFX. | ||
557 | +(define_insn_reservation "e6500_sfx" 1 | ||
558 | + (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ | ||
559 | + shift,cntlz,exts") | ||
560 | + (eq_attr "cpu" "ppce6500")) | ||
561 | + "e6500_decode,e6500_sfx") | ||
562 | + | ||
563 | +(define_insn_reservation "e6500_sfx2" 2 | ||
564 | + (and (eq_attr "type" "cmp,compare,fast_compare,trap") | ||
565 | + (eq_attr "cpu" "ppce6500")) | ||
566 | + "e6500_decode,e6500_sfx") | ||
567 | + | ||
568 | +(define_insn_reservation "e6500_delayed" 2 | ||
569 | + (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt") | ||
570 | + (eq_attr "cpu" "ppce6500")) | ||
571 | + "e6500_decode,e6500_sfx*2") | ||
572 | + | ||
573 | +(define_insn_reservation "e6500_two" 2 | ||
574 | + (and (eq_attr "type" "two") | ||
575 | + (eq_attr "cpu" "ppce6500")) | ||
576 | + "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx") | ||
577 | + | ||
578 | +(define_insn_reservation "e6500_three" 3 | ||
579 | + (and (eq_attr "type" "three") | ||
580 | + (eq_attr "cpu" "ppce6500")) | ||
581 | + "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx") | ||
582 | + | ||
583 | +;; SFX - Mfcr. | ||
584 | +(define_insn_reservation "e6500_mfcr" 4 | ||
585 | + (and (eq_attr "type" "mfcr") | ||
586 | + (eq_attr "cpu" "ppce6500")) | ||
587 | + "e6500_decode,e6500_sfx_0*4") | ||
588 | + | ||
589 | +;; SFX - Mtcrf. | ||
590 | +(define_insn_reservation "e6500_mtcrf" 1 | ||
591 | + (and (eq_attr "type" "mtcr") | ||
592 | + (eq_attr "cpu" "ppce6500")) | ||
593 | + "e6500_decode,e6500_sfx_0") | ||
594 | + | ||
595 | +;; SFX - Mtjmpr. | ||
596 | +(define_insn_reservation "e6500_mtjmpr" 1 | ||
597 | + (and (eq_attr "type" "mtjmpr,mfjmpr") | ||
598 | + (eq_attr "cpu" "ppce6500")) | ||
599 | + "e6500_decode,e6500_sfx") | ||
600 | + | ||
601 | +;; CFX - Multiply. | ||
602 | +(define_insn_reservation "e6500_multiply" 4 | ||
603 | + (and (eq_attr "type" "imul") | ||
604 | + (eq_attr "cpu" "ppce6500")) | ||
605 | + "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1") | ||
606 | + | ||
607 | +(define_insn_reservation "e6500_multiply_i" 5 | ||
608 | + (and (eq_attr "type" "imul2,imul3,imul_compare") | ||
609 | + (eq_attr "cpu" "ppce6500")) | ||
610 | + "e6500_decode,e6500_cfx_stage0,\ | ||
611 | + e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1") | ||
612 | + | ||
613 | +;; CFX - Divide. | ||
614 | +(define_insn_reservation "e6500_divide" 16 | ||
615 | + (and (eq_attr "type" "idiv") | ||
616 | + (eq_attr "cpu" "ppce6500")) | ||
617 | + "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ | ||
618 | + e6500_cfx_div*15") | ||
619 | + | ||
620 | +(define_insn_reservation "e6500_divide_d" 26 | ||
621 | + (and (eq_attr "type" "ldiv") | ||
622 | + (eq_attr "cpu" "ppce6500")) | ||
623 | + "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ | ||
624 | + e6500_cfx_div*25") | ||
625 | + | ||
626 | +;; LSU - Loads. | ||
627 | +(define_insn_reservation "e6500_load" 3 | ||
628 | + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ | ||
629 | + load_l,sync") | ||
630 | + (eq_attr "cpu" "ppce6500")) | ||
631 | + "e6500_decode,e6500_lsu") | ||
632 | + | ||
633 | +(define_insn_reservation "e6500_fpload" 4 | ||
634 | + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | ||
635 | + (eq_attr "cpu" "ppce6500")) | ||
636 | + "e6500_decode,e6500_lsu") | ||
637 | + | ||
638 | +(define_insn_reservation "e6500_vecload" 4 | ||
639 | + (and (eq_attr "type" "vecload") | ||
640 | + (eq_attr "cpu" "ppce6500")) | ||
641 | + "e6500_decode,e6500_lsu") | ||
642 | + | ||
643 | +;; LSU - Stores. | ||
644 | +(define_insn_reservation "e6500_store" 3 | ||
645 | + (and (eq_attr "type" "store,store_ux,store_u,store_c") | ||
646 | + (eq_attr "cpu" "ppce6500")) | ||
647 | + "e6500_decode,e6500_lsu") | ||
648 | + | ||
649 | +(define_insn_reservation "e6500_fpstore" 3 | ||
650 | + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") | ||
651 | + (eq_attr "cpu" "ppce6500")) | ||
652 | + "e6500_decode,e6500_lsu") | ||
653 | + | ||
654 | +(define_insn_reservation "e6500_vecstore" 4 | ||
655 | + (and (eq_attr "type" "vecstore") | ||
656 | + (eq_attr "cpu" "ppce6500")) | ||
657 | + "e6500_decode,e6500_lsu") | ||
658 | + | ||
659 | +;; FP. | ||
660 | +(define_insn_reservation "e6500_float" 7 | ||
661 | + (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul") | ||
662 | + (eq_attr "cpu" "ppce6500")) | ||
663 | + "e6500_decode,e6500_fpu") | ||
664 | + | ||
665 | +(define_insn_reservation "e6500_sdiv" 20 | ||
666 | + (and (eq_attr "type" "sdiv") | ||
667 | + (eq_attr "cpu" "ppce6500")) | ||
668 | + "e6500_decode,e6500_fpu*20") | ||
669 | + | ||
670 | +(define_insn_reservation "e6500_ddiv" 35 | ||
671 | + (and (eq_attr "type" "ddiv") | ||
672 | + (eq_attr "cpu" "ppce6500")) | ||
673 | + "e6500_decode,e6500_fpu*35") | ||
674 | + | ||
675 | +;; BU. | ||
676 | +(define_insn_reservation "e6500_branch" 1 | ||
677 | + (and (eq_attr "type" "jmpreg,branch,isync") | ||
678 | + (eq_attr "cpu" "ppce6500")) | ||
679 | + "e6500_decode,e6500_bu") | ||
680 | + | ||
681 | +;; BU - CR logical. | ||
682 | +(define_insn_reservation "e6500_cr_logical" 1 | ||
683 | + (and (eq_attr "type" "cr_logical,delayed_cr") | ||
684 | + (eq_attr "cpu" "ppce6500")) | ||
685 | + "e6500_decode,e6500_bu") | ||
686 | + | ||
687 | +;; VSFX. | ||
688 | +(define_insn_reservation "e6500_vecsimple" 1 | ||
689 | + (and (eq_attr "type" "vecsimple,veccmp") | ||
690 | + (eq_attr "cpu" "ppce6500")) | ||
691 | + "e6500_decode,e6500_vec") | ||
692 | + | ||
693 | +;; VCFX. | ||
694 | +(define_insn_reservation "e6500_veccomplex" 4 | ||
695 | + (and (eq_attr "type" "veccomplex") | ||
696 | + (eq_attr "cpu" "ppce6500")) | ||
697 | + "e6500_decode,e6500_vec") | ||
698 | + | ||
699 | +;; VFPU. | ||
700 | +(define_insn_reservation "e6500_vecfloat" 6 | ||
701 | + (and (eq_attr "type" "vecfloat") | ||
702 | + (eq_attr "cpu" "ppce6500")) | ||
703 | + "e6500_decode,e6500_vec") | ||
704 | + | ||
705 | +;; VPERM. | ||
706 | +(define_insn_reservation "e6500_vecperm" 2 | ||
707 | + (and (eq_attr "type" "vecperm") | ||
708 | + (eq_attr "cpu" "ppce6500")) | ||
709 | + "e6500_decode,e6500_vecperm") | ||
710 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000-builtin.def gcc-4.6.2/gcc/config/rs6000/rs6000-builtin.def | ||
711 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000-builtin.def 2011-02-21 15:38:21.000000000 -0600 | ||
712 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000-builtin.def 2012-03-06 12:37:40.248039025 -0600 | ||
713 | @@ -224,6 +224,9 @@ | ||
714 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEBX, RS6000_BTC_MEM) | ||
715 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEHX, RS6000_BTC_MEM) | ||
716 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEWX, RS6000_BTC_MEM) | ||
717 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXBX, RS6000_BTC_MEM) | ||
718 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXHX, RS6000_BTC_MEM) | ||
719 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXWX, RS6000_BTC_MEM) | ||
720 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVXL, RS6000_BTC_MEM) | ||
721 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVX, RS6000_BTC_MEM) | ||
722 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVX, RS6000_BTC_MEM) | ||
723 | @@ -231,14 +234,30 @@ | ||
724 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVLXL, RS6000_BTC_MEM) | ||
725 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRX, RS6000_BTC_MEM) | ||
726 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRXL, RS6000_BTC_MEM) | ||
727 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTLX, RS6000_BTC_MEM) | ||
728 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTLXL, RS6000_BTC_MEM) | ||
729 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTRX, RS6000_BTC_MEM) | ||
730 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTRXL, RS6000_BTC_MEM) | ||
731 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSWX, RS6000_BTC_MEM) | ||
732 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSWXL, RS6000_BTC_MEM) | ||
733 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSM, RS6000_BTC_MEM) | ||
734 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEBX, RS6000_BTC_MEM) | ||
735 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEHX, RS6000_BTC_MEM) | ||
736 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEWX, RS6000_BTC_MEM) | ||
737 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXBX, RS6000_BTC_MEM) | ||
738 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXHX, RS6000_BTC_MEM) | ||
739 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXWX, RS6000_BTC_MEM) | ||
740 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVXL, RS6000_BTC_MEM) | ||
741 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLX, RS6000_BTC_MEM) | ||
742 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLXL, RS6000_BTC_MEM) | ||
743 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRX, RS6000_BTC_MEM) | ||
744 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRXL, RS6000_BTC_MEM) | ||
745 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFLX, RS6000_BTC_MEM) | ||
746 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFLXL, RS6000_BTC_MEM) | ||
747 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFRX, RS6000_BTC_MEM) | ||
748 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFRXL, RS6000_BTC_MEM) | ||
749 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVSWX, RS6000_BTC_MEM) | ||
750 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVSWXL, RS6000_BTC_MEM) | ||
751 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPBFP_P, RS6000_BTC_FP_PURE) | ||
752 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQFP_P, RS6000_BTC_FP_PURE) | ||
753 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUB_P, RS6000_BTC_CONST) | ||
754 | @@ -275,6 +294,9 @@ | ||
755 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SF, RS6000_BTC_CONST) | ||
756 | RS6000_BUILTIN(ALTIVEC_BUILTIN_COPYSIGN_V4SF, RS6000_BTC_CONST) | ||
757 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VRECIPFP, RS6000_BTC_FP_PURE) | ||
758 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUB, RS6000_BTC_CONST) | ||
759 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUH, RS6000_BTC_CONST) | ||
760 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUW, RS6000_BTC_CONST) | ||
761 | |||
762 | /* Altivec overloaded builtins. */ | ||
763 | /* For now, don't set the classification for overloaded functions. | ||
764 | @@ -286,6 +308,7 @@ | ||
765 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGT_P, RS6000_BTC_MISC) | ||
766 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGE_P, RS6000_BTC_MISC) | ||
767 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABS, RS6000_BTC_MISC) | ||
768 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSD, RS6000_BTC_MISC) | ||
769 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSS, RS6000_BTC_MISC) | ||
770 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADD, RS6000_BTC_MISC) | ||
771 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADDC, RS6000_BTC_MISC) | ||
772 | @@ -321,10 +344,20 @@ | ||
773 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEBX, RS6000_BTC_MISC) | ||
774 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEHX, RS6000_BTC_MISC) | ||
775 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEWX, RS6000_BTC_MISC) | ||
776 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXBX, RS6000_BTC_MISC) | ||
777 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXHX, RS6000_BTC_MISC) | ||
778 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXWX, RS6000_BTC_MISC) | ||
779 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLX, RS6000_BTC_MISC) | ||
780 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLXL, RS6000_BTC_MISC) | ||
781 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRX, RS6000_BTC_MISC) | ||
782 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRXL, RS6000_BTC_MISC) | ||
783 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTLX, RS6000_BTC_MISC) | ||
784 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTLXL, RS6000_BTC_MISC) | ||
785 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTRX, RS6000_BTC_MISC) | ||
786 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTRXL, RS6000_BTC_MISC) | ||
787 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSWX, RS6000_BTC_MISC) | ||
788 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSWXL, RS6000_BTC_MISC) | ||
789 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSM, RS6000_BTC_MISC) | ||
790 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSL, RS6000_BTC_MISC) | ||
791 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSR, RS6000_BTC_MISC) | ||
792 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MADD, RS6000_BTC_MISC) | ||
793 | @@ -389,10 +422,19 @@ | ||
794 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEBX, RS6000_BTC_MISC) | ||
795 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEHX, RS6000_BTC_MISC) | ||
796 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEWX, RS6000_BTC_MISC) | ||
797 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXBX, RS6000_BTC_MISC) | ||
798 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXHX, RS6000_BTC_MISC) | ||
799 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXWX, RS6000_BTC_MISC) | ||
800 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLX, RS6000_BTC_MISC) | ||
801 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLXL, RS6000_BTC_MISC) | ||
802 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRX, RS6000_BTC_MISC) | ||
803 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRXL, RS6000_BTC_MISC) | ||
804 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFLX, RS6000_BTC_MISC) | ||
805 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFLXL, RS6000_BTC_MISC) | ||
806 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFRX, RS6000_BTC_MISC) | ||
807 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFRXL, RS6000_BTC_MISC) | ||
808 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVSWX, RS6000_BTC_MISC) | ||
809 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVSWXL, RS6000_BTC_MISC) | ||
810 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUB, RS6000_BTC_MISC) | ||
811 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBC, RS6000_BTC_MISC) | ||
812 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBS, RS6000_BTC_MISC) | ||
813 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.c gcc-4.6.2/gcc/config/rs6000/rs6000.c | ||
814 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.c 2011-09-18 17:01:56.000000000 -0500 | ||
815 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.c 2012-03-06 12:44:04.689039002 -0600 | ||
816 | @@ -779,6 +779,44 @@ | ||
817 | 1, /* prefetch streams /*/ | ||
818 | }; | ||
819 | |||
820 | +/* Instruction costs on PPCE5500 processors. */ | ||
821 | +static const | ||
822 | +struct processor_costs ppce5500_cost = { | ||
823 | + COSTS_N_INSNS (5), /* mulsi */ | ||
824 | + COSTS_N_INSNS (5), /* mulsi_const */ | ||
825 | + COSTS_N_INSNS (5), /* mulsi_const9 */ | ||
826 | + COSTS_N_INSNS (5), /* muldi */ | ||
827 | + COSTS_N_INSNS (14), /* divsi */ | ||
828 | + COSTS_N_INSNS (14), /* divdi */ | ||
829 | + COSTS_N_INSNS (7), /* fp */ | ||
830 | + COSTS_N_INSNS (10), /* dmul */ | ||
831 | + COSTS_N_INSNS (36), /* sdiv */ | ||
832 | + COSTS_N_INSNS (66), /* ddiv */ | ||
833 | + 64, /* cache line size */ | ||
834 | + 32, /* l1 cache */ | ||
835 | + 128, /* l2 cache */ | ||
836 | + 1, /* prefetch streams /*/ | ||
837 | +}; | ||
838 | + | ||
839 | +/* Instruction costs on PPCE6500 processors. */ | ||
840 | +static const | ||
841 | +struct processor_costs ppce6500_cost = { | ||
842 | + COSTS_N_INSNS (5), /* mulsi */ | ||
843 | + COSTS_N_INSNS (5), /* mulsi_const */ | ||
844 | + COSTS_N_INSNS (5), /* mulsi_const9 */ | ||
845 | + COSTS_N_INSNS (5), /* muldi */ | ||
846 | + COSTS_N_INSNS (14), /* divsi */ | ||
847 | + COSTS_N_INSNS (14), /* divdi */ | ||
848 | + COSTS_N_INSNS (7), /* fp */ | ||
849 | + COSTS_N_INSNS (10), /* dmul */ | ||
850 | + COSTS_N_INSNS (36), /* sdiv */ | ||
851 | + COSTS_N_INSNS (66), /* ddiv */ | ||
852 | + 64, /* cache line size */ | ||
853 | + 32, /* l1 cache */ | ||
854 | + 128, /* l2 cache */ | ||
855 | + 1, /* prefetch streams /*/ | ||
856 | +}; | ||
857 | + | ||
858 | /* Instruction costs on AppliedMicro Titan processors. */ | ||
859 | static const | ||
860 | struct processor_costs titan_cost = { | ||
861 | @@ -1690,7 +1728,7 @@ | ||
862 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW | ||
863 | | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP | ||
864 | | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE | ||
865 | - | MASK_RECIP_PRECISION) | ||
866 | + | MASK_RECIP_PRECISION | MASK_ALTIVEC2) | ||
867 | }; | ||
868 | |||
869 | /* Masks for instructions set at various powerpc ISAs. */ | ||
870 | @@ -1785,6 +1823,12 @@ | ||
871 | | MASK_ISEL}, | ||
872 | {"e500mc64", PROCESSOR_PPCE500MC64, POWERPC_BASE_MASK | MASK_POWERPC64 | ||
873 | | MASK_PPC_GFXOPT | MASK_ISEL}, | ||
874 | + {"e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64 | ||
875 | + | MASK_PPC_GFXOPT | MASK_ISEL | MASK_CMPB | MASK_POPCNTB | ||
876 | + | MASK_POPCNTD}, | ||
877 | + {"e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 | ||
878 | + | MASK_MFCRF | MASK_ISEL | MASK_CMPB | MASK_POPCNTB | MASK_POPCNTD | ||
879 | + | MASK_ALTIVEC2}, | ||
880 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | ||
881 | {"970", PROCESSOR_POWER4, | ||
882 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, | ||
883 | @@ -2742,13 +2786,19 @@ | ||
884 | : PROCESSOR_DEFAULT)); | ||
885 | |||
886 | if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 | ||
887 | - || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
888 | + || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
889 | + || rs6000_cpu == PROCESSOR_PPCE5500) | ||
890 | { | ||
891 | if (TARGET_ALTIVEC) | ||
892 | error ("AltiVec not supported in this target"); | ||
893 | if (TARGET_SPE) | ||
894 | error ("SPE not supported in this target"); | ||
895 | } | ||
896 | + if (rs6000_cpu == PROCESSOR_PPCE6500) | ||
897 | + { | ||
898 | + if (TARGET_SPE) | ||
899 | + error ("SPE not supported in this target"); | ||
900 | + } | ||
901 | |||
902 | /* Disable Cell microcode if we are optimizing for the Cell | ||
903 | and not optimizing for size. */ | ||
904 | @@ -2843,9 +2893,16 @@ | ||
905 | user's opinion, though. */ | ||
906 | if (rs6000_block_move_inline_limit == 0 | ||
907 | && (rs6000_cpu == PROCESSOR_PPCE500MC | ||
908 | - || rs6000_cpu == PROCESSOR_PPCE500MC64)) | ||
909 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
910 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
911 | + || rs6000_cpu == PROCESSOR_PPCE6500)) | ||
912 | rs6000_block_move_inline_limit = 128; | ||
913 | |||
914 | + /* Those machines does not have fsqrt instruction */ | ||
915 | + if (rs6000_cpu == PROCESSOR_PPCE5500 | ||
916 | + || rs6000_cpu == PROCESSOR_PPCE6500) | ||
917 | + target_flags &= ~MASK_PPC_GPOPT; | ||
918 | + | ||
919 | /* store_one_arg depends on expand_block_move to handle at least the | ||
920 | size of reg_parm_stack_space. */ | ||
921 | if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32)) | ||
922 | @@ -2977,7 +3034,9 @@ | ||
923 | #endif | ||
924 | |||
925 | if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC | ||
926 | - || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
927 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
928 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
929 | + || rs6000_cpu == PROCESSOR_PPCE6500) | ||
930 | { | ||
931 | /* The e500 and e500mc do not have string instructions, and we set | ||
932 | MASK_STRING above when optimizing for size. */ | ||
933 | @@ -3024,7 +3083,9 @@ | ||
934 | || rs6000_cpu == PROCESSOR_POWER6 | ||
935 | || rs6000_cpu == PROCESSOR_POWER7 | ||
936 | || rs6000_cpu == PROCESSOR_PPCE500MC | ||
937 | - || rs6000_cpu == PROCESSOR_PPCE500MC64); | ||
938 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
939 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
940 | + || rs6000_cpu == PROCESSOR_PPCE6500); | ||
941 | |||
942 | /* Allow debug switches to override the above settings. These are set to -1 | ||
943 | in rs6000.opt to indicate the user hasn't directly set the switch. */ | ||
944 | @@ -3246,6 +3307,14 @@ | ||
945 | rs6000_cost = &ppce500mc64_cost; | ||
946 | break; | ||
947 | |||
948 | + case PROCESSOR_PPCE5500: | ||
949 | + rs6000_cost = &ppce5500_cost; | ||
950 | + break; | ||
951 | + | ||
952 | + case PROCESSOR_PPCE6500: | ||
953 | + rs6000_cost = &ppce6500_cost; | ||
954 | + break; | ||
955 | + | ||
956 | case PROCESSOR_TITAN: | ||
957 | rs6000_cost = &titan_cost; | ||
958 | break; | ||
959 | @@ -10212,6 +10281,9 @@ | ||
960 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | ||
961 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | ||
962 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | ||
963 | + { MASK_ALTIVEC2, CODE_FOR_altivec_vabsdub, "__builtin_altivec_vabsdub", ALTIVEC_BUILTIN_ABSDUB }, | ||
964 | + { MASK_ALTIVEC2, CODE_FOR_altivec_vabsduh, "__builtin_altivec_vabsduh", ALTIVEC_BUILTIN_ABSDUH }, | ||
965 | + { MASK_ALTIVEC2, CODE_FOR_altivec_vabsduw, "__builtin_altivec_vabsduw", ALTIVEC_BUILTIN_ABSDUW }, | ||
966 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, | ||
967 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | ||
968 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | ||
969 | @@ -10372,6 +10444,7 @@ | ||
970 | { MASK_VSX, CODE_FOR_vec_interleave_highv2df, "__builtin_vsx_mergeh_2df", VSX_BUILTIN_VEC_MERGEH_V2DF }, | ||
971 | { MASK_VSX, CODE_FOR_vec_interleave_highv2di, "__builtin_vsx_mergeh_2di", VSX_BUILTIN_VEC_MERGEH_V2DI }, | ||
972 | |||
973 | + { MASK_ALTIVEC2, CODE_FOR_nothing, "__builtin_vec_absd", ALTIVEC_BUILTIN_VEC_ABSD }, | ||
974 | { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD }, | ||
975 | { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP }, | ||
976 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM }, | ||
977 | @@ -11803,6 +11876,12 @@ | ||
978 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp); | ||
979 | case ALTIVEC_BUILTIN_STVEWX: | ||
980 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp); | ||
981 | + case ALTIVEC_BUILTIN_STVEXBX: | ||
982 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvexbx, exp); | ||
983 | + case ALTIVEC_BUILTIN_STVEXHX: | ||
984 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvexhx, exp); | ||
985 | + case ALTIVEC_BUILTIN_STVEXWX: | ||
986 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvexwx, exp); | ||
987 | case ALTIVEC_BUILTIN_STVXL: | ||
988 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp); | ||
989 | |||
990 | @@ -11814,6 +11893,18 @@ | ||
991 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp); | ||
992 | case ALTIVEC_BUILTIN_STVRXL: | ||
993 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp); | ||
994 | + case ALTIVEC_BUILTIN_STVFLX: | ||
995 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvflx, exp); | ||
996 | + case ALTIVEC_BUILTIN_STVFLXL: | ||
997 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvflxl, exp); | ||
998 | + case ALTIVEC_BUILTIN_STVFRX: | ||
999 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvfrx, exp); | ||
1000 | + case ALTIVEC_BUILTIN_STVFRXL: | ||
1001 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvfrxl, exp); | ||
1002 | + case ALTIVEC_BUILTIN_STVSWX: | ||
1003 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvswx, exp); | ||
1004 | + case ALTIVEC_BUILTIN_STVSWXL: | ||
1005 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvswxl, exp); | ||
1006 | |||
1007 | case VSX_BUILTIN_STXVD2X_V2DF: | ||
1008 | return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp); | ||
1009 | @@ -11948,6 +12039,15 @@ | ||
1010 | case ALTIVEC_BUILTIN_LVEWX: | ||
1011 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, | ||
1012 | exp, target, false); | ||
1013 | + case ALTIVEC_BUILTIN_LVEXBX: | ||
1014 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvexbx, | ||
1015 | + exp, target, false); | ||
1016 | + case ALTIVEC_BUILTIN_LVEXHX: | ||
1017 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvexhx, | ||
1018 | + exp, target, false); | ||
1019 | + case ALTIVEC_BUILTIN_LVEXWX: | ||
1020 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvexwx, | ||
1021 | + exp, target, false); | ||
1022 | case ALTIVEC_BUILTIN_LVXL: | ||
1023 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, | ||
1024 | exp, target, false); | ||
1025 | @@ -11966,6 +12066,27 @@ | ||
1026 | case ALTIVEC_BUILTIN_LVRXL: | ||
1027 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl, | ||
1028 | exp, target, true); | ||
1029 | + case ALTIVEC_BUILTIN_LVTLX: | ||
1030 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtlx, | ||
1031 | + exp, target, true); | ||
1032 | + case ALTIVEC_BUILTIN_LVTLXL: | ||
1033 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtlxl, | ||
1034 | + exp, target, true); | ||
1035 | + case ALTIVEC_BUILTIN_LVTRX: | ||
1036 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtrx, | ||
1037 | + exp, target, true); | ||
1038 | + case ALTIVEC_BUILTIN_LVTRXL: | ||
1039 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtrxl, | ||
1040 | + exp, target, true); | ||
1041 | + case ALTIVEC_BUILTIN_LVSWX: | ||
1042 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvswx, | ||
1043 | + exp, target, true); | ||
1044 | + case ALTIVEC_BUILTIN_LVSWXL: | ||
1045 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvswxl, | ||
1046 | + exp, target, true); | ||
1047 | + case ALTIVEC_BUILTIN_LVSM: | ||
1048 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsm, | ||
1049 | + exp, target, true); | ||
1050 | case VSX_BUILTIN_LXVD2X_V2DF: | ||
1051 | return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df, | ||
1052 | exp, target, false); | ||
1053 | @@ -13278,6 +13399,9 @@ | ||
1054 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | ||
1055 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | ||
1056 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | ||
1057 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvexbx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEXBX); | ||
1058 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvexhx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEXHX); | ||
1059 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvexwx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEXWX); | ||
1060 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | ||
1061 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | ||
1062 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | ||
1063 | @@ -13285,6 +13409,9 @@ | ||
1064 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | ||
1065 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | ||
1066 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | ||
1067 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvexbx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEXBX); | ||
1068 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvexhx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEXHX); | ||
1069 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvexwx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEXWX); | ||
1070 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); | ||
1071 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); | ||
1072 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); | ||
1073 | @@ -13293,12 +13420,18 @@ | ||
1074 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); | ||
1075 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); | ||
1076 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); | ||
1077 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvexbx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEXBX); | ||
1078 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvexhx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEXHX); | ||
1079 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvexwx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEXWX); | ||
1080 | def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); | ||
1081 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); | ||
1082 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); | ||
1083 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); | ||
1084 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); | ||
1085 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); | ||
1086 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvexwx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEXWX); | ||
1087 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvexbx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEXBX); | ||
1088 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvexhx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEXHX); | ||
1089 | |||
1090 | def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid, | ||
1091 | VSX_BUILTIN_LXVD2X_V2DF); | ||
1092 | @@ -13351,6 +13484,33 @@ | ||
1093 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX); | ||
1094 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL); | ||
1095 | } | ||
1096 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTLX); | ||
1097 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTLXL); | ||
1098 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTRX); | ||
1099 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTRXL); | ||
1100 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTLX); | ||
1101 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTLXL); | ||
1102 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTRX); | ||
1103 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTRXL); | ||
1104 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvflx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFLX); | ||
1105 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvflxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFLXL); | ||
1106 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvfrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFRX); | ||
1107 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvfrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFRXL); | ||
1108 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvflx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFLX); | ||
1109 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvflxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFLXL); | ||
1110 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvfrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFRX); | ||
1111 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvfrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFRXL); | ||
1112 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvswx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSWX); | ||
1113 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvswxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSWXL); | ||
1114 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvswx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSWX); | ||
1115 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvswxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSWXL); | ||
1116 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvsm", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSM); | ||
1117 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvsm", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSM); | ||
1118 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvswx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVSWX); | ||
1119 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvswxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVSWXL); | ||
1120 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvswx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVSWX); | ||
1121 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvswxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVSWXL); | ||
1122 | + | ||
1123 | def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); | ||
1124 | def_builtin (MASK_ALTIVEC, "__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS); | ||
1125 | def_builtin (MASK_ALTIVEC, "__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE); | ||
1126 | @@ -13668,6 +13828,9 @@ | ||
1127 | case ALTIVEC_BUILTIN_VMULEUH_UNS: | ||
1128 | case ALTIVEC_BUILTIN_VMULOUB_UNS: | ||
1129 | case ALTIVEC_BUILTIN_VMULOUH_UNS: | ||
1130 | + case ALTIVEC_BUILTIN_ABSDUB: | ||
1131 | + case ALTIVEC_BUILTIN_ABSDUH: | ||
1132 | + case ALTIVEC_BUILTIN_ABSDUW: | ||
1133 | h.uns_p[0] = 1; | ||
1134 | h.uns_p[1] = 1; | ||
1135 | h.uns_p[2] = 1; | ||
1136 | @@ -23250,6 +23413,7 @@ | ||
1137 | || rs6000_cpu_attr == CPU_PPC750 | ||
1138 | || rs6000_cpu_attr == CPU_PPC7400 | ||
1139 | || rs6000_cpu_attr == CPU_PPC7450 | ||
1140 | + || rs6000_cpu_attr == CPU_PPCE5500 | ||
1141 | || rs6000_cpu_attr == CPU_POWER4 | ||
1142 | || rs6000_cpu_attr == CPU_POWER5 | ||
1143 | || rs6000_cpu_attr == CPU_POWER7 | ||
1144 | @@ -23794,6 +23958,8 @@ | ||
1145 | case CPU_PPCE300C3: | ||
1146 | case CPU_PPCE500MC: | ||
1147 | case CPU_PPCE500MC64: | ||
1148 | + case CPU_PPCE5500: | ||
1149 | + case CPU_PPCE6500: | ||
1150 | case CPU_TITAN: | ||
1151 | return 2; | ||
1152 | case CPU_RIOS2: | ||
1153 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000-c.c gcc-4.6.2/gcc/config/rs6000/rs6000-c.c | ||
1154 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000-c.c 2011-02-02 23:42:19.000000000 -0600 | ||
1155 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000-c.c 2012-03-06 12:54:55.964038969 -0600 | ||
1156 | @@ -310,6 +310,8 @@ | ||
1157 | /* Enable context-sensitive macros. */ | ||
1158 | cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; | ||
1159 | } | ||
1160 | + if (TARGET_ALTIVEC2) | ||
1161 | + builtin_define ("__ALTIVEC2__"); | ||
1162 | } | ||
1163 | if (rs6000_cpu == PROCESSOR_CELL) | ||
1164 | builtin_define ("__PPU__"); | ||
1165 | @@ -569,6 +571,24 @@ | ||
1166 | RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, | ||
1167 | |||
1168 | /* Binary AltiVec/VSX builtins. */ | ||
1169 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUB, | ||
1170 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, | ||
1171 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUB, | ||
1172 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, | ||
1173 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUB, | ||
1174 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, | ||
1175 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUH, | ||
1176 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, | ||
1177 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUH, | ||
1178 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, | ||
1179 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUH, | ||
1180 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, | ||
1181 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUW, | ||
1182 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, | ||
1183 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUW, | ||
1184 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, | ||
1185 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUW, | ||
1186 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, | ||
1187 | { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, | ||
1188 | RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, | ||
1189 | { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, | ||
1190 | @@ -1084,6 +1104,24 @@ | ||
1191 | RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1192 | { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, | ||
1193 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1194 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1195 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1196 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1197 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1198 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1199 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1200 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1201 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, | ||
1202 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1203 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, | ||
1204 | + { ALTIVEC_BUILTIN_VEC_LVEXHX, ALTIVEC_BUILTIN_LVEXHX, | ||
1205 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1206 | + { ALTIVEC_BUILTIN_VEC_LVEXHX, ALTIVEC_BUILTIN_LVEXHX, | ||
1207 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1208 | + { ALTIVEC_BUILTIN_VEC_LVEXBX, ALTIVEC_BUILTIN_LVEXBX, | ||
1209 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1210 | + { ALTIVEC_BUILTIN_VEC_LVEXBX, ALTIVEC_BUILTIN_LVEXBX, | ||
1211 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1212 | { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, | ||
1213 | RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1214 | { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, | ||
1215 | @@ -1336,6 +1374,258 @@ | ||
1216 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1217 | { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, | ||
1218 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1219 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1220 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1221 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1222 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1223 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1224 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1225 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1226 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1227 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1228 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1229 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1230 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1231 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1232 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1233 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1234 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1235 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1236 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1237 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1238 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1239 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1240 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1241 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1242 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1243 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1244 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1245 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1246 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1247 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1248 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1249 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1250 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1251 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1252 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1253 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1254 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1255 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1256 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1257 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1258 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1259 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1260 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1261 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1262 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1263 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1264 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1265 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1266 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1267 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1268 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1269 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1270 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1271 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1272 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1273 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1274 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1275 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1276 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1277 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1278 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1279 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1280 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1281 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1282 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1283 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1284 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1285 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1286 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1287 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1288 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1289 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1290 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1291 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1292 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1293 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1294 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1295 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1296 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1297 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1298 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1299 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1300 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1301 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1302 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1303 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1304 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1305 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1306 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1307 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1308 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1309 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1310 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1311 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1312 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1313 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1314 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1315 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1316 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1317 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1318 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1319 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1320 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1321 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1322 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1323 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1324 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1325 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1326 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1327 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1328 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1329 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1330 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1331 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1332 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1333 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1334 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1335 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1336 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1337 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1338 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1339 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1340 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1341 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1342 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1343 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1344 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1345 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1346 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1347 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1348 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1349 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1350 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1351 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1352 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1353 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1354 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1355 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1356 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1357 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1358 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1359 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1360 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1361 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1362 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1363 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1364 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1365 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1366 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1367 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1368 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1369 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1370 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1371 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1372 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1373 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1374 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1375 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1376 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1377 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1378 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1379 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1380 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1381 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1382 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1383 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1384 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1385 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1386 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1387 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1388 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1389 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1390 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1391 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1392 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1393 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1394 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1395 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1396 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1397 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1398 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1399 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1400 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1401 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1402 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1403 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1404 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1405 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1406 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1407 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1408 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1409 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1410 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1411 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1412 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1413 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1414 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1415 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1416 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1417 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1418 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1419 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1420 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1421 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1422 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1423 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1424 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1425 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1426 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1427 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1428 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1429 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1430 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1431 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1432 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1433 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1434 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1435 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1436 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1437 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1438 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1439 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1440 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1441 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1442 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1443 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1444 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1445 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1446 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1447 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1448 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1449 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1450 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1451 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1452 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1453 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1454 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1455 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1456 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1457 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1458 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1459 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1460 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1461 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1462 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1463 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1464 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1465 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1466 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1467 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1468 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1469 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1470 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1471 | { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, | ||
1472 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, | ||
1473 | { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, | ||
1474 | @@ -2812,6 +3102,46 @@ | ||
1475 | RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1476 | { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, | ||
1477 | RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1478 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1479 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1480 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1481 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1482 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1483 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1484 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1485 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1486 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1487 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1488 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1489 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1490 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1491 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1492 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1493 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1494 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1495 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1496 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1497 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1498 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1499 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1500 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1501 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1502 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1503 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1504 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1505 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1506 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1507 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1508 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1509 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1510 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1511 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1512 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1513 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1514 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1515 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1516 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1517 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1518 | { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, | ||
1519 | RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1520 | { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, | ||
1521 | @@ -3016,6 +3346,222 @@ | ||
1522 | RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1523 | { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, | ||
1524 | RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1525 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1526 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1527 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1528 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1529 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1530 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1531 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1532 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1533 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1534 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1535 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1536 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1537 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1538 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1539 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1540 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1541 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1542 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1543 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1544 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1545 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1546 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1547 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1548 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1549 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1550 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1551 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1552 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1553 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1554 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1555 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1556 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1557 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1558 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1559 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1560 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1561 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1562 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1563 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1564 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1565 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1566 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1567 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1568 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1569 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1570 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1571 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1572 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1573 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1574 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1575 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1576 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1577 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1578 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1579 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1580 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1581 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1582 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1583 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1584 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1585 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1586 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1587 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1588 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1589 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1590 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1591 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1592 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1593 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1594 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1595 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1596 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1597 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1598 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1599 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1600 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1601 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1602 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1603 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1604 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1605 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1606 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1607 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1608 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1609 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1610 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1611 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1612 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1613 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1614 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1615 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1616 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1617 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1618 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1619 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1620 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1621 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1622 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1623 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1624 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1625 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1626 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1627 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1628 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1629 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1630 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1631 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1632 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1633 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1634 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1635 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1636 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1637 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1638 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1639 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1640 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1641 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1642 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1643 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1644 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1645 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1646 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1647 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1648 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1649 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1650 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1651 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1652 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1653 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1654 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1655 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1656 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1657 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1658 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1659 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1660 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1661 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1662 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1663 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1664 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1665 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1666 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1667 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1668 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1669 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1670 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1671 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1672 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1673 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1674 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1675 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1676 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1677 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1678 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1679 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1680 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1681 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1682 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1683 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1684 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1685 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1686 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1687 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1688 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1689 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1690 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1691 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1692 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1693 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1694 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1695 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1696 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1697 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1698 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1699 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1700 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1701 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1702 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1703 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1704 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1705 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1706 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1707 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1708 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1709 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1710 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1711 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1712 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1713 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1714 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1715 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1716 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1717 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1718 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1719 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1720 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1721 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1722 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1723 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1724 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1725 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1726 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1727 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1728 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1729 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1730 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1731 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1732 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1733 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1734 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1735 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1736 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1737 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1738 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1739 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1740 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1741 | { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, | ||
1742 | RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, | ||
1743 | { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, | ||
1744 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.h gcc-4.6.2/gcc/config/rs6000/rs6000.h | ||
1745 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.h 2011-07-27 13:17:15.000000000 -0500 | ||
1746 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.h 2012-03-06 12:16:25.582039002 -0600 | ||
1747 | @@ -168,6 +168,8 @@ | ||
1748 | %{mcpu=e300c3: -me300} \ | ||
1749 | %{mcpu=e500mc: -me500mc} \ | ||
1750 | %{mcpu=e500mc64: -me500mc64} \ | ||
1751 | +%{mcpu=e5500: -me5500} \ | ||
1752 | +%{mcpu=e6500: -me6500} \ | ||
1753 | %{maltivec: -maltivec} \ | ||
1754 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ | ||
1755 | -many" | ||
1756 | @@ -477,13 +479,15 @@ | ||
1757 | |||
1758 | #define TARGET_FCTIDZ TARGET_FCFID | ||
1759 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | ||
1760 | -#define TARGET_LFIWAX TARGET_CMPB | ||
1761 | -#define TARGET_LFIWZX TARGET_POPCNTD | ||
1762 | -#define TARGET_FCFIDS TARGET_POPCNTD | ||
1763 | -#define TARGET_FCFIDU TARGET_POPCNTD | ||
1764 | -#define TARGET_FCFIDUS TARGET_POPCNTD | ||
1765 | -#define TARGET_FCTIDUZ TARGET_POPCNTD | ||
1766 | -#define TARGET_FCTIWUZ TARGET_POPCNTD | ||
1767 | +#define TARGET_LFIWAX (TARGET_CMPB && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1768 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1769 | +#define TARGET_LFIWZX (TARGET_POPCNTD && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1770 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1771 | +#define TARGET_FCFIDS TARGET_LFIWZX | ||
1772 | +#define TARGET_FCFIDU TARGET_LFIWZX | ||
1773 | +#define TARGET_FCFIDUS TARGET_LFIWZX | ||
1774 | +#define TARGET_FCTIDUZ TARGET_LFIWZX | ||
1775 | +#define TARGET_FCTIWUZ TARGET_LFIWZX | ||
1776 | |||
1777 | /* E500 processors only support plain "sync", not lwsync. */ | ||
1778 | #define TARGET_NO_LWSYNC TARGET_E500 | ||
1779 | @@ -494,10 +498,14 @@ | ||
1780 | |||
1781 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ | ||
1782 | && TARGET_DOUBLE_FLOAT \ | ||
1783 | - && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) | ||
1784 | + && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) \ | ||
1785 | + && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1786 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1787 | |||
1788 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | ||
1789 | - && TARGET_FPRS && TARGET_SINGLE_FLOAT) | ||
1790 | + && TARGET_FPRS && TARGET_SINGLE_FLOAT \ | ||
1791 | + && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1792 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1793 | |||
1794 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ | ||
1795 | && TARGET_DOUBLE_FLOAT \ | ||
1796 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.md gcc-4.6.2/gcc/config/rs6000/rs6000.md | ||
1797 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.md 2011-09-19 11:41:20.000000000 -0500 | ||
1798 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.md 2012-03-06 12:16:25.584039002 -0600 | ||
1799 | @@ -126,7 +126,7 @@ | ||
1800 | |||
1801 | ;; Define an insn type attribute. This is used in function unit delay | ||
1802 | ;; computations. | ||
1803 | -(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel" | ||
1804 | +(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt" | ||
1805 | (const_string "integer")) | ||
1806 | |||
1807 | ;; Define floating point instruction sub-types for use with Xfpu.md | ||
1808 | @@ -148,7 +148,7 @@ | ||
1809 | ;; Processor type -- this attribute must exactly match the processor_type | ||
1810 | ;; enumeration in rs6000.h. | ||
1811 | |||
1812 | -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan" | ||
1813 | +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan" | ||
1814 | (const (symbol_ref "rs6000_cpu_attr"))) | ||
1815 | |||
1816 | |||
1817 | @@ -176,6 +176,8 @@ | ||
1818 | (include "e300c2c3.md") | ||
1819 | (include "e500mc.md") | ||
1820 | (include "e500mc64.md") | ||
1821 | +(include "e5500.md") | ||
1822 | +(include "e6500.md") | ||
1823 | (include "power4.md") | ||
1824 | (include "power5.md") | ||
1825 | (include "power6.md") | ||
1826 | @@ -2302,13 +2304,17 @@ | ||
1827 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | ||
1828 | UNSPEC_POPCNTB))] | ||
1829 | "TARGET_POPCNTB" | ||
1830 | - "popcntb %0,%1") | ||
1831 | + "popcntb %0,%1" | ||
1832 | + [(set_attr "length" "4") | ||
1833 | + (set_attr "type" "popcnt")]) | ||
1834 | |||
1835 | (define_insn "popcntd<mode>2" | ||
1836 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | ||
1837 | (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | ||
1838 | "TARGET_POPCNTD" | ||
1839 | - "popcnt<wd> %0,%1") | ||
1840 | + "popcnt<wd> %0,%1" | ||
1841 | + [(set_attr "length" "4") | ||
1842 | + (set_attr "type" "popcnt")]) | ||
1843 | |||
1844 | (define_expand "popcount<mode>2" | ||
1845 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") | ||
1846 | @@ -5957,10 +5963,10 @@ | ||
1847 | && ((TARGET_PPC_GFXOPT | ||
1848 | && !HONOR_NANS (<MODE>mode) | ||
1849 | && !HONOR_SIGNED_ZEROS (<MODE>mode)) | ||
1850 | - || TARGET_CMPB | ||
1851 | + || TARGET_LFIWAX | ||
1852 | || VECTOR_UNIT_VSX_P (<MODE>mode))" | ||
1853 | { | ||
1854 | - if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode)) | ||
1855 | + if (TARGET_LFIWAX || VECTOR_UNIT_VSX_P (<MODE>mode)) | ||
1856 | { | ||
1857 | emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1], | ||
1858 | operands[2])); | ||
1859 | @@ -5979,7 +5985,7 @@ | ||
1860 | (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>") | ||
1861 | (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")] | ||
1862 | UNSPEC_COPYSIGN))] | ||
1863 | - "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)" | ||
1864 | + "TARGET_LFIWAX && !VECTOR_UNIT_VSX_P (<MODE>mode)" | ||
1865 | "fcpsgn %0,%2,%1" | ||
1866 | [(set_attr "type" "fp")]) | ||
1867 | |||
1868 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.opt gcc-4.6.2/gcc/config/rs6000/rs6000.opt | ||
1869 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.opt 2010-11-29 19:47:54.000000000 -0600 | ||
1870 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.opt 2012-03-06 12:16:25.584039002 -0600 | ||
1871 | @@ -179,6 +179,10 @@ | ||
1872 | Target Report Mask(ALTIVEC) Save | ||
1873 | Use AltiVec instructions | ||
1874 | |||
1875 | +maltivec2 | ||
1876 | +Target Report Mask(ALTIVEC2) Save | ||
1877 | +Use AltiVec PowerPC V2.07 instructions | ||
1878 | + | ||
1879 | mhard-dfp | ||
1880 | Target Report Mask(DFP) Save | ||
1881 | Use decimal floating point instructions | ||
1882 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000-opts.h gcc-4.6.2/gcc/config/rs6000/rs6000-opts.h | ||
1883 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000-opts.h 2010-11-19 11:27:18.000000000 -0600 | ||
1884 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000-opts.h 2012-03-06 12:16:25.584039002 -0600 | ||
1885 | @@ -53,6 +53,8 @@ | ||
1886 | PROCESSOR_PPCE300C3, | ||
1887 | PROCESSOR_PPCE500MC, | ||
1888 | PROCESSOR_PPCE500MC64, | ||
1889 | + PROCESSOR_PPCE5500, | ||
1890 | + PROCESSOR_PPCE6500, | ||
1891 | PROCESSOR_POWER4, | ||
1892 | PROCESSOR_POWER5, | ||
1893 | PROCESSOR_POWER6, | ||
1894 | diff -ruN gcc-4.6.2-orig/gcc/config.gcc gcc-4.6.2/gcc/config.gcc | ||
1895 | --- gcc-4.6.2-orig/gcc/config.gcc 2011-07-22 11:44:50.000000000 -0500 | ||
1896 | +++ gcc-4.6.2/gcc/config.gcc 2012-03-06 12:16:25.585039002 -0600 | ||
1897 | @@ -396,7 +396,7 @@ | ||
1898 | extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h" | ||
1899 | need_64bit_hwint=yes | ||
1900 | case x$with_cpu in | ||
1901 | - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64) | ||
1902 | + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500) | ||
1903 | cpu_is_64bit=yes | ||
1904 | ;; | ||
1905 | esac | ||
1906 | @@ -3501,8 +3501,8 @@ | ||
1907 | | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | ||
1908 | | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ | ||
1909 | | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ | ||
1910 | - | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\ | ||
1911 | - | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) | ||
1912 | + | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | e6500 \ | ||
1913 | + | titan | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) | ||
1914 | # OK | ||
1915 | ;; | ||
1916 | *) | ||
1917 | diff -ruN gcc-4.6.2-orig/gcc/doc/extend.texi gcc-4.6.2/gcc/doc/extend.texi | ||
1918 | --- gcc-4.6.2-orig/gcc/doc/extend.texi 2011-10-24 09:55:45.000000000 -0500 | ||
1919 | +++ gcc-4.6.2/gcc/doc/extend.texi 2012-03-06 12:56:49.399039002 -0600 | ||
1920 | @@ -12509,6 +12509,291 @@ | ||
1921 | @samp{vec_vsx_st} builtins will always generate the VSX @samp{LXVD2X}, | ||
1922 | @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. | ||
1923 | |||
1924 | +Using @option{-maltivec2} will extend the Altivec interface with the | ||
1925 | +following additional functions: | ||
1926 | + | ||
1927 | +@smallexample | ||
1928 | +vector unsigned char vec_absd (vector unsigned char, vector unsigned char); | ||
1929 | +vector unsigned char vec_absd (vector bool char, vector unsigned char); | ||
1930 | +vector unsigned char vec_absd (vector unsigned char, vector bool char); | ||
1931 | +vector unsigned short vec_absd (vector unsigned short, vector unsigned short); | ||
1932 | +vector unsigned short vec_absd (vector bool short, vector unsigned short); | ||
1933 | +vector unsigned short vec_absd (vector unsigned short, vector bool short); | ||
1934 | +vector unsigned int vec_absd (vector unsigned int, vector unsigned int); | ||
1935 | +vector unsigned int vec_absd (vector bool int, vector unsigned int); | ||
1936 | +vector unsigned int vec_absd (vector unsigned int, vector bool int); | ||
1937 | + | ||
1938 | +vector signed char vec_lvexbx (long, signed char *); | ||
1939 | +vector unsigned char vec_lvexbx (long, unsigned char *); | ||
1940 | +vector signed short vec_lvexhx (long, signed short *); | ||
1941 | +vector unsigned short vec_lvexhx (long, unsigned short *); | ||
1942 | +vector float vec_lvexwx (long, float *); | ||
1943 | +vector signed int vec_lvexwx (long, signed int *); | ||
1944 | +vector unsigned int vec_lvexwx (long, unsigned int *); | ||
1945 | +vector signed int vec_lvexwx (long, signed long *); | ||
1946 | +vector unsigned int vec_lvexwx (long, unsigned long *); | ||
1947 | + | ||
1948 | +void vec_stvexbx (vector signed char, long, signed char *); | ||
1949 | +void vec_stvexbx (vector unsigned char, long, unsigned char *); | ||
1950 | +void vec_stvexbx (vector bool char, long, signed char *); | ||
1951 | +void vec_stvexbx (vector bool char, long, unsigned char *); | ||
1952 | +void vec_stvexbx (vector signed char, long, void *); | ||
1953 | +void vec_stvexbx (vector unsigned char, long, void *); | ||
1954 | +void vec_stvexhx (vector signed short, long, signed short *); | ||
1955 | +void vec_stvexhx (vector unsigned short, long, unsigned short *); | ||
1956 | +void vec_stvexhx (vector bool short, long, signed short *); | ||
1957 | +void vec_stvexhx (vector bool short, long, unsigned short *); | ||
1958 | +void vec_stvexhx (vector signed short, long, void *); | ||
1959 | +void vec_stvexhx (vector unsigned short, long, void *); | ||
1960 | +void vec_stvexwx (vector float, long, float *); | ||
1961 | +void vec_stvexwx (vector signed int, long, signed int *); | ||
1962 | +void vec_stvexwx (vector unsigned int, long, unsigned int *); | ||
1963 | +void vec_stvexwx (vector bool int, long, signed int *); | ||
1964 | +void vec_stvexwx (vector bool int, long, unsigned int *); | ||
1965 | +void vec_stvexwx (vector float, long, void *); | ||
1966 | +void vec_stvexwx (vector signed int, long, void *); | ||
1967 | +void vec_stvexwx (vector unsigned int, long, void *); | ||
1968 | + | ||
1969 | +vector float vec_lvtlx (long, vector float *); | ||
1970 | +vector float vec_lvtlx (long, float *); | ||
1971 | +vector bool int vec_lvtlx (long, vector bool int *); | ||
1972 | +vector signed int vec_lvtlx (long, vector signed int *); | ||
1973 | +vector signed int vec_lvtlx (long, signed int *); | ||
1974 | +vector unsigned int vec_lvtlx (long, vector unsigned int *); | ||
1975 | +vector unsigned int vec_lvtlx (long, unsigned int *); | ||
1976 | +vector bool short vec_lvtlx (long, vector bool short *); | ||
1977 | +vector pixel vec_lvtlx (long, vector pixel *); | ||
1978 | +vector signed short vec_lvtlx (long, vector signed short *); | ||
1979 | +vector signed short vec_lvtlx (long, signed short *); | ||
1980 | +vector unsigned short vec_lvtlx (long, vector unsigned short *); | ||
1981 | +vector unsigned short vec_lvtlx (long, unsigned short *); | ||
1982 | +vector bool char vec_lvtlx (long, vector bool char *); | ||
1983 | +vector signed char vec_lvtlx (long, vector signed char *); | ||
1984 | +vector signed char vec_lvtlx (long, signed char *); | ||
1985 | +vector unsigned char vec_lvtlx (long, vector unsigned char *); | ||
1986 | +vector unsigned char vec_lvtlx (long, unsigned char *); | ||
1987 | +vector float vec_lvtlxl (long, vector float *); | ||
1988 | +vector float vec_lvtlxl (long, float *); | ||
1989 | +vector bool int vec_lvtlxl (long, vector bool int *); | ||
1990 | +vector signed int vec_lvtlxl (long, vector signed int *); | ||
1991 | +vector signed int vec_lvtlxl (long, signed int *); | ||
1992 | +vector unsigned int vec_lvtlxl (long, vector unsigned int *); | ||
1993 | +vector unsigned int vec_lvtlxl (long, unsigned int *); | ||
1994 | +vector bool short vec_lvtlxl (long, vector bool short *); | ||
1995 | +vector pixel vec_lvtlxl (long, vector pixel *); | ||
1996 | +vector signed short vec_lvtlxl (long, vector signed short *); | ||
1997 | +vector signed short vec_lvtlxl (long, signed short *); | ||
1998 | +vector unsigned short vec_lvtlxl (long, vector unsigned short *); | ||
1999 | +vector unsigned short vec_lvtlxl (long, unsigned short *); | ||
2000 | +vector bool char vec_lvtlxl (long, vector bool char *); | ||
2001 | +vector signed char vec_lvtlxl (long, vector signed char *); | ||
2002 | +vector signed char vec_lvtlxl (long, signed char *); | ||
2003 | +vector unsigned char vec_lvtlxl (long, vector unsigned char *); | ||
2004 | +vector unsigned char vec_lvtlxl (long, unsigned char *); | ||
2005 | +vector float vec_lvtrx (long, vector float *); | ||
2006 | +vector float vec_lvtrx (long, float *); | ||
2007 | +vector bool int vec_lvtrx (long, vector bool int *); | ||
2008 | +vector signed int vec_lvtrx (long, vector signed int *); | ||
2009 | +vector signed int vec_lvtrx (long, signed int *); | ||
2010 | +vector unsigned int vec_lvtrx (long, vector unsigned int *); | ||
2011 | +vector unsigned int vec_lvtrx (long, unsigned int *); | ||
2012 | +vector bool short vec_lvtrx (long, vector bool short *); | ||
2013 | +vector pixel vec_lvtrx (long, vector pixel *); | ||
2014 | +vector signed short vec_lvtrx (long, vector signed short *); | ||
2015 | +vector signed short vec_lvtrx (long, signed short *); | ||
2016 | +vector unsigned short vec_lvtrx (long, vector unsigned short *); | ||
2017 | +vector unsigned short vec_lvtrx (long, unsigned short *); | ||
2018 | +vector bool char vec_lvtrx (long, vector bool char *); | ||
2019 | +vector signed char vec_lvtrx (long, vector signed char *); | ||
2020 | +vector signed char vec_lvtrx (long, signed char *); | ||
2021 | +vector unsigned char vec_lvtrx (long, vector unsigned char *); | ||
2022 | +vector unsigned char vec_lvtrx (long, unsigned char *); | ||
2023 | +vector float vec_lvtrxl (long, vector float *); | ||
2024 | +vector float vec_lvtrxl (long, float *); | ||
2025 | +vector bool int vec_lvtrxl (long, vector bool int *); | ||
2026 | +vector signed int vec_lvtrxl (long, vector signed int *); | ||
2027 | +vector signed int vec_lvtrxl (long, signed int *); | ||
2028 | +vector unsigned int vec_lvtrxl (long, vector unsigned int *); | ||
2029 | +vector unsigned int vec_lvtrxl (long, unsigned int *); | ||
2030 | +vector bool short vec_lvtrxl (long, vector bool short *); | ||
2031 | +vector pixel vec_lvtrxl (long, vector pixel *); | ||
2032 | +vector signed short vec_lvtrxl (long, vector signed short *); | ||
2033 | +vector signed short vec_lvtrxl (long, signed short *); | ||
2034 | +vector unsigned short vec_lvtrxl (long, vector unsigned short *); | ||
2035 | +vector unsigned short vec_lvtrxl (long, unsigned short *); | ||
2036 | +vector bool char vec_lvtrxl (long, vector bool char *); | ||
2037 | +vector signed char vec_lvtrxl (long, vector signed char *); | ||
2038 | +vector signed char vec_lvtrxl (long, signed char *); | ||
2039 | +vector unsigned char vec_lvtrxl (long, vector unsigned char *); | ||
2040 | +vector unsigned char vec_lvtrxl (long, unsigned char *); | ||
2041 | + | ||
2042 | +void vec_stvflx (vector float, long, vector float *); | ||
2043 | +void vec_stvflx (vector float, long, float *); | ||
2044 | +void vec_stvflx (vector bool int, long, vector bool int *); | ||
2045 | +void vec_stvflx (vector signed int, long, vector signed int *); | ||
2046 | +void vec_stvflx (vector signed int, long, signed int *); | ||
2047 | +void vec_stvflx (vector unsigned int, long, vector unsigned int *); | ||
2048 | +void vec_stvflx (vector unsigned int, long, unsigned int *); | ||
2049 | +void vec_stvflx (vector bool short, long, vector bool short *); | ||
2050 | +void vec_stvflx (vector pixel, long, vector pixel *); | ||
2051 | +void vec_stvflx (vector signed short, long, vector signed short *); | ||
2052 | +void vec_stvflx (vector signed short, long, signed short *); | ||
2053 | +void vec_stvflx (vector unsigned short, long, vector unsigned short *); | ||
2054 | +void vec_stvflx (vector unsigned short, long, unsigned short *); | ||
2055 | +void vec_stvflx (vector bool char, long, vector bool char *); | ||
2056 | +void vec_stvflx (vector signed char, long, vector signed char *); | ||
2057 | +void vec_stvflx (vector signed char, long, signed char *); | ||
2058 | +void vec_stvflx (vector unsigned char, long, vector unsigned char *); | ||
2059 | +void vec_stvflx (vector unsigned char, long, unsigned char *); | ||
2060 | +void vec_stvflxl (vector float, long, vector float *); | ||
2061 | +void vec_stvflxl (vector float, long, float *); | ||
2062 | +void vec_stvflxl (vector bool int, long, vector bool int *); | ||
2063 | +void vec_stvflxl (vector signed int, long, vector signed int *); | ||
2064 | +void vec_stvflxl (vector signed int, long, signed int *); | ||
2065 | +void vec_stvflxl (vector unsigned int, long, vector unsigned int *); | ||
2066 | +void vec_stvflxl (vector unsigned int, long, unsigned int *); | ||
2067 | +void vec_stvflxl (vector bool short, long, vector bool short *); | ||
2068 | +void vec_stvflxl (vector pixel, long, vector pixel *); | ||
2069 | +void vec_stvflxl (vector signed short, long, vector signed short *); | ||
2070 | +void vec_stvflxl (vector signed short, long, signed short *); | ||
2071 | +void vec_stvflxl (vector unsigned short, long, vector unsigned short *); | ||
2072 | +void vec_stvflxl (vector unsigned short, long, unsigned short *); | ||
2073 | +void vec_stvflxl (vector bool char, long, vector bool char *); | ||
2074 | +void vec_stvflxl (vector signed char, long, vector signed char *); | ||
2075 | +void vec_stvflxl (vector signed char, long, signed char *); | ||
2076 | +void vec_stvflxl (vector unsigned char, long, vector unsigned char *); | ||
2077 | +void vec_stvflxl (vector unsigned char, long, unsigned char *); | ||
2078 | +void vec_stvfrx (vector float, long, vector float *); | ||
2079 | +void vec_stvfrx (vector float, long, float *); | ||
2080 | +void vec_stvfrx (vector bool int, long, vector bool int *); | ||
2081 | +void vec_stvfrx (vector signed int, long, vector signed int *); | ||
2082 | +void vec_stvfrx (vector signed int, long, signed int *); | ||
2083 | +void vec_stvfrx (vector unsigned int, long, vector unsigned int *); | ||
2084 | +void vec_stvfrx (vector unsigned int, long, unsigned int *); | ||
2085 | +void vec_stvfrx (vector bool short, long, vector bool short *); | ||
2086 | +void vec_stvfrx (vector pixel, long, vector pixel *); | ||
2087 | +void vec_stvfrx (vector signed short, long, vector signed short *); | ||
2088 | +void vec_stvfrx (vector signed short, long, signed short *); | ||
2089 | +void vec_stvfrx (vector unsigned short, long, vector unsigned short *); | ||
2090 | +void vec_stvfrx (vector unsigned short, long, unsigned short *); | ||
2091 | +void vec_stvfrx (vector bool char, long, vector bool char *); | ||
2092 | +void vec_stvfrx (vector signed char, long, vector signed char *); | ||
2093 | +void vec_stvfrx (vector signed char, long, signed char *); | ||
2094 | +void vec_stvfrx (vector unsigned char, long, vector unsigned char *); | ||
2095 | +void vec_stvfrx (vector unsigned char, long, unsigned char *); | ||
2096 | +void vec_stvfrxl (vector float, long, vector float *); | ||
2097 | +void vec_stvfrxl (vector float, long, float *); | ||
2098 | +void vec_stvfrxl (vector bool int, long, vector bool int *); | ||
2099 | +void vec_stvfrxl (vector signed int, long, vector signed int *); | ||
2100 | +void vec_stvfrxl (vector signed int, long, signed int *); | ||
2101 | +void vec_stvfrxl (vector unsigned int, long, vector unsigned int *); | ||
2102 | +void vec_stvfrxl (vector unsigned int, long, unsigned int *); | ||
2103 | +void vec_stvfrxl (vector bool short, long, vector bool short *); | ||
2104 | +void vec_stvfrxl (vector pixel, long, vector pixel *); | ||
2105 | +void vec_stvfrxl (vector signed short, long, vector signed short *); | ||
2106 | +void vec_stvfrxl (vector signed short, long, signed short *); | ||
2107 | +void vec_stvfrxl (vector unsigned short, long, vector unsigned short *); | ||
2108 | +void vec_stvfrxl (vector unsigned short, long, unsigned short *); | ||
2109 | +void vec_stvfrxl (vector bool char, long, vector bool char *); | ||
2110 | +void vec_stvfrxl (vector signed char, long, vector signed char *); | ||
2111 | +void vec_stvfrxl (vector signed char, long, signed char *); | ||
2112 | +void vec_stvfrxl (vector unsigned char, long, vector unsigned char *); | ||
2113 | +void vec_stvfrxl (vector unsigned char, long, unsigned char *); | ||
2114 | + | ||
2115 | +vector float vec_lvswx (long, vector float *); | ||
2116 | +vector float vec_lvswx (long, float *); | ||
2117 | +vector bool int vec_lvswx (long, vector bool int *); | ||
2118 | +vector signed int vec_lvswx (long, vector signed int *); | ||
2119 | +vector signed int vec_lvswx (long, signed int *); | ||
2120 | +vector unsigned int vec_lvswx (long, vector unsigned int *); | ||
2121 | +vector unsigned int vec_lvswx (long, unsigned int *); | ||
2122 | +vector bool short vec_lvswx (long, vector bool short *); | ||
2123 | +vector pixel vec_lvswx (long, vector pixel *); | ||
2124 | +vector signed short vec_lvswx (long, vector signed short *); | ||
2125 | +vector signed short vec_lvswx (long, signed short *); | ||
2126 | +vector unsigned short vec_lvswx (long, vector unsigned short *); | ||
2127 | +vector unsigned short vec_lvswx (long, unsigned short *); | ||
2128 | +vector bool char vec_lvswx (long, vector bool char *); | ||
2129 | +vector signed char vec_lvswx (long, vector signed char *); | ||
2130 | +vector signed char vec_lvswx (long, signed char *); | ||
2131 | +vector unsigned char vec_lvswx (long, vector unsigned char *); | ||
2132 | +vector unsigned char vec_lvswx (long, unsigned char *); | ||
2133 | +vector float vec_lvswxl (long, vector float *); | ||
2134 | +vector float vec_lvswxl (long, float *); | ||
2135 | +vector bool int vec_lvswxl (long, vector bool int *); | ||
2136 | +vector signed int vec_lvswxl (long, vector signed int *); | ||
2137 | +vector signed int vec_lvswxl (long, signed int *); | ||
2138 | +vector unsigned int vec_lvswxl (long, vector unsigned int *); | ||
2139 | +vector unsigned int vec_lvswxl (long, unsigned int *); | ||
2140 | +vector bool short vec_lvswxl (long, vector bool short *); | ||
2141 | +vector pixel vec_lvswxl (long, vector pixel *); | ||
2142 | +vector signed short vec_lvswxl (long, vector signed short *); | ||
2143 | +vector signed short vec_lvswxl (long, signed short *); | ||
2144 | +vector unsigned short vec_lvswxl (long, vector unsigned short *); | ||
2145 | +vector unsigned short vec_lvswxl (long, unsigned short *); | ||
2146 | +vector bool char vec_lvswxl (long, vector bool char *); | ||
2147 | +vector signed char vec_lvswxl (long, vector signed char *); | ||
2148 | +vector signed char vec_lvswxl (long, signed char *); | ||
2149 | +vector unsigned char vec_lvswxl (long, vector unsigned char *); | ||
2150 | +vector unsigned char vec_lvswxl (long, unsigned char *); | ||
2151 | + | ||
2152 | +void vec_stvswx (vector float, long, vector float *); | ||
2153 | +void vec_stvswx (vector float, long, float *); | ||
2154 | +void vec_stvswx (vector bool int, long, vector bool int *); | ||
2155 | +void vec_stvswx (vector signed int, long, vector signed int *); | ||
2156 | +void vec_stvswx (vector signed int, long, signed int *); | ||
2157 | +void vec_stvswx (vector unsigned int, long, vector unsigned int *); | ||
2158 | +void vec_stvswx (vector unsigned int, long, unsigned int *); | ||
2159 | +void vec_stvswx (vector bool short, long, vector bool short *); | ||
2160 | +void vec_stvswx (vector pixel, long, vector pixel *); | ||
2161 | +void vec_stvswx (vector signed short, long, vector signed short *); | ||
2162 | +void vec_stvswx (vector signed short, long, signed short *); | ||
2163 | +void vec_stvswx (vector unsigned short, long, vector unsigned short *); | ||
2164 | +void vec_stvswx (vector unsigned short, long, unsigned short *); | ||
2165 | +void vec_stvswx (vector bool char, long, vector bool char *); | ||
2166 | +void vec_stvswx (vector signed char, long, vector signed char *); | ||
2167 | +void vec_stvswx (vector signed char, long, signed char *); | ||
2168 | +void vec_stvswx (vector unsigned char, long, vector unsigned char *); | ||
2169 | +void vec_stvswx (vector unsigned char, long, unsigned char *); | ||
2170 | +void vec_stvswxl (vector float, long, vector float *); | ||
2171 | +void vec_stvswxl (vector float, long, float *); | ||
2172 | +void vec_stvswxl (vector bool int, long, vector bool int *); | ||
2173 | +void vec_stvswxl (vector signed int, long, vector signed int *); | ||
2174 | +void vec_stvswxl (vector signed int, long, signed int *); | ||
2175 | +void vec_stvswxl (vector unsigned int, long, vector unsigned int *); | ||
2176 | +void vec_stvswxl (vector unsigned int, long, unsigned int *); | ||
2177 | +void vec_stvswxl (vector bool short, long, vector bool short *); | ||
2178 | +void vec_stvswxl (vector pixel, long, vector pixel *); | ||
2179 | +void vec_stvswxl (vector signed short, long, vector signed short *); | ||
2180 | +void vec_stvswxl (vector signed short, long, signed short *); | ||
2181 | +void vec_stvswxl (vector unsigned short, long, vector unsigned short *); | ||
2182 | +void vec_stvswxl (vector unsigned short, long, unsigned short *); | ||
2183 | +void vec_stvswxl (vector bool char, long, vector bool char *); | ||
2184 | +void vec_stvswxl (vector signed char, long, vector signed char *); | ||
2185 | +void vec_stvswxl (vector signed char, long, signed char *); | ||
2186 | +void vec_stvswxl (vector unsigned char, long, vector unsigned char *); | ||
2187 | +void vec_stvswxl (vector unsigned char, long, unsigned char *); | ||
2188 | + | ||
2189 | +vector float vec_lvsm (long, vector float *); | ||
2190 | +vector float vec_lvsm (long, float *); | ||
2191 | +vector bool int vec_lvsm (long, vector bool int *); | ||
2192 | +vector signed int vec_lvsm (long, vector signed int *); | ||
2193 | +vector signed int vec_lvsm (long, signed int *); | ||
2194 | +vector unsigned int vec_lvsm (long, vector unsigned int *); | ||
2195 | +vector unsigned int vec_lvsm (long, unsigned int *); | ||
2196 | +vector bool short vec_lvsm (long, vector bool short *); | ||
2197 | +vector pixel vec_lvsm (long, vector pixel *); | ||
2198 | +vector signed short vec_lvsm (long, vector signed short *); | ||
2199 | +vector signed short vec_lvsm (long, signed short *); | ||
2200 | +vector unsigned short vec_lvsm (long, vector unsigned short *); | ||
2201 | +vector unsigned short vec_lvsm (long, unsigned short *); | ||
2202 | +vector bool char vec_lvsm (long, vector bool char *); | ||
2203 | +vector signed char vec_lvsm (long, vector signed char *); | ||
2204 | +vector signed char vec_lvsm (long, signed char *); | ||
2205 | +vector unsigned char vec_lvsm (long, vector unsigned char *); | ||
2206 | +vector unsigned char vec_lvsm (long, unsigned char *); | ||
2207 | +@end smallexample | ||
2208 | + | ||
2209 | GCC provides a few other builtins on Powerpc to access certain instructions: | ||
2210 | @smallexample | ||
2211 | float __builtin_recipdivf (float, float); | ||
2212 | diff -ruN gcc-4.6.2-orig/gcc/doc/invoke.texi gcc-4.6.2/gcc/doc/invoke.texi | ||
2213 | --- gcc-4.6.2-orig/gcc/doc/invoke.texi 2011-10-24 07:22:21.000000000 -0500 | ||
2214 | +++ gcc-4.6.2/gcc/doc/invoke.texi 2012-03-06 12:56:49.402039002 -0600 | ||
2215 | @@ -770,7 +770,7 @@ | ||
2216 | -mcmodel=@var{code-model} @gol | ||
2217 | -mpower -mno-power -mpower2 -mno-power2 @gol | ||
2218 | -mpowerpc -mpowerpc64 -mno-powerpc @gol | ||
2219 | --maltivec -mno-altivec @gol | ||
2220 | +-maltivec -mno-altivec -maltivec2 -mno-altivec2 @gol | ||
2221 | -mpowerpc-gpopt -mno-powerpc-gpopt @gol | ||
2222 | -mpowerpc-gfxopt -mno-powerpc-gfxopt @gol | ||
2223 | -mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol | ||
2224 | @@ -15536,16 +15536,21 @@ | ||
2225 | The @option{-mpopcntb} option allows GCC to generate the popcount and | ||
2226 | double precision FP reciprocal estimate instruction implemented on the | ||
2227 | POWER5 processor and other processors that support the PowerPC V2.02 | ||
2228 | -architecture. | ||
2229 | -The @option{-mpopcntd} option allows GCC to generate the popcount | ||
2230 | -instruction implemented on the POWER7 processor and other processors | ||
2231 | -that support the PowerPC V2.06 architecture. | ||
2232 | +architecture. On the e5500 and e6500 processors, only the popcount | ||
2233 | +instruction is generated. | ||
2234 | +The @option{-mpopcntd} option allows GCC to generate the popcount and | ||
2235 | +double word to FP conversion instructions implemented on the POWER7 | ||
2236 | +processor and other processors that support the PowerPC V2.06 | ||
2237 | +architecture. On the e5500 and e6500 processors, only the popcount | ||
2238 | +instruction is generated. | ||
2239 | The @option{-mfprnd} option allows GCC to generate the FP round to | ||
2240 | integer instructions implemented on the POWER5+ processor and other | ||
2241 | processors that support the PowerPC V2.03 architecture. | ||
2242 | The @option{-mcmpb} option allows GCC to generate the compare bytes | ||
2243 | -instruction implemented on the POWER6 processor and other processors | ||
2244 | -that support the PowerPC V2.05 architecture. | ||
2245 | +and copy sign instructions implemented on the POWER6 processor and | ||
2246 | +other processors that support the PowerPC V2.05 architecture. On the | ||
2247 | +e5500 and e6500 processors, only the compare bytes instruction is | ||
2248 | +generated. | ||
2249 | The @option{-mmfpgpr} option allows GCC to generate the FP move to/from | ||
2250 | general purpose register instructions implemented on the POWER6X | ||
2251 | processor and other processors that support the extended PowerPC V2.05 | ||
2252 | @@ -15592,11 +15597,13 @@ | ||
2253 | @samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740}, | ||
2254 | @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, | ||
2255 | @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2}, | ||
2256 | -@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3}, | ||
2257 | -@samp{G4}, @samp{G5}, @samp{titan}, @samp{power}, @samp{power2}, @samp{power3}, | ||
2258 | -@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, | ||
2259 | -@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, | ||
2260 | -@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}. | ||
2261 | +@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500}, | ||
2262 | +@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, | ||
2263 | +@samp{titan}, @samp{power}, @samp{power2}, @samp{power3}, | ||
2264 | +@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, | ||
2265 | +@samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc}, | ||
2266 | +@samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, | ||
2267 | +and @samp{rs64}. | ||
2268 | |||
2269 | @option{-mcpu=common} selects a completely generic processor. Code | ||
2270 | generated under this option will run on any POWER or PowerPC processor. | ||
2271 | @@ -15617,10 +15624,11 @@ | ||
2272 | The @option{-mcpu} options automatically enable or disable the | ||
2273 | following options: | ||
2274 | |||
2275 | -@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol | ||
2276 | --mnew-mnemonics -mpopcntb -mpopcntd -mpower -mpower2 -mpowerpc64 @gol | ||
2277 | --mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol | ||
2278 | --msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} | ||
2279 | +@gccoptlist{-maltivec -maltivec2 -mfprnd -mhard-float -mmfcrf | ||
2280 | +-mmultiple @gol -mnew-mnemonics -mpopcntb -mpopcntd -mpower -mpower2 | ||
2281 | +-mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float | ||
2282 | +-mdouble-float @gol -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr | ||
2283 | +-mvsx} | ||
2284 | |||
2285 | The particular options set for any particular CPU will vary between | ||
2286 | compiler versions, depending on what setting seems to produce optimal | ||
2287 | @@ -15671,6 +15679,16 @@ | ||
2288 | @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI | ||
2289 | enhancements. | ||
2290 | |||
2291 | +@item -maltivec2 | ||
2292 | +@itemx -mno-altivec2 | ||
2293 | +@opindex maltivec2 | ||
2294 | +@opindex mno-altivec2 | ||
2295 | +Generate code that uses (does not use) AltiVec2 instructions, and also | ||
2296 | +enable the use of built-in functions that allow more direct access to | ||
2297 | +the AltiVec2 instruction set. You may also need to set | ||
2298 | +@option{-mabi=altivec} to adjust the current ABI with AltiVec ABI | ||
2299 | +enhancements. | ||
2300 | + | ||
2301 | @item -mvrsave | ||
2302 | @itemx -mno-vrsave | ||
2303 | @opindex mvrsave | ||
2304 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c | ||
2305 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c 1969-12-31 18:00:00.000000000 -0600 | ||
2306 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c 2012-03-06 12:31:05.152039004 -0600 | ||
2307 | @@ -0,0 +1,66 @@ | ||
2308 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2309 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2310 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2311 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2312 | +/* { dg-final { scan-assembler-times "lvtlx" 37 } } */ | ||
2313 | + | ||
2314 | +#include <altivec.h> | ||
2315 | + | ||
2316 | +typedef __vector signed char vsc; | ||
2317 | +typedef __vector signed short vss; | ||
2318 | +typedef __vector signed int vsi; | ||
2319 | +typedef __vector unsigned char vuc; | ||
2320 | +typedef __vector unsigned short vus; | ||
2321 | +typedef __vector unsigned int vui; | ||
2322 | +typedef __vector bool char vbc; | ||
2323 | +typedef __vector bool short vbs; | ||
2324 | +typedef __vector bool int vbi; | ||
2325 | +typedef __vector float vsf; | ||
2326 | +typedef __vector pixel vp; | ||
2327 | +typedef signed char sc; | ||
2328 | +typedef signed short ss; | ||
2329 | +typedef signed int si; | ||
2330 | +typedef signed long sl; | ||
2331 | +typedef unsigned char uc; | ||
2332 | +typedef unsigned short us; | ||
2333 | +typedef unsigned int ui; | ||
2334 | +typedef unsigned long ul; | ||
2335 | +typedef float sf; | ||
2336 | + | ||
2337 | +vsc lc1(long a, void *p) { return __builtin_altivec_lvtlx (a,p); } | ||
2338 | +vsf llx01(long a, vsf *p) { return __builtin_vec_lvtlx (a,p); } | ||
2339 | +vsf llx02(long a, sf *p) { return __builtin_vec_lvtlx (a,p); } | ||
2340 | +vbi llx03(long a, vbi *p) { return __builtin_vec_lvtlx (a,p); } | ||
2341 | +vsi llx04(long a, vsi *p) { return __builtin_vec_lvtlx (a,p); } | ||
2342 | +vsi llx05(long a, si *p) { return __builtin_vec_lvtlx (a,p); } | ||
2343 | +vui llx06(long a, vui *p) { return __builtin_vec_lvtlx (a,p); } | ||
2344 | +vui llx07(long a, ui *p) { return __builtin_vec_lvtlx (a,p); } | ||
2345 | +vbs llx08(long a, vbs *p) { return __builtin_vec_lvtlx (a,p); } | ||
2346 | +vp llx09(long a, vp *p) { return __builtin_vec_lvtlx (a,p); } | ||
2347 | +vss llx10(long a, vss *p) { return __builtin_vec_lvtlx (a,p); } | ||
2348 | +vss llx11(long a, ss *p) { return __builtin_vec_lvtlx (a,p); } | ||
2349 | +vus llx12(long a, vus *p) { return __builtin_vec_lvtlx (a,p); } | ||
2350 | +vus llx13(long a, us *p) { return __builtin_vec_lvtlx (a,p); } | ||
2351 | +vbc llx14(long a, vbc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2352 | +vsc llx15(long a, vsc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2353 | +vsc llx16(long a, sc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2354 | +vuc llx17(long a, vuc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2355 | +vuc llx18(long a, uc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2356 | +vsf Dllx01(long a, vsf *p) { return vec_lvtlx (a,p); } | ||
2357 | +vsf Dllx02(long a, sf *p) { return vec_lvtlx (a,p); } | ||
2358 | +vbi Dllx03(long a, vbi *p) { return vec_lvtlx (a,p); } | ||
2359 | +vsi Dllx04(long a, vsi *p) { return vec_lvtlx (a,p); } | ||
2360 | +vsi Dllx05(long a, si *p) { return vec_lvtlx (a,p); } | ||
2361 | +vui Dllx06(long a, vui *p) { return vec_lvtlx (a,p); } | ||
2362 | +vui Dllx07(long a, ui *p) { return vec_lvtlx (a,p); } | ||
2363 | +vbs Dllx08(long a, vbs *p) { return vec_lvtlx (a,p); } | ||
2364 | +vp Dllx09(long a, vp *p) { return vec_lvtlx (a,p); } | ||
2365 | +vss Dllx10(long a, vss *p) { return vec_lvtlx (a,p); } | ||
2366 | +vss Dllx11(long a, ss *p) { return vec_lvtlx (a,p); } | ||
2367 | +vus Dllx12(long a, vus *p) { return vec_lvtlx (a,p); } | ||
2368 | +vus Dllx13(long a, us *p) { return vec_lvtlx (a,p); } | ||
2369 | +vbc Dllx14(long a, vbc *p) { return vec_lvtlx (a,p); } | ||
2370 | +vsc Dllx15(long a, vsc *p) { return vec_lvtlx (a,p); } | ||
2371 | +vsc Dllx16(long a, sc *p) { return vec_lvtlx (a,p); } | ||
2372 | +vuc Dllx17(long a, vuc *p) { return vec_lvtlx (a,p); } | ||
2373 | +vuc Dllx18(long a, uc *p) { return vec_lvtlx (a,p); } | ||
2374 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c | ||
2375 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c 1969-12-31 18:00:00.000000000 -0600 | ||
2376 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c 2012-03-06 12:31:05.153039004 -0600 | ||
2377 | @@ -0,0 +1,66 @@ | ||
2378 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2379 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2380 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2381 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2382 | +/* { dg-final { scan-assembler-times "lvtlxl" 37 } } */ | ||
2383 | + | ||
2384 | +#include <altivec.h> | ||
2385 | + | ||
2386 | +typedef __vector signed char vsc; | ||
2387 | +typedef __vector signed short vss; | ||
2388 | +typedef __vector signed int vsi; | ||
2389 | +typedef __vector unsigned char vuc; | ||
2390 | +typedef __vector unsigned short vus; | ||
2391 | +typedef __vector unsigned int vui; | ||
2392 | +typedef __vector bool char vbc; | ||
2393 | +typedef __vector bool short vbs; | ||
2394 | +typedef __vector bool int vbi; | ||
2395 | +typedef __vector float vsf; | ||
2396 | +typedef __vector pixel vp; | ||
2397 | +typedef signed char sc; | ||
2398 | +typedef signed short ss; | ||
2399 | +typedef signed int si; | ||
2400 | +typedef signed long sl; | ||
2401 | +typedef unsigned char uc; | ||
2402 | +typedef unsigned short us; | ||
2403 | +typedef unsigned int ui; | ||
2404 | +typedef unsigned long ul; | ||
2405 | +typedef float sf; | ||
2406 | + | ||
2407 | +vsc lc2(long a, void *p) { return __builtin_altivec_lvtlxl (a,p); } | ||
2408 | +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2409 | +vsf llxl02(long a, sf *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2410 | +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2411 | +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2412 | +vsi llxl05(long a, si *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2413 | +vui llxl06(long a, vui *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2414 | +vui llxl07(long a, ui *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2415 | +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2416 | +vp llxl09(long a, vp *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2417 | +vss llxl10(long a, vss *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2418 | +vss llxl11(long a, ss *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2419 | +vus llxl12(long a, vus *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2420 | +vus llxl13(long a, us *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2421 | +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2422 | +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2423 | +vsc llxl16(long a, sc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2424 | +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2425 | +vuc llxl18(long a, uc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2426 | +vsf Dllxl01(long a, vsf *p) { return vec_lvtlxl (a,p); } | ||
2427 | +vsf Dllxl02(long a, sf *p) { return vec_lvtlxl (a,p); } | ||
2428 | +vbi Dllxl03(long a, vbi *p) { return vec_lvtlxl (a,p); } | ||
2429 | +vsi Dllxl04(long a, vsi *p) { return vec_lvtlxl (a,p); } | ||
2430 | +vsi Dllxl05(long a, si *p) { return vec_lvtlxl (a,p); } | ||
2431 | +vui Dllxl06(long a, vui *p) { return vec_lvtlxl (a,p); } | ||
2432 | +vui Dllxl07(long a, ui *p) { return vec_lvtlxl (a,p); } | ||
2433 | +vbs Dllxl08(long a, vbs *p) { return vec_lvtlxl (a,p); } | ||
2434 | +vp Dllxl09(long a, vp *p) { return vec_lvtlxl (a,p); } | ||
2435 | +vss Dllxl10(long a, vss *p) { return vec_lvtlxl (a,p); } | ||
2436 | +vss Dllxl11(long a, ss *p) { return vec_lvtlxl (a,p); } | ||
2437 | +vus Dllxl12(long a, vus *p) { return vec_lvtlxl (a,p); } | ||
2438 | +vus Dllxl13(long a, us *p) { return vec_lvtlxl (a,p); } | ||
2439 | +vbc Dllxl14(long a, vbc *p) { return vec_lvtlxl (a,p); } | ||
2440 | +vsc Dllxl15(long a, vsc *p) { return vec_lvtlxl (a,p); } | ||
2441 | +vsc Dllxl16(long a, sc *p) { return vec_lvtlxl (a,p); } | ||
2442 | +vuc Dllxl17(long a, vuc *p) { return vec_lvtlxl (a,p); } | ||
2443 | +vuc Dllxl18(long a, uc *p) { return vec_lvtlxl (a,p); } | ||
2444 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c | ||
2445 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c 1969-12-31 18:00:00.000000000 -0600 | ||
2446 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c 2012-03-06 12:31:05.153039004 -0600 | ||
2447 | @@ -0,0 +1,66 @@ | ||
2448 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2449 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2450 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2451 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2452 | +/* { dg-final { scan-assembler-times "lvtrx" 37 } } */ | ||
2453 | + | ||
2454 | +#include <altivec.h> | ||
2455 | + | ||
2456 | +typedef __vector signed char vsc; | ||
2457 | +typedef __vector signed short vss; | ||
2458 | +typedef __vector signed int vsi; | ||
2459 | +typedef __vector unsigned char vuc; | ||
2460 | +typedef __vector unsigned short vus; | ||
2461 | +typedef __vector unsigned int vui; | ||
2462 | +typedef __vector bool char vbc; | ||
2463 | +typedef __vector bool short vbs; | ||
2464 | +typedef __vector bool int vbi; | ||
2465 | +typedef __vector float vsf; | ||
2466 | +typedef __vector pixel vp; | ||
2467 | +typedef signed char sc; | ||
2468 | +typedef signed short ss; | ||
2469 | +typedef signed int si; | ||
2470 | +typedef signed long sl; | ||
2471 | +typedef unsigned char uc; | ||
2472 | +typedef unsigned short us; | ||
2473 | +typedef unsigned int ui; | ||
2474 | +typedef unsigned long ul; | ||
2475 | +typedef float sf; | ||
2476 | + | ||
2477 | +vsc lc3(long a, void *p) { return __builtin_altivec_lvtrx (a,p); } | ||
2478 | +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvtrx (a,p); } | ||
2479 | +vsf lrx02(long a, sf *p) { return __builtin_vec_lvtrx (a,p); } | ||
2480 | +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvtrx (a,p); } | ||
2481 | +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvtrx (a,p); } | ||
2482 | +vsi lrx05(long a, si *p) { return __builtin_vec_lvtrx (a,p); } | ||
2483 | +vui lrx06(long a, vui *p) { return __builtin_vec_lvtrx (a,p); } | ||
2484 | +vui lrx07(long a, ui *p) { return __builtin_vec_lvtrx (a,p); } | ||
2485 | +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvtrx (a,p); } | ||
2486 | +vp lrx09(long a, vp *p) { return __builtin_vec_lvtrx (a,p); } | ||
2487 | +vss lrx10(long a, vss *p) { return __builtin_vec_lvtrx (a,p); } | ||
2488 | +vss lrx11(long a, ss *p) { return __builtin_vec_lvtrx (a,p); } | ||
2489 | +vus lrx12(long a, vus *p) { return __builtin_vec_lvtrx (a,p); } | ||
2490 | +vus lrx13(long a, us *p) { return __builtin_vec_lvtrx (a,p); } | ||
2491 | +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2492 | +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2493 | +vsc lrx16(long a, sc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2494 | +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2495 | +vuc lrx18(long a, uc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2496 | +vsf Dlrx01(long a, vsf *p) { return vec_lvtrx (a,p); } | ||
2497 | +vsf Dlrx02(long a, sf *p) { return vec_lvtrx (a,p); } | ||
2498 | +vbi Dlrx03(long a, vbi *p) { return vec_lvtrx (a,p); } | ||
2499 | +vsi Dlrx04(long a, vsi *p) { return vec_lvtrx (a,p); } | ||
2500 | +vsi Dlrx05(long a, si *p) { return vec_lvtrx (a,p); } | ||
2501 | +vui Dlrx06(long a, vui *p) { return vec_lvtrx (a,p); } | ||
2502 | +vui Dlrx07(long a, ui *p) { return vec_lvtrx (a,p); } | ||
2503 | +vbs Dlrx08(long a, vbs *p) { return vec_lvtrx (a,p); } | ||
2504 | +vp Dlrx09(long a, vp *p) { return vec_lvtrx (a,p); } | ||
2505 | +vss Dlrx10(long a, vss *p) { return vec_lvtrx (a,p); } | ||
2506 | +vss Dlrx11(long a, ss *p) { return vec_lvtrx (a,p); } | ||
2507 | +vus Dlrx12(long a, vus *p) { return vec_lvtrx (a,p); } | ||
2508 | +vus Dlrx13(long a, us *p) { return vec_lvtrx (a,p); } | ||
2509 | +vbc Dlrx14(long a, vbc *p) { return vec_lvtrx (a,p); } | ||
2510 | +vsc Dlrx15(long a, vsc *p) { return vec_lvtrx (a,p); } | ||
2511 | +vsc Dlrx16(long a, sc *p) { return vec_lvtrx (a,p); } | ||
2512 | +vuc Dlrx17(long a, vuc *p) { return vec_lvtrx (a,p); } | ||
2513 | +vuc Dlrx18(long a, uc *p) { return vec_lvtrx (a,p); } | ||
2514 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c | ||
2515 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c 1969-12-31 18:00:00.000000000 -0600 | ||
2516 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c 2012-03-06 12:31:05.153039004 -0600 | ||
2517 | @@ -0,0 +1,66 @@ | ||
2518 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2519 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2520 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2521 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2522 | +/* { dg-final { scan-assembler-times "lvtrxl" 37 } } */ | ||
2523 | + | ||
2524 | +#include <altivec.h> | ||
2525 | + | ||
2526 | +typedef __vector signed char vsc; | ||
2527 | +typedef __vector signed short vss; | ||
2528 | +typedef __vector signed int vsi; | ||
2529 | +typedef __vector unsigned char vuc; | ||
2530 | +typedef __vector unsigned short vus; | ||
2531 | +typedef __vector unsigned int vui; | ||
2532 | +typedef __vector bool char vbc; | ||
2533 | +typedef __vector bool short vbs; | ||
2534 | +typedef __vector bool int vbi; | ||
2535 | +typedef __vector float vsf; | ||
2536 | +typedef __vector pixel vp; | ||
2537 | +typedef signed char sc; | ||
2538 | +typedef signed short ss; | ||
2539 | +typedef signed int si; | ||
2540 | +typedef signed long sl; | ||
2541 | +typedef unsigned char uc; | ||
2542 | +typedef unsigned short us; | ||
2543 | +typedef unsigned int ui; | ||
2544 | +typedef unsigned long ul; | ||
2545 | +typedef float sf; | ||
2546 | + | ||
2547 | +vsc lc4(long a, void *p) { return __builtin_altivec_lvtrxl (a,p); } | ||
2548 | +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2549 | +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2550 | +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2551 | +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2552 | +vsi lrxl05(long a, si *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2553 | +vui lrxl06(long a, vui *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2554 | +vui lrxl07(long a, ui *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2555 | +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2556 | +vp lrxl09(long a, vp *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2557 | +vss lrxl10(long a, vss *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2558 | +vss lrxl11(long a, ss *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2559 | +vus lrxl12(long a, vus *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2560 | +vus lrxl13(long a, us *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2561 | +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2562 | +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2563 | +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2564 | +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2565 | +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2566 | +vsf Dlrxl01(long a, vsf *p) { return vec_lvtrxl (a,p); } | ||
2567 | +vsf Dlrxl02(long a, sf *p) { return vec_lvtrxl (a,p); } | ||
2568 | +vbi Dlrxl03(long a, vbi *p) { return vec_lvtrxl (a,p); } | ||
2569 | +vsi Dlrxl04(long a, vsi *p) { return vec_lvtrxl (a,p); } | ||
2570 | +vsi Dlrxl05(long a, si *p) { return vec_lvtrxl (a,p); } | ||
2571 | +vui Dlrxl06(long a, vui *p) { return vec_lvtrxl (a,p); } | ||
2572 | +vui Dlrxl07(long a, ui *p) { return vec_lvtrxl (a,p); } | ||
2573 | +vbs Dlrxl08(long a, vbs *p) { return vec_lvtrxl (a,p); } | ||
2574 | +vp Dlrxl09(long a, vp *p) { return vec_lvtrxl (a,p); } | ||
2575 | +vss Dlrxl10(long a, vss *p) { return vec_lvtrxl (a,p); } | ||
2576 | +vss Dlrxl11(long a, ss *p) { return vec_lvtrxl (a,p); } | ||
2577 | +vus Dlrxl12(long a, vus *p) { return vec_lvtrxl (a,p); } | ||
2578 | +vus Dlrxl13(long a, us *p) { return vec_lvtrxl (a,p); } | ||
2579 | +vbc Dlrxl14(long a, vbc *p) { return vec_lvtrxl (a,p); } | ||
2580 | +vsc Dlrxl15(long a, vsc *p) { return vec_lvtrxl (a,p); } | ||
2581 | +vsc Dlrxl16(long a, sc *p) { return vec_lvtrxl (a,p); } | ||
2582 | +vuc Dlrxl17(long a, vuc *p) { return vec_lvtrxl (a,p); } | ||
2583 | +vuc Dlrxl18(long a, uc *p) { return vec_lvtrxl (a,p); } | ||
2584 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c | ||
2585 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c 1969-12-31 18:00:00.000000000 -0600 | ||
2586 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c 2012-03-06 12:31:05.154039003 -0600 | ||
2587 | @@ -0,0 +1,66 @@ | ||
2588 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2589 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2590 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2591 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2592 | +/* { dg-final { scan-assembler-times "stvflx" 37 } } */ | ||
2593 | + | ||
2594 | +#include <altivec.h> | ||
2595 | + | ||
2596 | +typedef __vector signed char vsc; | ||
2597 | +typedef __vector signed short vss; | ||
2598 | +typedef __vector signed int vsi; | ||
2599 | +typedef __vector unsigned char vuc; | ||
2600 | +typedef __vector unsigned short vus; | ||
2601 | +typedef __vector unsigned int vui; | ||
2602 | +typedef __vector bool char vbc; | ||
2603 | +typedef __vector bool short vbs; | ||
2604 | +typedef __vector bool int vbi; | ||
2605 | +typedef __vector float vsf; | ||
2606 | +typedef __vector pixel vp; | ||
2607 | +typedef signed char sc; | ||
2608 | +typedef signed short ss; | ||
2609 | +typedef signed int si; | ||
2610 | +typedef signed long sl; | ||
2611 | +typedef unsigned char uc; | ||
2612 | +typedef unsigned short us; | ||
2613 | +typedef unsigned int ui; | ||
2614 | +typedef unsigned long ul; | ||
2615 | +typedef float sf; | ||
2616 | + | ||
2617 | +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvflx (v,a,p); } | ||
2618 | +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvflx (v,a,p); } | ||
2619 | +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvflx (v,a,p); } | ||
2620 | +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvflx (v,a,p); } | ||
2621 | +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvflx (v,a,p); } | ||
2622 | +void slx05(vsi v, long a, si *p) { __builtin_vec_stvflx (v,a,p); } | ||
2623 | +void slx06(vui v, long a, vui *p) { __builtin_vec_stvflx (v,a,p); } | ||
2624 | +void slx07(vui v, long a, ui *p) { __builtin_vec_stvflx (v,a,p); } | ||
2625 | +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvflx (v,a,p); } | ||
2626 | +void slx09(vp v, long a, vp *p) { __builtin_vec_stvflx (v,a,p); } | ||
2627 | +void slx10(vss v, long a, vss *p) { __builtin_vec_stvflx (v,a,p); } | ||
2628 | +void slx11(vss v, long a, ss *p) { __builtin_vec_stvflx (v,a,p); } | ||
2629 | +void slx12(vus v, long a, vus *p) { __builtin_vec_stvflx (v,a,p); } | ||
2630 | +void slx13(vus v, long a, us *p) { __builtin_vec_stvflx (v,a,p); } | ||
2631 | +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2632 | +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2633 | +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2634 | +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2635 | +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2636 | +void Dslx01(vsf v, long a, vsf *p) { vec_stvflx (v,a,p); } | ||
2637 | +void Dslx02(vsf v, long a, sf *p) { vec_stvflx (v,a,p); } | ||
2638 | +void Dslx03(vbi v, long a, vbi *p) { vec_stvflx (v,a,p); } | ||
2639 | +void Dslx04(vsi v, long a, vsi *p) { vec_stvflx (v,a,p); } | ||
2640 | +void Dslx05(vsi v, long a, si *p) { vec_stvflx (v,a,p); } | ||
2641 | +void Dslx06(vui v, long a, vui *p) { vec_stvflx (v,a,p); } | ||
2642 | +void Dslx07(vui v, long a, ui *p) { vec_stvflx (v,a,p); } | ||
2643 | +void Dslx08(vbs v, long a, vbs *p) { vec_stvflx (v,a,p); } | ||
2644 | +void Dslx09(vp v, long a, vp *p) { vec_stvflx (v,a,p); } | ||
2645 | +void Dslx10(vss v, long a, vss *p) { vec_stvflx (v,a,p); } | ||
2646 | +void Dslx11(vss v, long a, ss *p) { vec_stvflx (v,a,p); } | ||
2647 | +void Dslx12(vus v, long a, vus *p) { vec_stvflx (v,a,p); } | ||
2648 | +void Dslx13(vus v, long a, us *p) { vec_stvflx (v,a,p); } | ||
2649 | +void Dslx14(vbc v, long a, vbc *p) { vec_stvflx (v,a,p); } | ||
2650 | +void Dslx15(vsc v, long a, vsc *p) { vec_stvflx (v,a,p); } | ||
2651 | +void Dslx16(vsc v, long a, sc *p) { vec_stvflx (v,a,p); } | ||
2652 | +void Dslx17(vuc v, long a, vuc *p) { vec_stvflx (v,a,p); } | ||
2653 | +void Dslx18(vuc v, long a, uc *p) { vec_stvflx (v,a,p); } | ||
2654 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c | ||
2655 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c 1969-12-31 18:00:00.000000000 -0600 | ||
2656 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c 2012-03-06 12:31:05.154039003 -0600 | ||
2657 | @@ -0,0 +1,66 @@ | ||
2658 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2659 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2660 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2661 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2662 | +/* { dg-final { scan-assembler-times "stvflxl" 37 } } */ | ||
2663 | + | ||
2664 | +#include <altivec.h> | ||
2665 | + | ||
2666 | +typedef __vector signed char vsc; | ||
2667 | +typedef __vector signed short vss; | ||
2668 | +typedef __vector signed int vsi; | ||
2669 | +typedef __vector unsigned char vuc; | ||
2670 | +typedef __vector unsigned short vus; | ||
2671 | +typedef __vector unsigned int vui; | ||
2672 | +typedef __vector bool char vbc; | ||
2673 | +typedef __vector bool short vbs; | ||
2674 | +typedef __vector bool int vbi; | ||
2675 | +typedef __vector float vsf; | ||
2676 | +typedef __vector pixel vp; | ||
2677 | +typedef signed char sc; | ||
2678 | +typedef signed short ss; | ||
2679 | +typedef signed int si; | ||
2680 | +typedef signed long sl; | ||
2681 | +typedef unsigned char uc; | ||
2682 | +typedef unsigned short us; | ||
2683 | +typedef unsigned int ui; | ||
2684 | +typedef unsigned long ul; | ||
2685 | +typedef float sf; | ||
2686 | + | ||
2687 | +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvflxl (v,a,p); } | ||
2688 | +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2689 | +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2690 | +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2691 | +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2692 | +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2693 | +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2694 | +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2695 | +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2696 | +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2697 | +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2698 | +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2699 | +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2700 | +void slxl13(vus v, long a, us *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2701 | +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2702 | +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2703 | +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2704 | +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2705 | +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2706 | +void Dslxl01(vsf v, long a, vsf *p) { vec_stvflxl (v,a,p); } | ||
2707 | +void Dslxl02(vsf v, long a, sf *p) { vec_stvflxl (v,a,p); } | ||
2708 | +void Dslxl03(vbi v, long a, vbi *p) { vec_stvflxl (v,a,p); } | ||
2709 | +void Dslxl04(vsi v, long a, vsi *p) { vec_stvflxl (v,a,p); } | ||
2710 | +void Dslxl05(vsi v, long a, si *p) { vec_stvflxl (v,a,p); } | ||
2711 | +void Dslxl06(vui v, long a, vui *p) { vec_stvflxl (v,a,p); } | ||
2712 | +void Dslxl07(vui v, long a, ui *p) { vec_stvflxl (v,a,p); } | ||
2713 | +void Dslxl08(vbs v, long a, vbs *p) { vec_stvflxl (v,a,p); } | ||
2714 | +void Dslxl09(vp v, long a, vp *p) { vec_stvflxl (v,a,p); } | ||
2715 | +void Dslxl10(vss v, long a, vss *p) { vec_stvflxl (v,a,p); } | ||
2716 | +void Dslxl11(vss v, long a, ss *p) { vec_stvflxl (v,a,p); } | ||
2717 | +void Dslxl12(vus v, long a, vus *p) { vec_stvflxl (v,a,p); } | ||
2718 | +void Dslxl13(vus v, long a, us *p) { vec_stvflxl (v,a,p); } | ||
2719 | +void Dslxl14(vbc v, long a, vbc *p) { vec_stvflxl (v,a,p); } | ||
2720 | +void Dslxl15(vsc v, long a, vsc *p) { vec_stvflxl (v,a,p); } | ||
2721 | +void Dslxl16(vsc v, long a, sc *p) { vec_stvflxl (v,a,p); } | ||
2722 | +void Dslxl17(vuc v, long a, vuc *p) { vec_stvflxl (v,a,p); } | ||
2723 | +void Dslxl18(vuc v, long a, uc *p) { vec_stvflxl (v,a,p); } | ||
2724 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c | ||
2725 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c 1969-12-31 18:00:00.000000000 -0600 | ||
2726 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c 2012-03-06 12:31:05.154039003 -0600 | ||
2727 | @@ -0,0 +1,66 @@ | ||
2728 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2729 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2730 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2731 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2732 | +/* { dg-final { scan-assembler-times "stvfrx" 37 } } */ | ||
2733 | + | ||
2734 | +#include <altivec.h> | ||
2735 | + | ||
2736 | +typedef __vector signed char vsc; | ||
2737 | +typedef __vector signed short vss; | ||
2738 | +typedef __vector signed int vsi; | ||
2739 | +typedef __vector unsigned char vuc; | ||
2740 | +typedef __vector unsigned short vus; | ||
2741 | +typedef __vector unsigned int vui; | ||
2742 | +typedef __vector bool char vbc; | ||
2743 | +typedef __vector bool short vbs; | ||
2744 | +typedef __vector bool int vbi; | ||
2745 | +typedef __vector float vsf; | ||
2746 | +typedef __vector pixel vp; | ||
2747 | +typedef signed char sc; | ||
2748 | +typedef signed short ss; | ||
2749 | +typedef signed int si; | ||
2750 | +typedef signed long sl; | ||
2751 | +typedef unsigned char uc; | ||
2752 | +typedef unsigned short us; | ||
2753 | +typedef unsigned int ui; | ||
2754 | +typedef unsigned long ul; | ||
2755 | +typedef float sf; | ||
2756 | + | ||
2757 | +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvfrx (v,a,p); } | ||
2758 | +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2759 | +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2760 | +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2761 | +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2762 | +void srx05(vsi v, long a, si *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2763 | +void srx06(vui v, long a, vui *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2764 | +void srx07(vui v, long a, ui *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2765 | +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2766 | +void srx09(vp v, long a, vp *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2767 | +void srx10(vss v, long a, vss *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2768 | +void srx11(vss v, long a, ss *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2769 | +void srx12(vus v, long a, vus *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2770 | +void srx13(vus v, long a, us *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2771 | +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2772 | +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2773 | +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2774 | +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2775 | +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2776 | +void Dsrx01(vsf v, long a, vsf *p) { vec_stvfrx (v,a,p); } | ||
2777 | +void Dsrx02(vsf v, long a, sf *p) { vec_stvfrx (v,a,p); } | ||
2778 | +void Dsrx03(vbi v, long a, vbi *p) { vec_stvfrx (v,a,p); } | ||
2779 | +void Dsrx04(vsi v, long a, vsi *p) { vec_stvfrx (v,a,p); } | ||
2780 | +void Dsrx05(vsi v, long a, si *p) { vec_stvfrx (v,a,p); } | ||
2781 | +void Dsrx06(vui v, long a, vui *p) { vec_stvfrx (v,a,p); } | ||
2782 | +void Dsrx07(vui v, long a, ui *p) { vec_stvfrx (v,a,p); } | ||
2783 | +void Dsrx08(vbs v, long a, vbs *p) { vec_stvfrx (v,a,p); } | ||
2784 | +void Dsrx09(vp v, long a, vp *p) { vec_stvfrx (v,a,p); } | ||
2785 | +void Dsrx10(vss v, long a, vss *p) { vec_stvfrx (v,a,p); } | ||
2786 | +void Dsrx11(vss v, long a, ss *p) { vec_stvfrx (v,a,p); } | ||
2787 | +void Dsrx12(vus v, long a, vus *p) { vec_stvfrx (v,a,p); } | ||
2788 | +void Dsrx13(vus v, long a, us *p) { vec_stvfrx (v,a,p); } | ||
2789 | +void Dsrx14(vbc v, long a, vbc *p) { vec_stvfrx (v,a,p); } | ||
2790 | +void Dsrx15(vsc v, long a, vsc *p) { vec_stvfrx (v,a,p); } | ||
2791 | +void Dsrx16(vsc v, long a, sc *p) { vec_stvfrx (v,a,p); } | ||
2792 | +void Dsrx17(vuc v, long a, vuc *p) { vec_stvfrx (v,a,p); } | ||
2793 | +void Dsrx18(vuc v, long a, uc *p) { vec_stvfrx (v,a,p); } | ||
2794 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c | ||
2795 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c 1969-12-31 18:00:00.000000000 -0600 | ||
2796 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c 2012-03-06 12:31:05.155039001 -0600 | ||
2797 | @@ -0,0 +1,66 @@ | ||
2798 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2799 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2800 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2801 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2802 | +/* { dg-final { scan-assembler-times "stvfrxl" 37 } } */ | ||
2803 | + | ||
2804 | +#include <altivec.h> | ||
2805 | + | ||
2806 | +typedef __vector signed char vsc; | ||
2807 | +typedef __vector signed short vss; | ||
2808 | +typedef __vector signed int vsi; | ||
2809 | +typedef __vector unsigned char vuc; | ||
2810 | +typedef __vector unsigned short vus; | ||
2811 | +typedef __vector unsigned int vui; | ||
2812 | +typedef __vector bool char vbc; | ||
2813 | +typedef __vector bool short vbs; | ||
2814 | +typedef __vector bool int vbi; | ||
2815 | +typedef __vector float vsf; | ||
2816 | +typedef __vector pixel vp; | ||
2817 | +typedef signed char sc; | ||
2818 | +typedef signed short ss; | ||
2819 | +typedef signed int si; | ||
2820 | +typedef signed long sl; | ||
2821 | +typedef unsigned char uc; | ||
2822 | +typedef unsigned short us; | ||
2823 | +typedef unsigned int ui; | ||
2824 | +typedef unsigned long ul; | ||
2825 | +typedef float sf; | ||
2826 | + | ||
2827 | +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvfrxl (v,a,p); } | ||
2828 | +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2829 | +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2830 | +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2831 | +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2832 | +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2833 | +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2834 | +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2835 | +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2836 | +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2837 | +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2838 | +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2839 | +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2840 | +void srxl13(vus v, long a, us *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2841 | +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2842 | +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2843 | +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2844 | +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2845 | +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2846 | +void Dsrxl01(vsf v, long a, vsf *p) { vec_stvfrxl (v,a,p); } | ||
2847 | +void Dsrxl02(vsf v, long a, sf *p) { vec_stvfrxl (v,a,p); } | ||
2848 | +void Dsrxl03(vbi v, long a, vbi *p) { vec_stvfrxl (v,a,p); } | ||
2849 | +void Dsrxl04(vsi v, long a, vsi *p) { vec_stvfrxl (v,a,p); } | ||
2850 | +void Dsrxl05(vsi v, long a, si *p) { vec_stvfrxl (v,a,p); } | ||
2851 | +void Dsrxl06(vui v, long a, vui *p) { vec_stvfrxl (v,a,p); } | ||
2852 | +void Dsrxl07(vui v, long a, ui *p) { vec_stvfrxl (v,a,p); } | ||
2853 | +void Dsrxl08(vbs v, long a, vbs *p) { vec_stvfrxl (v,a,p); } | ||
2854 | +void Dsrxl09(vp v, long a, vp *p) { vec_stvfrxl (v,a,p); } | ||
2855 | +void Dsrxl10(vss v, long a, vss *p) { vec_stvfrxl (v,a,p); } | ||
2856 | +void Dsrxl11(vss v, long a, ss *p) { vec_stvfrxl (v,a,p); } | ||
2857 | +void Dsrxl12(vus v, long a, vus *p) { vec_stvfrxl (v,a,p); } | ||
2858 | +void Dsrxl13(vus v, long a, us *p) { vec_stvfrxl (v,a,p); } | ||
2859 | +void Dsrxl14(vbc v, long a, vbc *p) { vec_stvfrxl (v,a,p); } | ||
2860 | +void Dsrxl15(vsc v, long a, vsc *p) { vec_stvfrxl (v,a,p); } | ||
2861 | +void Dsrxl16(vsc v, long a, sc *p) { vec_stvfrxl (v,a,p); } | ||
2862 | +void Dsrxl17(vuc v, long a, vuc *p) { vec_stvfrxl (v,a,p); } | ||
2863 | +void Dsrxl18(vuc v, long a, uc *p) { vec_stvfrxl (v,a,p); } | ||
2864 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c | ||
2865 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c 1969-12-31 18:00:00.000000000 -0600 | ||
2866 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c 2012-03-06 12:31:05.155039001 -0600 | ||
2867 | @@ -0,0 +1,66 @@ | ||
2868 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2869 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2870 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2871 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2872 | +/* { dg-final { scan-assembler-times "lvswx" 37 } } */ | ||
2873 | + | ||
2874 | +#include <altivec.h> | ||
2875 | + | ||
2876 | +typedef __vector signed char vsc; | ||
2877 | +typedef __vector signed short vss; | ||
2878 | +typedef __vector signed int vsi; | ||
2879 | +typedef __vector unsigned char vuc; | ||
2880 | +typedef __vector unsigned short vus; | ||
2881 | +typedef __vector unsigned int vui; | ||
2882 | +typedef __vector bool char vbc; | ||
2883 | +typedef __vector bool short vbs; | ||
2884 | +typedef __vector bool int vbi; | ||
2885 | +typedef __vector float vsf; | ||
2886 | +typedef __vector pixel vp; | ||
2887 | +typedef signed char sc; | ||
2888 | +typedef signed short ss; | ||
2889 | +typedef signed int si; | ||
2890 | +typedef signed long sl; | ||
2891 | +typedef unsigned char uc; | ||
2892 | +typedef unsigned short us; | ||
2893 | +typedef unsigned int ui; | ||
2894 | +typedef unsigned long ul; | ||
2895 | +typedef float sf; | ||
2896 | + | ||
2897 | +vsc ls1(long a, void *p) { return __builtin_altivec_lvswx (a,p); } | ||
2898 | +vsf ls01(long a, vsf *p) { return __builtin_vec_lvswx (a,p); } | ||
2899 | +vsf ls02(long a, sf *p) { return __builtin_vec_lvswx (a,p); } | ||
2900 | +vbi ls03(long a, vbi *p) { return __builtin_vec_lvswx (a,p); } | ||
2901 | +vsi ls04(long a, vsi *p) { return __builtin_vec_lvswx (a,p); } | ||
2902 | +vsi ls05(long a, si *p) { return __builtin_vec_lvswx (a,p); } | ||
2903 | +vui ls06(long a, vui *p) { return __builtin_vec_lvswx (a,p); } | ||
2904 | +vui ls07(long a, ui *p) { return __builtin_vec_lvswx (a,p); } | ||
2905 | +vbs ls08(long a, vbs *p) { return __builtin_vec_lvswx (a,p); } | ||
2906 | +vp ls09(long a, vp *p) { return __builtin_vec_lvswx (a,p); } | ||
2907 | +vss ls10(long a, vss *p) { return __builtin_vec_lvswx (a,p); } | ||
2908 | +vss ls11(long a, ss *p) { return __builtin_vec_lvswx (a,p); } | ||
2909 | +vus ls12(long a, vus *p) { return __builtin_vec_lvswx (a,p); } | ||
2910 | +vus ls13(long a, us *p) { return __builtin_vec_lvswx (a,p); } | ||
2911 | +vbc ls14(long a, vbc *p) { return __builtin_vec_lvswx (a,p); } | ||
2912 | +vsc ls15(long a, vsc *p) { return __builtin_vec_lvswx (a,p); } | ||
2913 | +vsc ls16(long a, sc *p) { return __builtin_vec_lvswx (a,p); } | ||
2914 | +vuc ls17(long a, vuc *p) { return __builtin_vec_lvswx (a,p); } | ||
2915 | +vuc ls18(long a, uc *p) { return __builtin_vec_lvswx (a,p); } | ||
2916 | +vsf Dls01(long a, vsf *p) { return vec_lvswx (a,p); } | ||
2917 | +vsf Dls02(long a, sf *p) { return vec_lvswx (a,p); } | ||
2918 | +vbi Dls03(long a, vbi *p) { return vec_lvswx (a,p); } | ||
2919 | +vsi Dls04(long a, vsi *p) { return vec_lvswx (a,p); } | ||
2920 | +vsi Dls05(long a, si *p) { return vec_lvswx (a,p); } | ||
2921 | +vui Dls06(long a, vui *p) { return vec_lvswx (a,p); } | ||
2922 | +vui Dls07(long a, ui *p) { return vec_lvswx (a,p); } | ||
2923 | +vbs Dls08(long a, vbs *p) { return vec_lvswx (a,p); } | ||
2924 | +vp Dls09(long a, vp *p) { return vec_lvswx (a,p); } | ||
2925 | +vss Dls10(long a, vss *p) { return vec_lvswx (a,p); } | ||
2926 | +vss Dls11(long a, ss *p) { return vec_lvswx (a,p); } | ||
2927 | +vus Dls12(long a, vus *p) { return vec_lvswx (a,p); } | ||
2928 | +vus Dls13(long a, us *p) { return vec_lvswx (a,p); } | ||
2929 | +vbc Dls14(long a, vbc *p) { return vec_lvswx (a,p); } | ||
2930 | +vsc Dls15(long a, vsc *p) { return vec_lvswx (a,p); } | ||
2931 | +vsc Dls16(long a, sc *p) { return vec_lvswx (a,p); } | ||
2932 | +vuc Dls17(long a, vuc *p) { return vec_lvswx (a,p); } | ||
2933 | +vuc Dls18(long a, uc *p) { return vec_lvswx (a,p); } | ||
2934 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c | ||
2935 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c 1969-12-31 18:00:00.000000000 -0600 | ||
2936 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c 2012-03-06 12:31:05.155039001 -0600 | ||
2937 | @@ -0,0 +1,66 @@ | ||
2938 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2939 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2940 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2941 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2942 | +/* { dg-final { scan-assembler-times "lvswxl" 37 } } */ | ||
2943 | + | ||
2944 | +#include <altivec.h> | ||
2945 | + | ||
2946 | +typedef __vector signed char vsc; | ||
2947 | +typedef __vector signed short vss; | ||
2948 | +typedef __vector signed int vsi; | ||
2949 | +typedef __vector unsigned char vuc; | ||
2950 | +typedef __vector unsigned short vus; | ||
2951 | +typedef __vector unsigned int vui; | ||
2952 | +typedef __vector bool char vbc; | ||
2953 | +typedef __vector bool short vbs; | ||
2954 | +typedef __vector bool int vbi; | ||
2955 | +typedef __vector float vsf; | ||
2956 | +typedef __vector pixel vp; | ||
2957 | +typedef signed char sc; | ||
2958 | +typedef signed short ss; | ||
2959 | +typedef signed int si; | ||
2960 | +typedef signed long sl; | ||
2961 | +typedef unsigned char uc; | ||
2962 | +typedef unsigned short us; | ||
2963 | +typedef unsigned int ui; | ||
2964 | +typedef unsigned long ul; | ||
2965 | +typedef float sf; | ||
2966 | + | ||
2967 | +vsc ls2l(long a, void *p) { return __builtin_altivec_lvswxl (a,p); } | ||
2968 | +vsf lsl01(long a, vsf *p) { return __builtin_vec_lvswxl (a,p); } | ||
2969 | +vsf lsl02(long a, sf *p) { return __builtin_vec_lvswxl (a,p); } | ||
2970 | +vbi lsl03(long a, vbi *p) { return __builtin_vec_lvswxl (a,p); } | ||
2971 | +vsi lsl04(long a, vsi *p) { return __builtin_vec_lvswxl (a,p); } | ||
2972 | +vsi lsl05(long a, si *p) { return __builtin_vec_lvswxl (a,p); } | ||
2973 | +vui lsl06(long a, vui *p) { return __builtin_vec_lvswxl (a,p); } | ||
2974 | +vui lsl07(long a, ui *p) { return __builtin_vec_lvswxl (a,p); } | ||
2975 | +vbs lsl08(long a, vbs *p) { return __builtin_vec_lvswxl (a,p); } | ||
2976 | +vp lsl09(long a, vp *p) { return __builtin_vec_lvswxl (a,p); } | ||
2977 | +vss lsl10(long a, vss *p) { return __builtin_vec_lvswxl (a,p); } | ||
2978 | +vss lsl11(long a, ss *p) { return __builtin_vec_lvswxl (a,p); } | ||
2979 | +vus lsl12(long a, vus *p) { return __builtin_vec_lvswxl (a,p); } | ||
2980 | +vus lsl13(long a, us *p) { return __builtin_vec_lvswxl (a,p); } | ||
2981 | +vbc lsl14(long a, vbc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2982 | +vsc lsl15(long a, vsc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2983 | +vsc lsl16(long a, sc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2984 | +vuc lsl17(long a, vuc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2985 | +vuc lsl18(long a, uc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2986 | +vsf Dlsl01(long a, vsf *p) { return vec_lvswxl (a,p); } | ||
2987 | +vsf Dlsl02(long a, sf *p) { return vec_lvswxl (a,p); } | ||
2988 | +vbi Dlsl03(long a, vbi *p) { return vec_lvswxl (a,p); } | ||
2989 | +vsi Dlsl04(long a, vsi *p) { return vec_lvswxl (a,p); } | ||
2990 | +vsi Dlsl05(long a, si *p) { return vec_lvswxl (a,p); } | ||
2991 | +vui Dlsl06(long a, vui *p) { return vec_lvswxl (a,p); } | ||
2992 | +vui Dlsl07(long a, ui *p) { return vec_lvswxl (a,p); } | ||
2993 | +vbs Dlsl08(long a, vbs *p) { return vec_lvswxl (a,p); } | ||
2994 | +vp Dlsl09(long a, vp *p) { return vec_lvswxl (a,p); } | ||
2995 | +vss Dlsl10(long a, vss *p) { return vec_lvswxl (a,p); } | ||
2996 | +vss Dlsl11(long a, ss *p) { return vec_lvswxl (a,p); } | ||
2997 | +vus Dlsl12(long a, vus *p) { return vec_lvswxl (a,p); } | ||
2998 | +vus Dlsl13(long a, us *p) { return vec_lvswxl (a,p); } | ||
2999 | +vbc Dlsl14(long a, vbc *p) { return vec_lvswxl (a,p); } | ||
3000 | +vsc Dlsl15(long a, vsc *p) { return vec_lvswxl (a,p); } | ||
3001 | +vsc Dlsl16(long a, sc *p) { return vec_lvswxl (a,p); } | ||
3002 | +vuc Dlsl17(long a, vuc *p) { return vec_lvswxl (a,p); } | ||
3003 | +vuc Dlsl18(long a, uc *p) { return vec_lvswxl (a,p); } | ||
3004 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c | ||
3005 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c 1969-12-31 18:00:00.000000000 -0600 | ||
3006 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c 2012-03-06 12:31:05.156039000 -0600 | ||
3007 | @@ -0,0 +1,36 @@ | ||
3008 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3009 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3010 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3011 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3012 | +/* { dg-final { scan-assembler-times "vabsdub" 7 } } */ | ||
3013 | + | ||
3014 | +#include <altivec.h> | ||
3015 | + | ||
3016 | +typedef __vector signed char vsc; | ||
3017 | +typedef __vector signed short vss; | ||
3018 | +typedef __vector signed int vsi; | ||
3019 | +typedef __vector unsigned char vuc; | ||
3020 | +typedef __vector unsigned short vus; | ||
3021 | +typedef __vector unsigned int vui; | ||
3022 | +typedef __vector bool char vbc; | ||
3023 | +typedef __vector bool short vbs; | ||
3024 | +typedef __vector bool int vbi; | ||
3025 | +typedef __vector float vsf; | ||
3026 | +typedef __vector pixel vp; | ||
3027 | +typedef signed char sc; | ||
3028 | +typedef signed short ss; | ||
3029 | +typedef signed int si; | ||
3030 | +typedef signed long sl; | ||
3031 | +typedef unsigned char uc; | ||
3032 | +typedef unsigned short us; | ||
3033 | +typedef unsigned int ui; | ||
3034 | +typedef unsigned long ul; | ||
3035 | +typedef float sf; | ||
3036 | + | ||
3037 | +vuc fa1b(vuc a, vuc b) { return __builtin_altivec_vabsdub (a,b); } | ||
3038 | +vuc ad1(vuc a, vuc b) { return __builtin_vec_absd (a,b); } | ||
3039 | +vuc ad2(vbc a, vuc b) { return __builtin_vec_absd (a,b); } | ||
3040 | +vuc ad3(vuc a, vbc b) { return __builtin_vec_absd (a,b); } | ||
3041 | +vuc Dad1(vuc a, vuc b) { return vec_absd (a,b); } | ||
3042 | +vuc Dad2(vbc a, vuc b) { return vec_absd (a,b); } | ||
3043 | +vuc Dad3(vuc a, vbc b) { return vec_absd (a,b); } | ||
3044 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c | ||
3045 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c 1969-12-31 18:00:00.000000000 -0600 | ||
3046 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c 2012-03-06 12:31:05.156039000 -0600 | ||
3047 | @@ -0,0 +1,66 @@ | ||
3048 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3049 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3050 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3051 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3052 | +/* { dg-final { scan-assembler-times "stvswx" 37 } } */ | ||
3053 | + | ||
3054 | +#include <altivec.h> | ||
3055 | + | ||
3056 | +typedef __vector signed char vsc; | ||
3057 | +typedef __vector signed short vss; | ||
3058 | +typedef __vector signed int vsi; | ||
3059 | +typedef __vector unsigned char vuc; | ||
3060 | +typedef __vector unsigned short vus; | ||
3061 | +typedef __vector unsigned int vui; | ||
3062 | +typedef __vector bool char vbc; | ||
3063 | +typedef __vector bool short vbs; | ||
3064 | +typedef __vector bool int vbi; | ||
3065 | +typedef __vector float vsf; | ||
3066 | +typedef __vector pixel vp; | ||
3067 | +typedef signed char sc; | ||
3068 | +typedef signed short ss; | ||
3069 | +typedef signed int si; | ||
3070 | +typedef signed long sl; | ||
3071 | +typedef unsigned char uc; | ||
3072 | +typedef unsigned short us; | ||
3073 | +typedef unsigned int ui; | ||
3074 | +typedef unsigned long ul; | ||
3075 | +typedef float sf; | ||
3076 | + | ||
3077 | +void ss1(vsc v, long a, vsc *p) { __builtin_altivec_stvswx (v,a,p); } | ||
3078 | +void ssx01(vsf v, long a, vsf *p) { __builtin_vec_stvswx (v,a,p); } | ||
3079 | +void ssx02(vsf v, long a, sf *p) { __builtin_vec_stvswx (v,a,p); } | ||
3080 | +void ssx03(vbi v, long a, vbi *p) { __builtin_vec_stvswx (v,a,p); } | ||
3081 | +void ssx04(vsi v, long a, vsi *p) { __builtin_vec_stvswx (v,a,p); } | ||
3082 | +void ssx05(vsi v, long a, si *p) { __builtin_vec_stvswx (v,a,p); } | ||
3083 | +void ssx06(vui v, long a, vui *p) { __builtin_vec_stvswx (v,a,p); } | ||
3084 | +void ssx07(vui v, long a, ui *p) { __builtin_vec_stvswx (v,a,p); } | ||
3085 | +void ssx08(vbs v, long a, vbs *p) { __builtin_vec_stvswx (v,a,p); } | ||
3086 | +void ssx09(vp v, long a, vp *p) { __builtin_vec_stvswx (v,a,p); } | ||
3087 | +void ssx10(vss v, long a, vss *p) { __builtin_vec_stvswx (v,a,p); } | ||
3088 | +void ssx11(vss v, long a, ss *p) { __builtin_vec_stvswx (v,a,p); } | ||
3089 | +void ssx12(vus v, long a, vus *p) { __builtin_vec_stvswx (v,a,p); } | ||
3090 | +void ssx13(vus v, long a, us *p) { __builtin_vec_stvswx (v,a,p); } | ||
3091 | +void ssx14(vbc v, long a, vbc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3092 | +void ssx15(vsc v, long a, vsc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3093 | +void ssx16(vsc v, long a, sc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3094 | +void ssx17(vuc v, long a, vuc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3095 | +void ssx18(vuc v, long a, uc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3096 | +void Dssx01(vsf v, long a, vsf *p) { vec_stvswx (v,a,p); } | ||
3097 | +void Dssx02(vsf v, long a, sf *p) { vec_stvswx (v,a,p); } | ||
3098 | +void Dssx03(vbi v, long a, vbi *p) { vec_stvswx (v,a,p); } | ||
3099 | +void Dssx04(vsi v, long a, vsi *p) { vec_stvswx (v,a,p); } | ||
3100 | +void Dssx05(vsi v, long a, si *p) { vec_stvswx (v,a,p); } | ||
3101 | +void Dssx06(vui v, long a, vui *p) { vec_stvswx (v,a,p); } | ||
3102 | +void Dssx07(vui v, long a, ui *p) { vec_stvswx (v,a,p); } | ||
3103 | +void Dssx08(vbs v, long a, vbs *p) { vec_stvswx (v,a,p); } | ||
3104 | +void Dssx09(vp v, long a, vp *p) { vec_stvswx (v,a,p); } | ||
3105 | +void Dssx10(vss v, long a, vss *p) { vec_stvswx (v,a,p); } | ||
3106 | +void Dssx11(vss v, long a, ss *p) { vec_stvswx (v,a,p); } | ||
3107 | +void Dssx12(vus v, long a, vus *p) { vec_stvswx (v,a,p); } | ||
3108 | +void Dssx13(vus v, long a, us *p) { vec_stvswx (v,a,p); } | ||
3109 | +void Dssx14(vbc v, long a, vbc *p) { vec_stvswx (v,a,p); } | ||
3110 | +void Dssx15(vsc v, long a, vsc *p) { vec_stvswx (v,a,p); } | ||
3111 | +void Dssx16(vsc v, long a, sc *p) { vec_stvswx (v,a,p); } | ||
3112 | +void Dssx17(vuc v, long a, vuc *p) { vec_stvswx (v,a,p); } | ||
3113 | +void Dssx18(vuc v, long a, uc *p) { vec_stvswx (v,a,p); } | ||
3114 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c | ||
3115 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c 1969-12-31 18:00:00.000000000 -0600 | ||
3116 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c 2012-03-06 12:31:05.156039000 -0600 | ||
3117 | @@ -0,0 +1,66 @@ | ||
3118 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3119 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3120 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3121 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3122 | +/* { dg-final { scan-assembler-times "stvswxl" 37 } } */ | ||
3123 | + | ||
3124 | +#include <altivec.h> | ||
3125 | + | ||
3126 | +typedef __vector signed char vsc; | ||
3127 | +typedef __vector signed short vss; | ||
3128 | +typedef __vector signed int vsi; | ||
3129 | +typedef __vector unsigned char vuc; | ||
3130 | +typedef __vector unsigned short vus; | ||
3131 | +typedef __vector unsigned int vui; | ||
3132 | +typedef __vector bool char vbc; | ||
3133 | +typedef __vector bool short vbs; | ||
3134 | +typedef __vector bool int vbi; | ||
3135 | +typedef __vector float vsf; | ||
3136 | +typedef __vector pixel vp; | ||
3137 | +typedef signed char sc; | ||
3138 | +typedef signed short ss; | ||
3139 | +typedef signed int si; | ||
3140 | +typedef signed long sl; | ||
3141 | +typedef unsigned char uc; | ||
3142 | +typedef unsigned short us; | ||
3143 | +typedef unsigned int ui; | ||
3144 | +typedef unsigned long ul; | ||
3145 | +typedef float sf; | ||
3146 | + | ||
3147 | +void ss2l(vsc v, long a, vsc *p) { __builtin_altivec_stvswxl (v,a,p); } | ||
3148 | +void ssxl01(vsf v, long a, vsf *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3149 | +void ssxl02(vsf v, long a, sf *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3150 | +void ssxl03(vbi v, long a, vbi *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3151 | +void ssxl04(vsi v, long a, vsi *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3152 | +void ssxl05(vsi v, long a, si *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3153 | +void ssxl06(vui v, long a, vui *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3154 | +void ssxl07(vui v, long a, ui *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3155 | +void ssxl08(vbs v, long a, vbs *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3156 | +void ssxl09(vp v, long a, vp *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3157 | +void ssxl10(vss v, long a, vss *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3158 | +void ssxl11(vss v, long a, ss *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3159 | +void ssxl12(vus v, long a, vus *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3160 | +void ssxl13(vus v, long a, us *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3161 | +void ssxl14(vbc v, long a, vbc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3162 | +void ssxl15(vsc v, long a, vsc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3163 | +void ssxl16(vsc v, long a, sc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3164 | +void ssxl17(vuc v, long a, vuc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3165 | +void ssxl18(vuc v, long a, uc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3166 | +void Dssxl01(vsf v, long a, vsf *p) { vec_stvswxl (v,a,p); } | ||
3167 | +void Dssxl02(vsf v, long a, sf *p) { vec_stvswxl (v,a,p); } | ||
3168 | +void Dssxl03(vbi v, long a, vbi *p) { vec_stvswxl (v,a,p); } | ||
3169 | +void Dssxl04(vsi v, long a, vsi *p) { vec_stvswxl (v,a,p); } | ||
3170 | +void Dssxl05(vsi v, long a, si *p) { vec_stvswxl (v,a,p); } | ||
3171 | +void Dssxl06(vui v, long a, vui *p) { vec_stvswxl (v,a,p); } | ||
3172 | +void Dssxl07(vui v, long a, ui *p) { vec_stvswxl (v,a,p); } | ||
3173 | +void Dssxl08(vbs v, long a, vbs *p) { vec_stvswxl (v,a,p); } | ||
3174 | +void Dssxl09(vp v, long a, vp *p) { vec_stvswxl (v,a,p); } | ||
3175 | +void Dssxl10(vss v, long a, vss *p) { vec_stvswxl (v,a,p); } | ||
3176 | +void Dssxl11(vss v, long a, ss *p) { vec_stvswxl (v,a,p); } | ||
3177 | +void Dssxl12(vus v, long a, vus *p) { vec_stvswxl (v,a,p); } | ||
3178 | +void Dssxl13(vus v, long a, us *p) { vec_stvswxl (v,a,p); } | ||
3179 | +void Dssxl14(vbc v, long a, vbc *p) { vec_stvswxl (v,a,p); } | ||
3180 | +void Dssxl15(vsc v, long a, vsc *p) { vec_stvswxl (v,a,p); } | ||
3181 | +void Dssxl16(vsc v, long a, sc *p) { vec_stvswxl (v,a,p); } | ||
3182 | +void Dssxl17(vuc v, long a, vuc *p) { vec_stvswxl (v,a,p); } | ||
3183 | +void Dssxl18(vuc v, long a, uc *p) { vec_stvswxl (v,a,p); } | ||
3184 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c | ||
3185 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c 1969-12-31 18:00:00.000000000 -0600 | ||
3186 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c 2012-03-06 12:31:05.157039001 -0600 | ||
3187 | @@ -0,0 +1,66 @@ | ||
3188 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3189 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3190 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3191 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3192 | +/* { dg-final { scan-assembler-times "lvsm" 37 } } */ | ||
3193 | + | ||
3194 | +#include <altivec.h> | ||
3195 | + | ||
3196 | +typedef __vector signed char vsc; | ||
3197 | +typedef __vector signed short vss; | ||
3198 | +typedef __vector signed int vsi; | ||
3199 | +typedef __vector unsigned char vuc; | ||
3200 | +typedef __vector unsigned short vus; | ||
3201 | +typedef __vector unsigned int vui; | ||
3202 | +typedef __vector bool char vbc; | ||
3203 | +typedef __vector bool short vbs; | ||
3204 | +typedef __vector bool int vbi; | ||
3205 | +typedef __vector float vsf; | ||
3206 | +typedef __vector pixel vp; | ||
3207 | +typedef signed char sc; | ||
3208 | +typedef signed short ss; | ||
3209 | +typedef signed int si; | ||
3210 | +typedef signed long sl; | ||
3211 | +typedef unsigned char uc; | ||
3212 | +typedef unsigned short us; | ||
3213 | +typedef unsigned int ui; | ||
3214 | +typedef unsigned long ul; | ||
3215 | +typedef float sf; | ||
3216 | + | ||
3217 | +vsc lsm(long a, void *p) { return __builtin_altivec_lvsm (a,p); } | ||
3218 | +vsf lm01(long a, vsf *p) { return __builtin_vec_lvsm (a,p); } | ||
3219 | +vsf lm02(long a, sf *p) { return __builtin_vec_lvsm (a,p); } | ||
3220 | +vbi lm03(long a, vbi *p) { return __builtin_vec_lvsm (a,p); } | ||
3221 | +vsi lm04(long a, vsi *p) { return __builtin_vec_lvsm (a,p); } | ||
3222 | +vsi lm05(long a, si *p) { return __builtin_vec_lvsm (a,p); } | ||
3223 | +vui lm06(long a, vui *p) { return __builtin_vec_lvsm (a,p); } | ||
3224 | +vui lm07(long a, ui *p) { return __builtin_vec_lvsm (a,p); } | ||
3225 | +vbs lm08(long a, vbs *p) { return __builtin_vec_lvsm (a,p); } | ||
3226 | +vp lm09(long a, vp *p) { return __builtin_vec_lvsm (a,p); } | ||
3227 | +vss lm10(long a, vss *p) { return __builtin_vec_lvsm (a,p); } | ||
3228 | +vss lm11(long a, ss *p) { return __builtin_vec_lvsm (a,p); } | ||
3229 | +vus lm12(long a, vus *p) { return __builtin_vec_lvsm (a,p); } | ||
3230 | +vus lm13(long a, us *p) { return __builtin_vec_lvsm (a,p); } | ||
3231 | +vbc lm14(long a, vbc *p) { return __builtin_vec_lvsm (a,p); } | ||
3232 | +vsc lm15(long a, vsc *p) { return __builtin_vec_lvsm (a,p); } | ||
3233 | +vsc lm16(long a, sc *p) { return __builtin_vec_lvsm (a,p); } | ||
3234 | +vuc lm17(long a, vuc *p) { return __builtin_vec_lvsm (a,p); } | ||
3235 | +vuc lm18(long a, uc *p) { return __builtin_vec_lvsm (a,p); } | ||
3236 | +vsf Dlm01(long a, vsf *p) { return vec_lvsm (a,p); } | ||
3237 | +vsf Dlm02(long a, sf *p) { return vec_lvsm (a,p); } | ||
3238 | +vbi Dlm03(long a, vbi *p) { return vec_lvsm (a,p); } | ||
3239 | +vsi Dlm04(long a, vsi *p) { return vec_lvsm (a,p); } | ||
3240 | +vsi Dlm05(long a, si *p) { return vec_lvsm (a,p); } | ||
3241 | +vui Dlm06(long a, vui *p) { return vec_lvsm (a,p); } | ||
3242 | +vui Dlm07(long a, ui *p) { return vec_lvsm (a,p); } | ||
3243 | +vbs Dlm08(long a, vbs *p) { return vec_lvsm (a,p); } | ||
3244 | +vp Dlm09(long a, vp *p) { return vec_lvsm (a,p); } | ||
3245 | +vss Dlm10(long a, vss *p) { return vec_lvsm (a,p); } | ||
3246 | +vss Dlm11(long a, ss *p) { return vec_lvsm (a,p); } | ||
3247 | +vus Dlm12(long a, vus *p) { return vec_lvsm (a,p); } | ||
3248 | +vus Dlm13(long a, us *p) { return vec_lvsm (a,p); } | ||
3249 | +vbc Dlm14(long a, vbc *p) { return vec_lvsm (a,p); } | ||
3250 | +vsc Dlm15(long a, vsc *p) { return vec_lvsm (a,p); } | ||
3251 | +vsc Dlm16(long a, sc *p) { return vec_lvsm (a,p); } | ||
3252 | +vuc Dlm17(long a, vuc *p) { return vec_lvsm (a,p); } | ||
3253 | +vuc Dlm18(long a, uc *p) { return vec_lvsm (a,p); } | ||
3254 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c | ||
3255 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c 1969-12-31 18:00:00.000000000 -0600 | ||
3256 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c 2012-03-06 12:31:05.157039001 -0600 | ||
3257 | @@ -0,0 +1,36 @@ | ||
3258 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3259 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3260 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3261 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3262 | +/* { dg-final { scan-assembler-times "vabsduh" 7 } } */ | ||
3263 | + | ||
3264 | +#include <altivec.h> | ||
3265 | + | ||
3266 | +typedef __vector signed char vsc; | ||
3267 | +typedef __vector signed short vss; | ||
3268 | +typedef __vector signed int vsi; | ||
3269 | +typedef __vector unsigned char vuc; | ||
3270 | +typedef __vector unsigned short vus; | ||
3271 | +typedef __vector unsigned int vui; | ||
3272 | +typedef __vector bool char vbc; | ||
3273 | +typedef __vector bool short vbs; | ||
3274 | +typedef __vector bool int vbi; | ||
3275 | +typedef __vector float vsf; | ||
3276 | +typedef __vector pixel vp; | ||
3277 | +typedef signed char sc; | ||
3278 | +typedef signed short ss; | ||
3279 | +typedef signed int si; | ||
3280 | +typedef signed long sl; | ||
3281 | +typedef unsigned char uc; | ||
3282 | +typedef unsigned short us; | ||
3283 | +typedef unsigned int ui; | ||
3284 | +typedef unsigned long ul; | ||
3285 | +typedef float sf; | ||
3286 | + | ||
3287 | +vus fa2h(vus a, vus b) { return __builtin_altivec_vabsduh (a,b); } | ||
3288 | +vus ad4(vus a, vus b) { return __builtin_vec_absd (a,b); } | ||
3289 | +vus ad5(vbs a, vus b) { return __builtin_vec_absd (a,b); } | ||
3290 | +vus ad6(vus a, vbs b) { return __builtin_vec_absd (a,b); } | ||
3291 | +vus Dad4(vus a, vus b) { return vec_absd (a,b); } | ||
3292 | +vus Dad5(vbs a, vus b) { return vec_absd (a,b); } | ||
3293 | +vus Dad6(vus a, vbs b) { return vec_absd (a,b); } | ||
3294 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c | ||
3295 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c 1969-12-31 18:00:00.000000000 -0600 | ||
3296 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c 2012-03-06 12:31:05.157039001 -0600 | ||
3297 | @@ -0,0 +1,36 @@ | ||
3298 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3299 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3300 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3301 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3302 | +/* { dg-final { scan-assembler-times "vabsduw" 7 } } */ | ||
3303 | + | ||
3304 | +#include <altivec.h> | ||
3305 | + | ||
3306 | +typedef __vector signed char vsc; | ||
3307 | +typedef __vector signed short vss; | ||
3308 | +typedef __vector signed int vsi; | ||
3309 | +typedef __vector unsigned char vuc; | ||
3310 | +typedef __vector unsigned short vus; | ||
3311 | +typedef __vector unsigned int vui; | ||
3312 | +typedef __vector bool char vbc; | ||
3313 | +typedef __vector bool short vbs; | ||
3314 | +typedef __vector bool int vbi; | ||
3315 | +typedef __vector float vsf; | ||
3316 | +typedef __vector pixel vp; | ||
3317 | +typedef signed char sc; | ||
3318 | +typedef signed short ss; | ||
3319 | +typedef signed int si; | ||
3320 | +typedef signed long sl; | ||
3321 | +typedef unsigned char uc; | ||
3322 | +typedef unsigned short us; | ||
3323 | +typedef unsigned int ui; | ||
3324 | +typedef unsigned long ul; | ||
3325 | +typedef float sf; | ||
3326 | + | ||
3327 | +vui fa3w(vui a, vui b) { return __builtin_altivec_vabsduw (a,b); } | ||
3328 | +vui ad7(vui a, vui b) { return __builtin_vec_absd (a,b); } | ||
3329 | +vui ad8(vbi a, vui b) { return __builtin_vec_absd (a,b); } | ||
3330 | +vui ad9(vui a, vbi b) { return __builtin_vec_absd (a,b); } | ||
3331 | +vui Dad7(vui a, vui b) { return vec_absd (a,b); } | ||
3332 | +vui Dad8(vbi a, vui b) { return vec_absd (a,b); } | ||
3333 | +vui Dad9(vui a, vbi b) { return vec_absd (a,b); } | ||
3334 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c | ||
3335 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c 1969-12-31 18:00:00.000000000 -0600 | ||
3336 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c 2012-03-06 12:31:05.158039002 -0600 | ||
3337 | @@ -0,0 +1,34 @@ | ||
3338 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3339 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3340 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3341 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3342 | +/* { dg-final { scan-assembler-times "lvexbx" 5 } } */ | ||
3343 | + | ||
3344 | +#include <altivec.h> | ||
3345 | + | ||
3346 | +typedef __vector signed char vsc; | ||
3347 | +typedef __vector signed short vss; | ||
3348 | +typedef __vector signed int vsi; | ||
3349 | +typedef __vector unsigned char vuc; | ||
3350 | +typedef __vector unsigned short vus; | ||
3351 | +typedef __vector unsigned int vui; | ||
3352 | +typedef __vector bool char vbc; | ||
3353 | +typedef __vector bool short vbs; | ||
3354 | +typedef __vector bool int vbi; | ||
3355 | +typedef __vector float vsf; | ||
3356 | +typedef __vector pixel vp; | ||
3357 | +typedef signed char sc; | ||
3358 | +typedef signed short ss; | ||
3359 | +typedef signed int si; | ||
3360 | +typedef signed long sl; | ||
3361 | +typedef unsigned char uc; | ||
3362 | +typedef unsigned short us; | ||
3363 | +typedef unsigned int ui; | ||
3364 | +typedef unsigned long ul; | ||
3365 | +typedef float sf; | ||
3366 | + | ||
3367 | +vsc le1b(long a, void *p) { return __builtin_altivec_lvexbx (a,p); } | ||
3368 | +vsc leb1(long a, sc *p) { return __builtin_vec_lvexbx (a,p); } | ||
3369 | +vuc leb2(long a, uc *p) { return __builtin_vec_lvexbx (a,p); } | ||
3370 | +vsc Dleb1(long a, sc *p) { return vec_lvexbx (a,p); } | ||
3371 | +vuc Dleb2(long a, uc *p) { return vec_lvexbx (a,p); } | ||
3372 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c | ||
3373 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c 1969-12-31 18:00:00.000000000 -0600 | ||
3374 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c 2012-03-06 12:31:05.158039002 -0600 | ||
3375 | @@ -0,0 +1,34 @@ | ||
3376 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3377 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3378 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3379 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3380 | +/* { dg-final { scan-assembler-times "lvexhx" 5 } } */ | ||
3381 | + | ||
3382 | +#include <altivec.h> | ||
3383 | + | ||
3384 | +typedef __vector signed char vsc; | ||
3385 | +typedef __vector signed short vss; | ||
3386 | +typedef __vector signed int vsi; | ||
3387 | +typedef __vector unsigned char vuc; | ||
3388 | +typedef __vector unsigned short vus; | ||
3389 | +typedef __vector unsigned int vui; | ||
3390 | +typedef __vector bool char vbc; | ||
3391 | +typedef __vector bool short vbs; | ||
3392 | +typedef __vector bool int vbi; | ||
3393 | +typedef __vector float vsf; | ||
3394 | +typedef __vector pixel vp; | ||
3395 | +typedef signed char sc; | ||
3396 | +typedef signed short ss; | ||
3397 | +typedef signed int si; | ||
3398 | +typedef signed long sl; | ||
3399 | +typedef unsigned char uc; | ||
3400 | +typedef unsigned short us; | ||
3401 | +typedef unsigned int ui; | ||
3402 | +typedef unsigned long ul; | ||
3403 | +typedef float sf; | ||
3404 | + | ||
3405 | +vss le2h(long a, void *p) { return __builtin_altivec_lvexhx (a,p); } | ||
3406 | +vss leh1(long a, ss *p) { return __builtin_vec_lvexhx (a,p); } | ||
3407 | +vus leh2(long a, us *p) { return __builtin_vec_lvexhx (a,p); } | ||
3408 | +vss Dleh1(long a, ss *p) { return vec_lvexhx (a,p); } | ||
3409 | +vus Dleh2(long a, us *p) { return vec_lvexhx (a,p); } | ||
3410 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c | ||
3411 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c 1969-12-31 18:00:00.000000000 -0600 | ||
3412 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c 2012-03-06 12:31:05.158039002 -0600 | ||
3413 | @@ -0,0 +1,40 @@ | ||
3414 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3415 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3416 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3417 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3418 | +/* { dg-final { scan-assembler-times "lvexwx" 11 } } */ | ||
3419 | + | ||
3420 | +#include <altivec.h> | ||
3421 | + | ||
3422 | +typedef __vector signed char vsc; | ||
3423 | +typedef __vector signed short vss; | ||
3424 | +typedef __vector signed int vsi; | ||
3425 | +typedef __vector unsigned char vuc; | ||
3426 | +typedef __vector unsigned short vus; | ||
3427 | +typedef __vector unsigned int vui; | ||
3428 | +typedef __vector bool char vbc; | ||
3429 | +typedef __vector bool short vbs; | ||
3430 | +typedef __vector bool int vbi; | ||
3431 | +typedef __vector float vsf; | ||
3432 | +typedef __vector pixel vp; | ||
3433 | +typedef signed char sc; | ||
3434 | +typedef signed short ss; | ||
3435 | +typedef signed int si; | ||
3436 | +typedef signed long sl; | ||
3437 | +typedef unsigned char uc; | ||
3438 | +typedef unsigned short us; | ||
3439 | +typedef unsigned int ui; | ||
3440 | +typedef unsigned long ul; | ||
3441 | +typedef float sf; | ||
3442 | + | ||
3443 | +vsi le3w(long a, void *p) { return __builtin_altivec_lvexwx (a,p); } | ||
3444 | +vsf lew1(long a, sf *p) { return __builtin_vec_lvexwx (a,p); } | ||
3445 | +vsi lew2(long a, si *p) { return __builtin_vec_lvexwx (a,p); } | ||
3446 | +vui lew3(long a, ui *p) { return __builtin_vec_lvexwx (a,p); } | ||
3447 | +vsi lew4(long a, sl *p) { return __builtin_vec_lvexwx (a,p); } | ||
3448 | +vui lew5(long a, ul *p) { return __builtin_vec_lvexwx (a,p); } | ||
3449 | +vsf Dlew1(long a, sf *p) { return vec_lvexwx (a,p); } | ||
3450 | +vsi Dlew2(long a, si *p) { return vec_lvexwx (a,p); } | ||
3451 | +vui Dlew3(long a, ui *p) { return vec_lvexwx (a,p); } | ||
3452 | +vsi Dlew4(long a, sl *p) { return vec_lvexwx (a,p); } | ||
3453 | +vui Dlew5(long a, ul *p) { return vec_lvexwx (a,p); } | ||
3454 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c | ||
3455 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c 1969-12-31 18:00:00.000000000 -0600 | ||
3456 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c 2012-03-06 12:31:05.159039002 -0600 | ||
3457 | @@ -0,0 +1,42 @@ | ||
3458 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3459 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3460 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3461 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3462 | +/* { dg-final { scan-assembler-times "stvexbx" 13 } } */ | ||
3463 | + | ||
3464 | +#include <altivec.h> | ||
3465 | + | ||
3466 | +typedef __vector signed char vsc; | ||
3467 | +typedef __vector signed short vss; | ||
3468 | +typedef __vector signed int vsi; | ||
3469 | +typedef __vector unsigned char vuc; | ||
3470 | +typedef __vector unsigned short vus; | ||
3471 | +typedef __vector unsigned int vui; | ||
3472 | +typedef __vector bool char vbc; | ||
3473 | +typedef __vector bool short vbs; | ||
3474 | +typedef __vector bool int vbi; | ||
3475 | +typedef __vector float vsf; | ||
3476 | +typedef __vector pixel vp; | ||
3477 | +typedef signed char sc; | ||
3478 | +typedef signed short ss; | ||
3479 | +typedef signed int si; | ||
3480 | +typedef signed long sl; | ||
3481 | +typedef unsigned char uc; | ||
3482 | +typedef unsigned short us; | ||
3483 | +typedef unsigned int ui; | ||
3484 | +typedef unsigned long ul; | ||
3485 | +typedef float sf; | ||
3486 | + | ||
3487 | +void se1b(vsc v, long a, vsc *p) { __builtin_altivec_stvexbx (v,a,p); } | ||
3488 | +void seb1(vsc v, long a, sc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3489 | +void seb2(vuc v, long a, uc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3490 | +void seb3(vbc v, long a, sc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3491 | +void seb4(vbc v, long a, uc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3492 | +void seb5(vsc v, long a, void *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3493 | +void seb6(vuc v, long a, void *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3494 | +void Dseb1(vsc v, long a, sc *p) { vec_stvexbx (v,a,p); } | ||
3495 | +void Dseb2(vuc v, long a, uc *p) { vec_stvexbx (v,a,p); } | ||
3496 | +void Dseb3(vbc v, long a, sc *p) { vec_stvexbx (v,a,p); } | ||
3497 | +void Dseb4(vbc v, long a, uc *p) { vec_stvexbx (v,a,p); } | ||
3498 | +void Dseb5(vsc v, long a, void *p) { vec_stvexbx (v,a,p); } | ||
3499 | +void Dseb6(vuc v, long a, void *p) { vec_stvexbx (v,a,p); } | ||
3500 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c | ||
3501 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c 1969-12-31 18:00:00.000000000 -0600 | ||
3502 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c 2012-03-06 12:31:05.159039002 -0600 | ||
3503 | @@ -0,0 +1,42 @@ | ||
3504 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3505 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3506 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3507 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3508 | +/* { dg-final { scan-assembler-times "stvexhx" 13 } } */ | ||
3509 | + | ||
3510 | +#include <altivec.h> | ||
3511 | + | ||
3512 | +typedef __vector signed char vsc; | ||
3513 | +typedef __vector signed short vss; | ||
3514 | +typedef __vector signed int vsi; | ||
3515 | +typedef __vector unsigned char vuc; | ||
3516 | +typedef __vector unsigned short vus; | ||
3517 | +typedef __vector unsigned int vui; | ||
3518 | +typedef __vector bool char vbc; | ||
3519 | +typedef __vector bool short vbs; | ||
3520 | +typedef __vector bool int vbi; | ||
3521 | +typedef __vector float vsf; | ||
3522 | +typedef __vector pixel vp; | ||
3523 | +typedef signed char sc; | ||
3524 | +typedef signed short ss; | ||
3525 | +typedef signed int si; | ||
3526 | +typedef signed long sl; | ||
3527 | +typedef unsigned char uc; | ||
3528 | +typedef unsigned short us; | ||
3529 | +typedef unsigned int ui; | ||
3530 | +typedef unsigned long ul; | ||
3531 | +typedef float sf; | ||
3532 | + | ||
3533 | +void se2h(vss v, long a, vss *p) { __builtin_altivec_stvexhx (v,a,p); } | ||
3534 | +void seh1(vss v, long a, ss *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3535 | +void seh2(vus v, long a, us *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3536 | +void seh3(vbs v, long a, ss *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3537 | +void seh4(vbs v, long a, us *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3538 | +void seh5(vss v, long a, void *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3539 | +void seh6(vus v, long a, void *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3540 | +void Dseh1(vss v, long a, ss *p) { vec_stvexhx (v,a,p); } | ||
3541 | +void Dseh2(vus v, long a, us *p) { vec_stvexhx (v,a,p); } | ||
3542 | +void Dseh3(vbs v, long a, ss *p) { vec_stvexhx (v,a,p); } | ||
3543 | +void Dseh4(vbs v, long a, us *p) { vec_stvexhx (v,a,p); } | ||
3544 | +void Dseh5(vss v, long a, void *p) { vec_stvexhx (v,a,p); } | ||
3545 | +void Dseh6(vus v, long a, void *p) { vec_stvexhx (v,a,p); } | ||
3546 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c | ||
3547 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c 1969-12-31 18:00:00.000000000 -0600 | ||
3548 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c 2012-03-06 12:31:05.159039002 -0600 | ||
3549 | @@ -0,0 +1,46 @@ | ||
3550 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3551 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3552 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3553 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3554 | +/* { dg-final { scan-assembler-times "stvexwx" 17 } } */ | ||
3555 | + | ||
3556 | +#include <altivec.h> | ||
3557 | + | ||
3558 | +typedef __vector signed char vsc; | ||
3559 | +typedef __vector signed short vss; | ||
3560 | +typedef __vector signed int vsi; | ||
3561 | +typedef __vector unsigned char vuc; | ||
3562 | +typedef __vector unsigned short vus; | ||
3563 | +typedef __vector unsigned int vui; | ||
3564 | +typedef __vector bool char vbc; | ||
3565 | +typedef __vector bool short vbs; | ||
3566 | +typedef __vector bool int vbi; | ||
3567 | +typedef __vector float vsf; | ||
3568 | +typedef __vector pixel vp; | ||
3569 | +typedef signed char sc; | ||
3570 | +typedef signed short ss; | ||
3571 | +typedef signed int si; | ||
3572 | +typedef signed long sl; | ||
3573 | +typedef unsigned char uc; | ||
3574 | +typedef unsigned short us; | ||
3575 | +typedef unsigned int ui; | ||
3576 | +typedef unsigned long ul; | ||
3577 | +typedef float sf; | ||
3578 | + | ||
3579 | +void se3w(vsi v, long a, vsi *p) { __builtin_altivec_stvexwx (v,a,p); } | ||
3580 | +void sew1(vsf v, long a, sf *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3581 | +void sew2(vsi v, long a, si *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3582 | +void sew3(vui v, long a, ui *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3583 | +void sew4(vbi v, long a, si *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3584 | +void sew5(vbi v, long a, ui *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3585 | +void sew6(vsf v, long a, void *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3586 | +void sew7(vsi v, long a, void *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3587 | +void sew8(vui v, long a, void *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3588 | +void Dsew1(vsf v, long a, sf *p) { vec_stvexwx (v,a,p); } | ||
3589 | +void Dsew2(vsi v, long a, si *p) { vec_stvexwx (v,a,p); } | ||
3590 | +void Dsew3(vui v, long a, ui *p) { vec_stvexwx (v,a,p); } | ||
3591 | +void Dsew4(vbi v, long a, si *p) { vec_stvexwx (v,a,p); } | ||
3592 | +void Dsew5(vbi v, long a, ui *p) { vec_stvexwx (v,a,p); } | ||
3593 | +void Dsew6(vsf v, long a, void *p) { vec_stvexwx (v,a,p); } | ||
3594 | +void Dsew7(vsi v, long a, void *p) { vec_stvexwx (v,a,p); } | ||
3595 | +void Dsew8(vui v, long a, void *p) { vec_stvexwx (v,a,p); } | ||
3596 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c | ||
3597 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c 1969-12-31 18:00:00.000000000 -0600 | ||
3598 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c 2012-03-06 12:31:15.921038995 -0600 | ||
3599 | @@ -0,0 +1,48 @@ | ||
3600 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3601 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3602 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3603 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3604 | +/* { dg-final { scan-assembler-times "lvlx" 19 } } */ | ||
3605 | + | ||
3606 | +#include <altivec.h> | ||
3607 | + | ||
3608 | +typedef __vector signed char vsc; | ||
3609 | +typedef __vector signed short vss; | ||
3610 | +typedef __vector signed int vsi; | ||
3611 | +typedef __vector unsigned char vuc; | ||
3612 | +typedef __vector unsigned short vus; | ||
3613 | +typedef __vector unsigned int vui; | ||
3614 | +typedef __vector bool char vbc; | ||
3615 | +typedef __vector bool short vbs; | ||
3616 | +typedef __vector bool int vbi; | ||
3617 | +typedef __vector float vsf; | ||
3618 | +typedef __vector pixel vp; | ||
3619 | +typedef signed char sc; | ||
3620 | +typedef signed short ss; | ||
3621 | +typedef signed int si; | ||
3622 | +typedef signed long sl; | ||
3623 | +typedef unsigned char uc; | ||
3624 | +typedef unsigned short us; | ||
3625 | +typedef unsigned int ui; | ||
3626 | +typedef unsigned long ul; | ||
3627 | +typedef float sf; | ||
3628 | + | ||
3629 | +vsc lc1(long a, void *p) { return __builtin_altivec_lvlx (a,p); } | ||
3630 | +vsf llx01(long a, vsf *p) { return __builtin_vec_lvlx (a,p); } | ||
3631 | +vsf llx02(long a, sf *p) { return __builtin_vec_lvlx (a,p); } | ||
3632 | +vbi llx03(long a, vbi *p) { return __builtin_vec_lvlx (a,p); } | ||
3633 | +vsi llx04(long a, vsi *p) { return __builtin_vec_lvlx (a,p); } | ||
3634 | +vsi llx05(long a, si *p) { return __builtin_vec_lvlx (a,p); } | ||
3635 | +vui llx06(long a, vui *p) { return __builtin_vec_lvlx (a,p); } | ||
3636 | +vui llx07(long a, ui *p) { return __builtin_vec_lvlx (a,p); } | ||
3637 | +vbs llx08(long a, vbs *p) { return __builtin_vec_lvlx (a,p); } | ||
3638 | +vp llx09(long a, vp *p) { return __builtin_vec_lvlx (a,p); } | ||
3639 | +vss llx10(long a, vss *p) { return __builtin_vec_lvlx (a,p); } | ||
3640 | +vss llx11(long a, ss *p) { return __builtin_vec_lvlx (a,p); } | ||
3641 | +vus llx12(long a, vus *p) { return __builtin_vec_lvlx (a,p); } | ||
3642 | +vus llx13(long a, us *p) { return __builtin_vec_lvlx (a,p); } | ||
3643 | +vbc llx14(long a, vbc *p) { return __builtin_vec_lvlx (a,p); } | ||
3644 | +vsc llx15(long a, vsc *p) { return __builtin_vec_lvlx (a,p); } | ||
3645 | +vsc llx16(long a, sc *p) { return __builtin_vec_lvlx (a,p); } | ||
3646 | +vuc llx17(long a, vuc *p) { return __builtin_vec_lvlx (a,p); } | ||
3647 | +vuc llx18(long a, uc *p) { return __builtin_vec_lvlx (a,p); } | ||
3648 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c | ||
3649 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c 1969-12-31 18:00:00.000000000 -0600 | ||
3650 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c 2012-03-06 12:31:15.921038995 -0600 | ||
3651 | @@ -0,0 +1,48 @@ | ||
3652 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3653 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3654 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3655 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3656 | +/* { dg-final { scan-assembler-times "lvlxl" 19 } } */ | ||
3657 | + | ||
3658 | +#include <altivec.h> | ||
3659 | + | ||
3660 | +typedef __vector signed char vsc; | ||
3661 | +typedef __vector signed short vss; | ||
3662 | +typedef __vector signed int vsi; | ||
3663 | +typedef __vector unsigned char vuc; | ||
3664 | +typedef __vector unsigned short vus; | ||
3665 | +typedef __vector unsigned int vui; | ||
3666 | +typedef __vector bool char vbc; | ||
3667 | +typedef __vector bool short vbs; | ||
3668 | +typedef __vector bool int vbi; | ||
3669 | +typedef __vector float vsf; | ||
3670 | +typedef __vector pixel vp; | ||
3671 | +typedef signed char sc; | ||
3672 | +typedef signed short ss; | ||
3673 | +typedef signed int si; | ||
3674 | +typedef signed long sl; | ||
3675 | +typedef unsigned char uc; | ||
3676 | +typedef unsigned short us; | ||
3677 | +typedef unsigned int ui; | ||
3678 | +typedef unsigned long ul; | ||
3679 | +typedef float sf; | ||
3680 | + | ||
3681 | +vsc lc2(long a, void *p) { return __builtin_altivec_lvlxl (a,p); } | ||
3682 | +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvlxl (a,p); } | ||
3683 | +vsf llxl02(long a, sf *p) { return __builtin_vec_lvlxl (a,p); } | ||
3684 | +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvlxl (a,p); } | ||
3685 | +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvlxl (a,p); } | ||
3686 | +vsi llxl05(long a, si *p) { return __builtin_vec_lvlxl (a,p); } | ||
3687 | +vui llxl06(long a, vui *p) { return __builtin_vec_lvlxl (a,p); } | ||
3688 | +vui llxl07(long a, ui *p) { return __builtin_vec_lvlxl (a,p); } | ||
3689 | +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvlxl (a,p); } | ||
3690 | +vp llxl09(long a, vp *p) { return __builtin_vec_lvlxl (a,p); } | ||
3691 | +vss llxl10(long a, vss *p) { return __builtin_vec_lvlxl (a,p); } | ||
3692 | +vss llxl11(long a, ss *p) { return __builtin_vec_lvlxl (a,p); } | ||
3693 | +vus llxl12(long a, vus *p) { return __builtin_vec_lvlxl (a,p); } | ||
3694 | +vus llxl13(long a, us *p) { return __builtin_vec_lvlxl (a,p); } | ||
3695 | +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3696 | +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3697 | +vsc llxl16(long a, sc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3698 | +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3699 | +vuc llxl18(long a, uc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3700 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c | ||
3701 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c 1969-12-31 18:00:00.000000000 -0600 | ||
3702 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c 2012-03-06 12:31:15.922038996 -0600 | ||
3703 | @@ -0,0 +1,48 @@ | ||
3704 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3705 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3706 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3707 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3708 | +/* { dg-final { scan-assembler-times "lvrx" 19 } } */ | ||
3709 | + | ||
3710 | +#include <altivec.h> | ||
3711 | + | ||
3712 | +typedef __vector signed char vsc; | ||
3713 | +typedef __vector signed short vss; | ||
3714 | +typedef __vector signed int vsi; | ||
3715 | +typedef __vector unsigned char vuc; | ||
3716 | +typedef __vector unsigned short vus; | ||
3717 | +typedef __vector unsigned int vui; | ||
3718 | +typedef __vector bool char vbc; | ||
3719 | +typedef __vector bool short vbs; | ||
3720 | +typedef __vector bool int vbi; | ||
3721 | +typedef __vector float vsf; | ||
3722 | +typedef __vector pixel vp; | ||
3723 | +typedef signed char sc; | ||
3724 | +typedef signed short ss; | ||
3725 | +typedef signed int si; | ||
3726 | +typedef signed long sl; | ||
3727 | +typedef unsigned char uc; | ||
3728 | +typedef unsigned short us; | ||
3729 | +typedef unsigned int ui; | ||
3730 | +typedef unsigned long ul; | ||
3731 | +typedef float sf; | ||
3732 | + | ||
3733 | +vsc lc3(long a, void *p) { return __builtin_altivec_lvrx (a,p); } | ||
3734 | +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvrx (a,p); } | ||
3735 | +vsf lrx02(long a, sf *p) { return __builtin_vec_lvrx (a,p); } | ||
3736 | +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvrx (a,p); } | ||
3737 | +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvrx (a,p); } | ||
3738 | +vsi lrx05(long a, si *p) { return __builtin_vec_lvrx (a,p); } | ||
3739 | +vui lrx06(long a, vui *p) { return __builtin_vec_lvrx (a,p); } | ||
3740 | +vui lrx07(long a, ui *p) { return __builtin_vec_lvrx (a,p); } | ||
3741 | +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvrx (a,p); } | ||
3742 | +vp lrx09(long a, vp *p) { return __builtin_vec_lvrx (a,p); } | ||
3743 | +vss lrx10(long a, vss *p) { return __builtin_vec_lvrx (a,p); } | ||
3744 | +vss lrx11(long a, ss *p) { return __builtin_vec_lvrx (a,p); } | ||
3745 | +vus lrx12(long a, vus *p) { return __builtin_vec_lvrx (a,p); } | ||
3746 | +vus lrx13(long a, us *p) { return __builtin_vec_lvrx (a,p); } | ||
3747 | +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvrx (a,p); } | ||
3748 | +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvrx (a,p); } | ||
3749 | +vsc lrx16(long a, sc *p) { return __builtin_vec_lvrx (a,p); } | ||
3750 | +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvrx (a,p); } | ||
3751 | +vuc lrx18(long a, uc *p) { return __builtin_vec_lvrx (a,p); } | ||
3752 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c | ||
3753 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c 1969-12-31 18:00:00.000000000 -0600 | ||
3754 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c 2012-03-06 12:31:15.922038996 -0600 | ||
3755 | @@ -0,0 +1,48 @@ | ||
3756 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3757 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3758 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3759 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3760 | +/* { dg-final { scan-assembler-times "lvrxl" 19 } } */ | ||
3761 | + | ||
3762 | +#include <altivec.h> | ||
3763 | + | ||
3764 | +typedef __vector signed char vsc; | ||
3765 | +typedef __vector signed short vss; | ||
3766 | +typedef __vector signed int vsi; | ||
3767 | +typedef __vector unsigned char vuc; | ||
3768 | +typedef __vector unsigned short vus; | ||
3769 | +typedef __vector unsigned int vui; | ||
3770 | +typedef __vector bool char vbc; | ||
3771 | +typedef __vector bool short vbs; | ||
3772 | +typedef __vector bool int vbi; | ||
3773 | +typedef __vector float vsf; | ||
3774 | +typedef __vector pixel vp; | ||
3775 | +typedef signed char sc; | ||
3776 | +typedef signed short ss; | ||
3777 | +typedef signed int si; | ||
3778 | +typedef signed long sl; | ||
3779 | +typedef unsigned char uc; | ||
3780 | +typedef unsigned short us; | ||
3781 | +typedef unsigned int ui; | ||
3782 | +typedef unsigned long ul; | ||
3783 | +typedef float sf; | ||
3784 | + | ||
3785 | +vsc lc4(long a, void *p) { return __builtin_altivec_lvrxl (a,p); } | ||
3786 | +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvrxl (a,p); } | ||
3787 | +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvrxl (a,p); } | ||
3788 | +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvrxl (a,p); } | ||
3789 | +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvrxl (a,p); } | ||
3790 | +vsi lrxl05(long a, si *p) { return __builtin_vec_lvrxl (a,p); } | ||
3791 | +vui lrxl06(long a, vui *p) { return __builtin_vec_lvrxl (a,p); } | ||
3792 | +vui lrxl07(long a, ui *p) { return __builtin_vec_lvrxl (a,p); } | ||
3793 | +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvrxl (a,p); } | ||
3794 | +vp lrxl09(long a, vp *p) { return __builtin_vec_lvrxl (a,p); } | ||
3795 | +vss lrxl10(long a, vss *p) { return __builtin_vec_lvrxl (a,p); } | ||
3796 | +vss lrxl11(long a, ss *p) { return __builtin_vec_lvrxl (a,p); } | ||
3797 | +vus lrxl12(long a, vus *p) { return __builtin_vec_lvrxl (a,p); } | ||
3798 | +vus lrxl13(long a, us *p) { return __builtin_vec_lvrxl (a,p); } | ||
3799 | +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3800 | +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3801 | +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3802 | +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3803 | +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3804 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c | ||
3805 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c 1969-12-31 18:00:00.000000000 -0600 | ||
3806 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c 2012-03-06 12:31:15.922038996 -0600 | ||
3807 | @@ -0,0 +1,48 @@ | ||
3808 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3809 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3810 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3811 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3812 | +/* { dg-final { scan-assembler-times "stvlx" 19 } } */ | ||
3813 | + | ||
3814 | +#include <altivec.h> | ||
3815 | + | ||
3816 | +typedef __vector signed char vsc; | ||
3817 | +typedef __vector signed short vss; | ||
3818 | +typedef __vector signed int vsi; | ||
3819 | +typedef __vector unsigned char vuc; | ||
3820 | +typedef __vector unsigned short vus; | ||
3821 | +typedef __vector unsigned int vui; | ||
3822 | +typedef __vector bool char vbc; | ||
3823 | +typedef __vector bool short vbs; | ||
3824 | +typedef __vector bool int vbi; | ||
3825 | +typedef __vector float vsf; | ||
3826 | +typedef __vector pixel vp; | ||
3827 | +typedef signed char sc; | ||
3828 | +typedef signed short ss; | ||
3829 | +typedef signed int si; | ||
3830 | +typedef signed long sl; | ||
3831 | +typedef unsigned char uc; | ||
3832 | +typedef unsigned short us; | ||
3833 | +typedef unsigned int ui; | ||
3834 | +typedef unsigned long ul; | ||
3835 | +typedef float sf; | ||
3836 | + | ||
3837 | +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvlx (v,a,p); } | ||
3838 | +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvlx (v,a,p); } | ||
3839 | +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvlx (v,a,p); } | ||
3840 | +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvlx (v,a,p); } | ||
3841 | +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvlx (v,a,p); } | ||
3842 | +void slx05(vsi v, long a, si *p) { __builtin_vec_stvlx (v,a,p); } | ||
3843 | +void slx06(vui v, long a, vui *p) { __builtin_vec_stvlx (v,a,p); } | ||
3844 | +void slx07(vui v, long a, ui *p) { __builtin_vec_stvlx (v,a,p); } | ||
3845 | +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvlx (v,a,p); } | ||
3846 | +void slx09(vp v, long a, vp *p) { __builtin_vec_stvlx (v,a,p); } | ||
3847 | +void slx10(vss v, long a, vss *p) { __builtin_vec_stvlx (v,a,p); } | ||
3848 | +void slx11(vss v, long a, ss *p) { __builtin_vec_stvlx (v,a,p); } | ||
3849 | +void slx12(vus v, long a, vus *p) { __builtin_vec_stvlx (v,a,p); } | ||
3850 | +void slx13(vus v, long a, us *p) { __builtin_vec_stvlx (v,a,p); } | ||
3851 | +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3852 | +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3853 | +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3854 | +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3855 | +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3856 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c | ||
3857 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c 1969-12-31 18:00:00.000000000 -0600 | ||
3858 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c 2012-03-06 12:31:15.923039000 -0600 | ||
3859 | @@ -0,0 +1,48 @@ | ||
3860 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3861 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3862 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3863 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3864 | +/* { dg-final { scan-assembler-times "stvlxl" 19 } } */ | ||
3865 | + | ||
3866 | +#include <altivec.h> | ||
3867 | + | ||
3868 | +typedef __vector signed char vsc; | ||
3869 | +typedef __vector signed short vss; | ||
3870 | +typedef __vector signed int vsi; | ||
3871 | +typedef __vector unsigned char vuc; | ||
3872 | +typedef __vector unsigned short vus; | ||
3873 | +typedef __vector unsigned int vui; | ||
3874 | +typedef __vector bool char vbc; | ||
3875 | +typedef __vector bool short vbs; | ||
3876 | +typedef __vector bool int vbi; | ||
3877 | +typedef __vector float vsf; | ||
3878 | +typedef __vector pixel vp; | ||
3879 | +typedef signed char sc; | ||
3880 | +typedef signed short ss; | ||
3881 | +typedef signed int si; | ||
3882 | +typedef signed long sl; | ||
3883 | +typedef unsigned char uc; | ||
3884 | +typedef unsigned short us; | ||
3885 | +typedef unsigned int ui; | ||
3886 | +typedef unsigned long ul; | ||
3887 | +typedef float sf; | ||
3888 | + | ||
3889 | +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvlxl (v,a,p); } | ||
3890 | +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3891 | +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3892 | +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3893 | +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3894 | +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3895 | +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3896 | +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3897 | +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3898 | +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3899 | +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3900 | +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3901 | +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3902 | +void slxl13(vus v, long a, us *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3903 | +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3904 | +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3905 | +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3906 | +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3907 | +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3908 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c | ||
3909 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c 1969-12-31 18:00:00.000000000 -0600 | ||
3910 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c 2012-03-06 12:31:15.923039000 -0600 | ||
3911 | @@ -0,0 +1,48 @@ | ||
3912 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3913 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3914 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3915 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3916 | +/* { dg-final { scan-assembler-times "stvrx" 19 } } */ | ||
3917 | + | ||
3918 | +#include <altivec.h> | ||
3919 | + | ||
3920 | +typedef __vector signed char vsc; | ||
3921 | +typedef __vector signed short vss; | ||
3922 | +typedef __vector signed int vsi; | ||
3923 | +typedef __vector unsigned char vuc; | ||
3924 | +typedef __vector unsigned short vus; | ||
3925 | +typedef __vector unsigned int vui; | ||
3926 | +typedef __vector bool char vbc; | ||
3927 | +typedef __vector bool short vbs; | ||
3928 | +typedef __vector bool int vbi; | ||
3929 | +typedef __vector float vsf; | ||
3930 | +typedef __vector pixel vp; | ||
3931 | +typedef signed char sc; | ||
3932 | +typedef signed short ss; | ||
3933 | +typedef signed int si; | ||
3934 | +typedef signed long sl; | ||
3935 | +typedef unsigned char uc; | ||
3936 | +typedef unsigned short us; | ||
3937 | +typedef unsigned int ui; | ||
3938 | +typedef unsigned long ul; | ||
3939 | +typedef float sf; | ||
3940 | + | ||
3941 | +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvrx (v,a,p); } | ||
3942 | +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvrx (v,a,p); } | ||
3943 | +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvrx (v,a,p); } | ||
3944 | +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvrx (v,a,p); } | ||
3945 | +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvrx (v,a,p); } | ||
3946 | +void srx05(vsi v, long a, si *p) { __builtin_vec_stvrx (v,a,p); } | ||
3947 | +void srx06(vui v, long a, vui *p) { __builtin_vec_stvrx (v,a,p); } | ||
3948 | +void srx07(vui v, long a, ui *p) { __builtin_vec_stvrx (v,a,p); } | ||
3949 | +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvrx (v,a,p); } | ||
3950 | +void srx09(vp v, long a, vp *p) { __builtin_vec_stvrx (v,a,p); } | ||
3951 | +void srx10(vss v, long a, vss *p) { __builtin_vec_stvrx (v,a,p); } | ||
3952 | +void srx11(vss v, long a, ss *p) { __builtin_vec_stvrx (v,a,p); } | ||
3953 | +void srx12(vus v, long a, vus *p) { __builtin_vec_stvrx (v,a,p); } | ||
3954 | +void srx13(vus v, long a, us *p) { __builtin_vec_stvrx (v,a,p); } | ||
3955 | +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3956 | +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3957 | +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3958 | +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3959 | +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3960 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c | ||
3961 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c 1969-12-31 18:00:00.000000000 -0600 | ||
3962 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c 2012-03-06 12:31:15.923039000 -0600 | ||
3963 | @@ -0,0 +1,48 @@ | ||
3964 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3965 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3966 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3967 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3968 | +/* { dg-final { scan-assembler-times "stvrxl" 19 } } */ | ||
3969 | + | ||
3970 | +#include <altivec.h> | ||
3971 | + | ||
3972 | +typedef __vector signed char vsc; | ||
3973 | +typedef __vector signed short vss; | ||
3974 | +typedef __vector signed int vsi; | ||
3975 | +typedef __vector unsigned char vuc; | ||
3976 | +typedef __vector unsigned short vus; | ||
3977 | +typedef __vector unsigned int vui; | ||
3978 | +typedef __vector bool char vbc; | ||
3979 | +typedef __vector bool short vbs; | ||
3980 | +typedef __vector bool int vbi; | ||
3981 | +typedef __vector float vsf; | ||
3982 | +typedef __vector pixel vp; | ||
3983 | +typedef signed char sc; | ||
3984 | +typedef signed short ss; | ||
3985 | +typedef signed int si; | ||
3986 | +typedef signed long sl; | ||
3987 | +typedef unsigned char uc; | ||
3988 | +typedef unsigned short us; | ||
3989 | +typedef unsigned int ui; | ||
3990 | +typedef unsigned long ul; | ||
3991 | +typedef float sf; | ||
3992 | + | ||
3993 | +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvrxl (v,a,p); } | ||
3994 | +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvrxl (v,a,p); } | ||
3995 | +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvrxl (v,a,p); } | ||
3996 | +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvrxl (v,a,p); } | ||
3997 | +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvrxl (v,a,p); } | ||
3998 | +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvrxl (v,a,p); } | ||
3999 | +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4000 | +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4001 | +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4002 | +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4003 | +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4004 | +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4005 | +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4006 | +void srxl13(vus v, long a, us *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4007 | +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4008 | +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4009 | +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4010 | +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4011 | +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
diff --git a/recipes-devtools/gcc/files/gcc.experimental_move.patch b/recipes-devtools/gcc/files/gcc.experimental_move.patch new file mode 100644 index 0000000..b9642ed --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.experimental_move.patch | |||
@@ -0,0 +1,32 @@ | |||
1 | diff -ruN gcc-4.4.0/gcc/config/rs6000/rs6000.c gcc-4.4.0-e500mc64/gcc/config/rs6000/rs6000.c | ||
2 | --- gcc-4.4.0/gcc/config/rs6000/rs6000.c 2009-03-17 15:18:21.000000000 -0500 | ||
3 | +++ gcc-4.4.0-e500mc64/gcc/config/rs6000/rs6000.c 2009-12-04 10:36:44.000000000 -0600 | ||
4 | @@ -11032,6 +11059,14 @@ | ||
5 | mode = SImode; | ||
6 | gen_func.mov = gen_movsi; | ||
7 | } | ||
8 | + else if (TARGET_COPY_UNALIGNED && bytes == 3 && offset > 0) | ||
9 | + { | ||
10 | + /* We generate a single unaligned SI move instead of 2 (HI, QI) */ | ||
11 | + move_bytes = 3; | ||
12 | + mode = SImode; | ||
13 | + gen_func.mov = gen_movsi; | ||
14 | + offset--; | ||
15 | + } | ||
16 | else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) | ||
17 | { /* move 2 bytes */ | ||
18 | move_bytes = 2; | ||
19 | diff -ruN gcc-4.4.0/gcc/config/rs6000/rs6000.opt gcc-4.4.0-e500mc64/gcc/config/rs6000/rs6000.opt | ||
20 | --- gcc-4.4.0/gcc/config/rs6000/rs6000.opt 2009-02-20 09:20:38.000000000 -0600 | ||
21 | +++ gcc-4.4.0-e500mc64/gcc/config/rs6000/rs6000.opt 2009-09-30 13:51:17.000000000 -0500 | ||
22 | @@ -201,6 +201,10 @@ | ||
23 | Target RejectNegative Joined | ||
24 | -misel=yes/no Deprecated option. Use -misel/-mno-isel instead | ||
25 | |||
26 | +mcopy-unaligned | ||
27 | +Target Report Var(TARGET_COPY_UNALIGNED) | ||
28 | +Generate unaligned word load and stores to move 3 bytes | ||
29 | + | ||
30 | mspe | ||
31 | Target | ||
32 | Generate SPE SIMD instructions on E500 | ||
diff --git a/recipes-devtools/gcc/files/gcc.extelim-v3.patch b/recipes-devtools/gcc/files/gcc.extelim-v3.patch new file mode 100644 index 0000000..e124b18 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.extelim-v3.patch | |||
@@ -0,0 +1,3491 @@ | |||
1 | Eliminate sign and zero extensions in PPC generated code | ||
2 | A new module is introduced 'extelim.c' and a new RTL pass is introduced. | ||
3 | The '-f[no-]extelim' flag controls this pass and is enabled at -O2 and above. | ||
4 | The algorithm is based on the paper "Effective Sign Extension Elimination", Kawahito, et. al. | ||
5 | More details on implementation in the extelim.c module. | ||
6 | |||
7 | --- gcc-4.6-branch-clean/gcc/opts.c 2011-07-27 12:02:02.483850879 -0500 | ||
8 | +++ gcc-4.6-branch/gcc/opts.c 2011-07-25 17:59:00.911975444 -0500 | ||
9 | @@ -492,6 +492,7 @@ | ||
10 | { OPT_LEVELS_2_PLUS, OPT_falign_jumps, NULL, 1 }, | ||
11 | { OPT_LEVELS_2_PLUS, OPT_falign_labels, NULL, 1 }, | ||
12 | { OPT_LEVELS_2_PLUS, OPT_falign_functions, NULL, 1 }, | ||
13 | + { OPT_LEVELS_2_PLUS, OPT_fextelim, NULL, 1 }, | ||
14 | |||
15 | /* -O3 optimizations. */ | ||
16 | { OPT_LEVELS_3_PLUS, OPT_ftree_loop_distribute_patterns, NULL, 1 }, | ||
17 | --- gcc-4.6-branch-clean/gcc/tree-pass.h 2011-07-27 12:02:02.485981448 -0500 | ||
18 | +++ gcc-4.6-branch/gcc/tree-pass.h 2011-07-25 17:59:00.912976334 -0500 | ||
19 | @@ -483,6 +483,7 @@ | ||
20 | extern struct rtl_opt_pass pass_initial_value_sets; | ||
21 | extern struct rtl_opt_pass pass_unshare_all_rtl; | ||
22 | extern struct rtl_opt_pass pass_instantiate_virtual_regs; | ||
23 | +extern struct rtl_opt_pass pass_rtl_extelim; | ||
24 | extern struct rtl_opt_pass pass_rtl_fwprop; | ||
25 | extern struct rtl_opt_pass pass_rtl_fwprop_addr; | ||
26 | extern struct rtl_opt_pass pass_jump2; | ||
27 | --- gcc-4.6-branch-clean/gcc/timevar.def 2011-07-27 12:02:02.487999008 -0500 | ||
28 | +++ gcc-4.6-branch/gcc/timevar.def 2011-07-25 17:59:00.913979563 -0500 | ||
29 | @@ -180,6 +180,7 @@ | ||
30 | DEFTIMEVAR (TV_VARCONST , "varconst") | ||
31 | DEFTIMEVAR (TV_LOWER_SUBREG , "lower subreg") | ||
32 | DEFTIMEVAR (TV_JUMP , "jump") | ||
33 | +DEFTIMEVAR (TV_EXTELIM , "extension elimination") | ||
34 | DEFTIMEVAR (TV_FWPROP , "forward prop") | ||
35 | DEFTIMEVAR (TV_CSE , "CSE") | ||
36 | DEFTIMEVAR (TV_DCE , "dead code elimination") | ||
37 | --- gcc-4.6-branch-clean/gcc/common.opt 2011-07-27 12:02:02.490978128 -0500 | ||
38 | +++ gcc-4.6-branch/gcc/common.opt 2011-07-25 17:59:00.915979093 -0500 | ||
39 | @@ -996,6 +996,10 @@ | ||
40 | Common Report Var(flag_eliminate_dwarf2_dups) | ||
41 | Perform DWARF2 duplicate elimination | ||
42 | |||
43 | +fextelim | ||
44 | +Common Report Var(flag_extelim) | ||
45 | +Perform zero/sign extension removal | ||
46 | + | ||
47 | fipa-sra | ||
48 | Common Report Var(flag_ipa_sra) Init(0) Optimization | ||
49 | Perform interprocedural reduction of aggregates | ||
50 | --- gcc-4.6-branch-clean/gcc/Makefile.in 2011-07-27 12:02:02.498976606 -0500 | ||
51 | +++ gcc-4.6-branch/gcc/Makefile.in 2011-07-25 17:59:00.919975303 -0500 | ||
52 | @@ -1233,6 +1233,7 @@ | ||
53 | explow.o \ | ||
54 | expmed.o \ | ||
55 | expr.o \ | ||
56 | + extelim.o \ | ||
57 | final.o \ | ||
58 | fixed-value.o \ | ||
59 | fold-const.o \ | ||
60 | @@ -2891,6 +2892,11 @@ | ||
61 | reload.h langhooks.h intl.h $(TM_P_H) $(TARGET_H) \ | ||
62 | tree-iterator.h gt-expr.h $(MACHMODE_H) $(TIMEVAR_H) $(TREE_FLOW_H) \ | ||
63 | $(TREE_PASS_H) $(DF_H) $(DIAGNOSTIC_H) vecprim.h $(SSAEXPAND_H) | ||
64 | +extelim.o : extelim.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ | ||
65 | + $(TREE_H) $(TM_P_H) $(FLAGS_H) $(REGS_H) hard-reg-set.h $(BASIC_BLOCK_H) \ | ||
66 | + insn-config.h $(FUNCTION_H) $(EXPR_H) $(INSN_ATTR_H) $(RECOG_H) \ | ||
67 | + toplev.h $(TARGET_H) $(TIMEVAR_H) $(OPTABS_H) insn-codes.h \ | ||
68 | + output.h $(PARAMS_H) $(TREE_PASS_H) $(CGRAPH_H) | ||
69 | dojump.o : dojump.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(TREE_H) \ | ||
70 | $(FLAGS_H) $(FUNCTION_H) $(EXPR_H) $(OPTABS_H) $(INSN_ATTR_H) insn-config.h \ | ||
71 | langhooks.h $(GGC_H) gt-dojump.h vecprim.h $(BASIC_BLOCK_H) output.h | ||
72 | --- gcc-4.6-branch-clean/gcc/passes.c 2011-07-27 12:02:02.502976386 -0500 | ||
73 | +++ gcc-4.6-branch/gcc/passes.c 2011-07-25 17:59:00.922975752 -0500 | ||
74 | @@ -990,6 +990,7 @@ | ||
75 | NEXT_PASS (pass_web); | ||
76 | NEXT_PASS (pass_rtl_cprop); | ||
77 | NEXT_PASS (pass_cse2); | ||
78 | + NEXT_PASS (pass_rtl_extelim); | ||
79 | NEXT_PASS (pass_rtl_dse1); | ||
80 | NEXT_PASS (pass_rtl_fwprop_addr); | ||
81 | NEXT_PASS (pass_inc_dec); | ||
82 | --- gcc-4.6.1-clean/gcc/extelim.c 1969-12-31 18:00:00.000000000 -0600 | ||
83 | +++ gcc-4.6.1/gcc/extelim.c 2011-11-14 15:43:10.041143996 -0600 | ||
84 | @@ -0,0 +1,3407 @@ | ||
85 | +/* Redundant extension elimination | ||
86 | + Copyright (C) 2010 Free Software Foundation, Inc. | ||
87 | + Contributed by John Russo (john.russo@freescale.com) | ||
88 | + | ||
89 | +This file is part of GCC. | ||
90 | + | ||
91 | +GCC is free software; you can redistribute it and/or modify it under | ||
92 | +the terms of the GNU General Public License as published by the Free | ||
93 | +Software Foundation; either version 3, or (at your option) any later | ||
94 | +version. | ||
95 | + | ||
96 | +GCC is distributed in the hope that it will be useful, but WITHOUT ANY | ||
97 | +WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
98 | +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
99 | +for more details. | ||
100 | + | ||
101 | +You should have received a copy of the GNU General Public License | ||
102 | +along with GCC; see the file COPYING3. If not see | ||
103 | +<http://www.gnu.org/licenses/>. */ | ||
104 | + | ||
105 | +/* | ||
106 | +PURPOSE: Implement a method for eliminating redundant and superflous sign | ||
107 | +extension instructions from 64-bit PPC e5500 generated code. | ||
108 | + | ||
109 | +MOTIVATING EXAMPLE: | ||
110 | +The Nullstone loop_6.c kernel looks like: | ||
111 | + int i; | ||
112 | + int a[100]; | ||
113 | + | ||
114 | + ref_int_p (&a[0]); | ||
115 | + | ||
116 | + for (i=2; i<100; i++) | ||
117 | + a[i] = a[i-1] + a[i-2]; | ||
118 | + | ||
119 | +The final, generated code for the loop body is: | ||
120 | + | ||
121 | +32-bit 64-bit | ||
122 | +add r25,r11,r0 add r5,r5,r8 | ||
123 | +add r26,r0,r25 addi r4,r4,12 | ||
124 | +stw r25,0(r9) add r27,r5,r8 | ||
125 | +add r27,r25,r26 stw r5,0(r9) | ||
126 | +stw r26,4(r9) extsw r12,r27 <=== | ||
127 | +add r28,r26,r27 stw r27,4(r9) | ||
128 | +stw r27,8(r9) add r6,r5,r12 | ||
129 | +add r29,r27,r28 add r28,r6,r12 | ||
130 | +stw r28,12(r9) stw r6,8(r9) | ||
131 | +add r30,r28,r29 extsw r0,r28 <=== | ||
132 | +stw r29,16(r9) stw r28,12(r9) | ||
133 | +add r12,r29,r30 add r7,r6,r0 | ||
134 | +stw r30,20(r9) add r29,r7,r0 | ||
135 | +add r3,r30,r12 stw r7,16(r9) | ||
136 | +stw r12,24(r9) extsw r3,r29 <=== | ||
137 | +add r4,r12,r3 stw r29,20(r9) | ||
138 | +stw r3,28(r9) add r10,r7,r3 | ||
139 | +add r5,r3,r4 add r30,r10,r3 | ||
140 | +stw r4,32(r9) stw r10,24(r9) | ||
141 | +add r6,r4,r5 extsw r8,r30 <=== | ||
142 | +stw r5,36(r9) stw r30,28(r9) | ||
143 | +add r7,r5,r6 add r11,r10,r8 | ||
144 | +stw r6,40(r9) add r12,r11,r8 | ||
145 | +add r8,r6,r7 stw r11,32(r9) | ||
146 | +stw r7,44(r9) extsw r26,r12 <=== | ||
147 | +add r10,r7,r8 stw r12,36(r9) | ||
148 | +stw r8,48(r9) add r0,r11,r26 | ||
149 | +add r11,r8,r10 add r3,r0,r26 | ||
150 | +stw r10,52(r9) stw r0,40(r9) | ||
151 | +add r0,r10,r11 subfic r26,r4,100 | ||
152 | +stw r11,56(r9) stw r3,44(r9) | ||
153 | +stw r0,60(r9) extsw r5,r0 <=== | ||
154 | +addi r9,r9,64 extsw r8,r3 <=== | ||
155 | +bdnz+ 10000640 extsw r4,r4 <=== | ||
156 | + clrldi r26,r26,32 | ||
157 | + addi r9,r9,48 | ||
158 | + bdnz+ 10000890 | ||
159 | + | ||
160 | +GENERAL APPROACH: | ||
161 | +Consider a machine whose native register size is 64-bits | ||
162 | + | ||
163 | +0 3132 63 | ||
164 | +|-----------||-----------| | ||
165 | + | ||
166 | +where bit 63 is the LSB and bit 0 is the MSB of a long int | ||
167 | +and bit 63 is the LSB and bit 32 is the MSB of an int. | ||
168 | + | ||
169 | +Sign and zero extension are inserted to RTL to preserve the | ||
170 | +operation's semantics when the operands used are not the | ||
171 | +native register size since normally the machine only performs | ||
172 | +the operation using a native register size. In practice, many | ||
173 | +of the inserted extensions are not necessary. | ||
174 | + | ||
175 | +First, the extension may simply be redundant. That is, the | ||
176 | +same operation is performed on the same operands. The redundant | ||
177 | +extensions can be eliminated. | ||
178 | + | ||
179 | +Secondly, if the extended portion of the register (the "upper" bits) | ||
180 | +are not essential to the calculations performed on the output of the | ||
181 | +extension, then the extension is not necessary. For example, given | ||
182 | +int (32-bit) inputs and outputs: | ||
183 | + | ||
184 | +c = a + b | ||
185 | +d = sxt(c) | ||
186 | +e = d + 1; | ||
187 | + | ||
188 | +The "upper" bits of d (bit 0-31) do not affect the calculation | ||
189 | +of e. It doesn't matter what the "upper" bits of d are, the int result | ||
190 | +e is the same regardless of the sxt instruction. | ||
191 | + | ||
192 | +Thirdly, the extensions may not be necessary if the operands are | ||
193 | +already extended and the operation preserves the extended bits. | ||
194 | + | ||
195 | +a = mem[&b] ; sign extending load | ||
196 | +c = a + 1 | ||
197 | +d = sxt(c) | ||
198 | + | ||
199 | +Here, a is generated by a sign extending load, the operation | ||
200 | +does nothing to invalidate the extension to c, thus the extension | ||
201 | +on c to d is not necessary. | ||
202 | + | ||
203 | +In each case, the redundant extension must be replaced by a copy, | ||
204 | +with the copy to be optimized out in later phases. | ||
205 | + | ||
206 | +The three cases described above form the general idea behind the | ||
207 | +algorithms implemented here to eliminate redundant and unneccessary | ||
208 | +extensions. | ||
209 | + | ||
210 | +Sign extensions do not have to be preserved for overflow conditions | ||
211 | +since signed overflow behavior is not defined in C. For example, | ||
212 | +take a 16-bit variable in a 32-bit register. It is ok | ||
213 | +for 0x0000_7fff to overflow to 0x0000_8000 and not 0xffff_8000. | ||
214 | +This implies that it is not necessary to preserve the sign | ||
215 | +extension. | ||
216 | + | ||
217 | +Unsigned overflow extension need to be preserved because | ||
218 | +unsigned overflow is modulo. For example, a 16-bit unsigned | ||
219 | +overflow of 0x0000_FFFF must be 0x0000_0000 in a 32-bit register, | ||
220 | +not 0x0001_0000. In order to remove the unsigned zero extension, | ||
221 | +we would need to range check the variable to be sure it doesn't | ||
222 | +overflow. | ||
223 | + | ||
224 | +RTL ANALYSIS: | ||
225 | +I looked at the RTL representation after RTL generation (.expand) and | ||
226 | +after the first forward propagation (.fwprop1). Since RTL is not compact | ||
227 | +when printing out, I reduced the .fwprop1 RTL to this pseudocode: | ||
228 | + | ||
229 | +(note: sxt,zxt mean double word length, 64-bit, extension). | ||
230 | + | ||
231 | +(1) r198 = m[r113+ #112] ; load a[0] | ||
232 | +(2) r174 = sxt(r198) | ||
233 | +(3) r199 = m[r113+ #116] ; load a[1] | ||
234 | +(4) r186 = sxt(r199) | ||
235 | +(5) r181 = r113 + #120 ; load &a[2] | ||
236 | +(6) r180 = 2 ; i = 2 | ||
237 | +(7) L1: | ||
238 | +(8) r200 = r174 + r186 ; t1 = a[i-1] + a[i-2] | ||
239 | +(9) r174 = sxt(r200) | ||
240 | +(10) m[r181] = r200 ; a[i] = t1 | ||
241 | +(11) r201 = r200 + r186 ; t2 = t1 + a[i-1] | ||
242 | +(12) r186 = sxt(r201) | ||
243 | +(13) m[r181+4] = r201 ; a[i+1] = t2 | ||
244 | +(14) r202 = r180 + 2 ; i += 2 | ||
245 | +(14.1) r180 = sxt(r202) | ||
246 | +(15) r203 = 100 - r202 ; used to calc loop remainder | ||
247 | +(16) r185 = zxt(r203) ; used to calc loop remainder | ||
248 | +(17) r181 = r181 + 8 ; address induction var | ||
249 | +(18) ccr204 = cmp(r202,#98) ; set CC | ||
250 | +(19) BNE ccr204,L1 ; branch | ||
251 | + | ||
252 | +In the pseudo-code, you see several sign extension candidates: (2),(4), | ||
253 | +(9), (12), (14.1), (16). | ||
254 | + | ||
255 | +ALGORITHM: | ||
256 | +To eliminate the extra sign ext you have to look at (1) the definitions | ||
257 | +of the source of the sign extensions and/or (2) look at the uses of the target | ||
258 | +of the sign extensions. In either case, if doing a global elimination | ||
259 | +pass, you'll need def-use chain information. | ||
260 | + | ||
261 | +The algorithms are recursive. Using the use/def and def/use chains | ||
262 | +we attempt to find ultimately whether the extension is relevant | ||
263 | +or not. | ||
264 | + | ||
265 | + | ||
266 | +Example 1. | ||
267 | +Extensions (2) and (4) are not put in the candidate list because | ||
268 | +they are combined into a load/ext pair that is ultimately generated | ||
269 | +as sign extending loads. | ||
270 | + | ||
271 | +Take the sign extension at (9), r174 = sxt(r200). | ||
272 | +Def analysis shows that r200 is defined by 2 registers, thus no | ||
273 | +further def analysis recursion can occur. | ||
274 | +Use analysis. Find all the uses of r174. There is 1 use at (8) r200 = r174 + r186. | ||
275 | +The extension does not affect the add operation results. Continuing, we look at | ||
276 | +the uses of r200 to see if the results of operations on r200 need the sign extended bits. | ||
277 | +We see 2 uses of r200 at (10) and (11). (10) is a 32-bit store of r200, | ||
278 | +so the sign extended bits are irrelevant. (11), however, is an unknown, | ||
279 | +so we must look that the uses of this result, r201. A similar sequence | ||
280 | +occurs for r201 when it defines r186. Looking at the uses of r186 at | ||
281 | +(8) and (11), we have already visited those statements so they have | ||
282 | +been covered already. So it appears that the sxt to r174 at (9) ultimately | ||
283 | +dead-ends to a store instruction that doesn't case about the sign extended | ||
284 | +bits. The sxt at (9) can be removed. | ||
285 | + | ||
286 | +The remaining extensions are processed similarly. | ||
287 | + | ||
288 | +PROGRAM STRUCTURE: | ||
289 | + | ||
290 | +extension elimination -- main entry point | ||
291 | + find extensions -- identify extension candidates | ||
292 | + extension duplication -- insert extension at strategic points to | ||
293 | + enable removal of extensions at more frequently | ||
294 | + executed points. | ||
295 | + find extensions -- recreate extension candidate list | ||
296 | + sort extensions -- sort extension candidate list by loop depth | ||
297 | + for each ext in list -- process each extension candidate | ||
298 | + eliminate one extension | ||
299 | + replace marked candidates with copy -- optimize the extension | ||
300 | + | ||
301 | +PSEUDOCODE: | ||
302 | + | ||
303 | +Create working list of sign extensions, sxt_list | ||
304 | + | ||
305 | +For each insn, insn_sxt, in sxt_list | ||
306 | + ext_needed = true | ||
307 | + For all insns, insn_def, that DEFINE and REACH the SOURCE_REG(insn_sxt) | ||
308 | + ext_needed = analyze_def(insn_def, insn_sxt) | ||
309 | + if (ext_needed) | ||
310 | + break; | ||
311 | + end_loop | ||
312 | + if (ext_needed) | ||
313 | + For all insns, insn_use, that USE and are REACHED by the DEST_REG(insn_sxt) | ||
314 | + ext_needed = analyze_use(insn_use, insn_sxt) | ||
315 | + if (ext_needed) | ||
316 | + break; | ||
317 | + end_loop | ||
318 | + | ||
319 | + if (!ext_needed) | ||
320 | + mark_for_replace_with_copy(I) | ||
321 | +end_loop | ||
322 | + | ||
323 | +For each insn, insn_sxt, in sxt_list | ||
324 | + if (insn_sxt is marked for replacement) | ||
325 | + replace_insn_with_copy(insn_sxt) | ||
326 | +end_loop | ||
327 | + | ||
328 | +-------------------------- | ||
329 | +function: analyze_def(def) | ||
330 | +--------------------------- | ||
331 | +return true if extension is needed, false otherwise. | ||
332 | + | ||
333 | +destination_operand = defined operand of source | ||
334 | +source_operand = source operand of def | ||
335 | + | ||
336 | +if (have_seen_this_insn_already (def)) | ||
337 | + return true; | ||
338 | + | ||
339 | +set_seen_this_insn_flag (def) | ||
340 | + | ||
341 | +analysis_result = analyze_result_def (def) | ||
342 | +switch (analysis_result) | ||
343 | + case source_operand_is_extended: | ||
344 | + return false | ||
345 | + case stop_recursion: | ||
346 | + return true | ||
347 | + case continue_recursion: | ||
348 | + break; | ||
349 | + | ||
350 | +ext_needed = true; | ||
351 | + | ||
352 | +For all insns, insn_def, that USE and REACHED by the register of destination_operand | ||
353 | + ext_needed = analyze_def(insn_def)) | ||
354 | + if (ext_needed) | ||
355 | + break; | ||
356 | +end_loop | ||
357 | + | ||
358 | +return ext_needed | ||
359 | + | ||
360 | +-------------------------- | ||
361 | +function: analyze_use(use) | ||
362 | +--------------------------- | ||
363 | +return true if extension is needed, false otherwise. | ||
364 | + | ||
365 | +destination_operand = destination operand of use | ||
366 | +source_operand = source operand of use | ||
367 | + | ||
368 | +if (have_seen_this_insn_already (use)) | ||
369 | + return false; | ||
370 | + | ||
371 | +set_seen_this_insn_flag (use) | ||
372 | + | ||
373 | +analysis_result = analyze_result_use (use) | ||
374 | +switch (analysis_result) | ||
375 | + case low_bits_not_affected_by_use: | ||
376 | + return false | ||
377 | + case low_bits_affected_by_use: | ||
378 | + return true | ||
379 | + case look_at_uses_of_destination_operand | ||
380 | + break; | ||
381 | + | ||
382 | +ext_needed = true; | ||
383 | +For all insns, insn_use, that USE the register of destination_operand | ||
384 | + ext_needed = analyze_use(insn_use)) | ||
385 | + if (ext_needed) | ||
386 | + break; | ||
387 | +end_loop | ||
388 | + | ||
389 | +return ext_needed | ||
390 | + | ||
391 | +REFERENCES: | ||
392 | + | ||
393 | +"Effective Sign Extension Elimination", Kawahito, Komatsu, Nakatani. | ||
394 | +IBM Tokyo Researc Laboratory. | ||
395 | + | ||
396 | +"New sign/zero extension elimination pass", deVries. | ||
397 | +http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01529.html | ||
398 | +*/ | ||
399 | + | ||
400 | +/* | ||
401 | +Iteration 4: pre-ZERO_EXTEND version, duplicates sign_extend at uses | ||
402 | +Iteration 5: begin supporting ZERO_EXTEND, crashes on Coremark. | ||
403 | +Iteration 6: revert to 4, support SI:HI sign_extensions. | ||
404 | +Iteration 7: Add support for zero extend. This version deletes | ||
405 | + "inserted" duplicate extensions when redundant and propagates | ||
406 | + the copied value. This propagate fails in other_tests/test2.sh. | ||
407 | + I am reverting back to replacing the "inserted" extension to a copy. | ||
408 | + Copy propagation should always be able to eliminate this copy. | ||
409 | + Coremark was stable, however. | ||
410 | +Iteration 8: Revert to change extensions to copy, regardless of whether | ||
411 | + the extension was duplicated or not. | ||
412 | + Refactor setting of dest,src in analyze_ext_use, analyze_ext_def, now | ||
413 | + handled with a single function. | ||
414 | +Iteration 9: | ||
415 | + Inserted redundant extensions at function return points. | ||
416 | + Sorted the order that extensions are processed by loop depth. | ||
417 | + Additional cases in upper_bits_do_not_affect_dest | ||
418 | +Iteration 10: | ||
419 | + Fixes for test failures. A major problem was uncovered where | ||
420 | + the "visited" flag was not properly cleared. This meant that | ||
421 | + each time a new extension was processed, it appeared that some | ||
422 | + extensions were visited already and there were not. The result | ||
423 | + was false removals. This fix significantly affects the benchmark. | ||
424 | + Another change was to comment out the duplicate_exts_at_uses. This | ||
425 | + seemed to have little effect now that the visited flag issue is | ||
426 | + fixed. | ||
427 | +Iteration 11: | ||
428 | + Cleanup warnings during build. | ||
429 | +Iteration 12: | ||
430 | + QImode support started. | ||
431 | +Iteration 13: | ||
432 | + Redesign and refactor analyze_ext_use, analyze_ext_def | ||
433 | +Iteration 14: | ||
434 | + Continue redesign and refactor of analyze_ext_use, analyze_ext_def | ||
435 | + Debugging paper_example.c | ||
436 | +Iteration 15: | ||
437 | + cond_c fix | ||
438 | +Iteration 16: (not tested) | ||
439 | + Refactor check_compare code | ||
440 | + Refactor action decision in PARALLEL | ||
441 | + Allow pass-thru on insns that are marked for replace copy | ||
442 | + instead of stopping recursion if we see a marked insn. | ||
443 | + Examining lshiftrt.c program (signed and unsigned). | ||
444 | +Iteration 17: | ||
445 | + Refactor mostly complete. Passed all local testing including | ||
446 | + nas and perfect. Best coremark results so far. | ||
447 | +Iteration 18: | ||
448 | + Oops. analyze_ext_def was disabled. Enabling it improves | ||
449 | + Coremark. Passed coremark, perfect. | ||
450 | +Iteration 19: | ||
451 | + Local tests are passing. Tested with glibc. | ||
452 | + Added statistics. | ||
453 | + Fixed elimination from CALL output in operand_is_extended. | ||
454 | + This impacted Coremark went from 6300 to 6170. But is necessary. | ||
455 | + More safety for used regs in analyze_ext_def. | ||
456 | + More safety for the types of extensions. | ||
457 | +Iteration 20: | ||
458 | + Fixes for various tests. | ||
459 | +Iteration 21: | ||
460 | + pr43017 -funroll_loops fix. | ||
461 | +Iteration 22: | ||
462 | + Fixes for AND immediate in operand_is_extended. | ||
463 | + Cosmetic cleanup. | ||
464 | +Iteration 23: | ||
465 | + Fixes for consumer-2,spec2k,spec2k6. Handle | ||
466 | + SUBREG_PROMOTED_VAR_P flags on operands whose | ||
467 | + dependent extension has been eliminated. | ||
468 | +Iteration 24: | ||
469 | + Fixed problem in native build during bootstrapping. | ||
470 | + Extelim was considering debug_insns and should have | ||
471 | + ignored them. This resulted in a compare fail between | ||
472 | + stage2 and stage3. | ||
473 | +Iteration 25: | ||
474 | + - Post-release 4.6.1 development | ||
475 | + - Full duplication of extensions at uses turned on. | ||
476 | + - Recursion into original extension no longer kills optimization (analyze_ext_def only) | ||
477 | + - Allow some duplication into the same block if it enables insn selection | ||
478 | + - Allow CCmode and CCUNSmode into mode_supported_p | ||
479 | +Iteration 26: | ||
480 | + - Solve ICEs due to null df-ref. | ||
481 | +Iteration 27: | ||
482 | + - Fixed issue with duplication of extension at a self-assign. | ||
483 | + - Some fixes for copying flags during duplication | ||
484 | + - Some fixes for counting register uses. | ||
485 | +Iteration 28: | ||
486 | + - Fixed issue with duplication of extension when use has multiple | ||
487 | + reaching definitions. | ||
488 | +Iteration 29: | ||
489 | + - Release candidate for Q42011 release iteration. | ||
490 | +Iteration 30: | ||
491 | + - Turn off extension duplication - minimally effective | ||
492 | + | ||
493 | +*/ | ||
494 | + | ||
495 | +#include "config.h" | ||
496 | +#include "system.h" | ||
497 | +#include "coretypes.h" | ||
498 | +#include "tm.h" | ||
499 | +#include "rtl.h" | ||
500 | +#include "tree.h" | ||
501 | +#include "tm_p.h" | ||
502 | +#include "flags.h" | ||
503 | +#include "regs.h" | ||
504 | +#include "hard-reg-set.h" | ||
505 | +#include "basic-block.h" | ||
506 | +#include "insn-config.h" | ||
507 | +#include "function.h" | ||
508 | +#include "expr.h" | ||
509 | +#include "insn-attr.h" | ||
510 | +#include "recog.h" | ||
511 | +#include "toplev.h" | ||
512 | +#include "target.h" | ||
513 | +#include "timevar.h" | ||
514 | +#include "optabs.h" | ||
515 | +#include "insn-codes.h" | ||
516 | +#include "rtlhooks-def.h" | ||
517 | +#include "output.h" | ||
518 | +#include "params.h" | ||
519 | +#include "timevar.h" | ||
520 | +#include "tree-pass.h" | ||
521 | +#include "cgraph.h" | ||
522 | +#include "df.h" | ||
523 | +#include "vec.h" | ||
524 | + | ||
525 | +/* Feature flags */ | ||
526 | +/* Duplicate extensions at each immediate use */ | ||
527 | +#define EXTELIM_DUPLICATE_EXTS_AT_USES 0 | ||
528 | +/* Dump DF information also in dump */ | ||
529 | +#define EXTELIM_DF_DUMP 0 | ||
530 | + | ||
531 | + | ||
532 | +/* Typedefs */ | ||
533 | +typedef unsigned int insn_flag_t; /* Insn flags type */ | ||
534 | +typedef int extelim_uid_t; /* UID type */ | ||
535 | +DEF_VEC_I (insn_flag_t); /* Define vector type and allocation type */ | ||
536 | +DEF_VEC_ALLOC_I (insn_flag_t, heap); | ||
537 | + | ||
538 | +typedef struct GTY (()) ext_record | ||
539 | +{ | ||
540 | + rtx ext; /* The extension insn */ | ||
541 | + VEC (rtx, heap) * ext_uses; /* List of use records for this extension. For some | ||
542 | + some extensions, we will duplicate the extension | ||
543 | + at these use points. */ | ||
544 | + VEC (rtx, heap) * ext_updates;/* List of rtx that need to be updated if the extension | ||
545 | + is to be eliminated. For example, SUBREG_PROMOTED flags | ||
546 | + on SUBREG uses defined by this extension should | ||
547 | + be reset since the extension is eliminated. The PROMOTED | ||
548 | + flag is no longer valid. */ | ||
549 | +} *ext_record_t; | ||
550 | + | ||
551 | +typedef struct regspec_cb_data | ||
552 | +{ | ||
553 | + unsigned int regno; | ||
554 | + rtx exp; | ||
555 | +} regspec_cb_data_t; | ||
556 | + | ||
557 | +/* Static variables */ | ||
558 | +DEF_VEC_P (ext_record_t); | ||
559 | +DEF_VEC_ALLOC_P (ext_record_t, heap); | ||
560 | +VEC (ext_record_t, heap) * extensions; /* Vector holding all extension records */ | ||
561 | +VEC (insn_flag_t, heap) * insn_flags; /* Vector holding flags for all insns */ | ||
562 | +VEC (rtx, heap) * returns; /* Vector holding return insns for this function */ | ||
563 | + | ||
564 | + static extelim_uid_t max_uid; /* Max UID insn value for insn_flags allocation */ | ||
565 | + static ext_record_t current_ext_record; /* Current extension record being processed */ | ||
566 | + | ||
567 | +/* Statistics */ | ||
568 | + static int num_cand; /* Number of extensions detected */ | ||
569 | + static int num_cand_ignored; /* Number of extensions ignored */ | ||
570 | + static int num_cand_transformed; /* Number of extensions transformed to copy */ | ||
571 | + | ||
572 | +/* Basic information about the extension being processed */ | ||
573 | + enum machine_mode ext_to_mode; /* Mode extended to */ | ||
574 | + enum machine_mode ext_from_mode; /* Mode extended from */ | ||
575 | + enum rtx_code ext_code; /* Sign or zero extend */ | ||
576 | + | ||
577 | +/* Insn use analysis possible results */ | ||
578 | + enum insn_use_results | ||
579 | + { | ||
580 | + EXTELIM_ANALYSIS_RESULT_LOWBITS_NOT_AFFECTED, | ||
581 | + EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED, | ||
582 | + EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION | ||
583 | + }; | ||
584 | + | ||
585 | +/* Insn def analysis possible results */ | ||
586 | + enum insn_def_results | ||
587 | + { | ||
588 | + EXTELIM_ANALYSIS_RESULT_DEF_EXTENDED, | ||
589 | + EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION, | ||
590 | + EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION | ||
591 | + }; | ||
592 | + | ||
593 | +/* Insn flags for this pass */ | ||
594 | +#define EXTELIM_NONE 0 | ||
595 | +#define EXTELIM_SEEN (1<<0) /* Mark insn as visited during DF traversal */ | ||
596 | +#define EXTELIM_REPLACE_COPY (1<<1) /* Mark ext insn as replace with copy */ | ||
597 | +#define EXTELIM_INSERTED (1<<2) /* Mark ext insn as algorithmically inserted */ | ||
598 | +#define EXTELIM_INSERTED_FOR (1<<3) /* Mark use insn for which ext has been inserted */ | ||
599 | + | ||
600 | + | ||
601 | +/* Query the insn flag */ | ||
602 | + | ||
603 | + static bool insn_flag_p (insn_flag_t set_p, extelim_uid_t uid) | ||
604 | +{ | ||
605 | + insn_flag_t flags; | ||
606 | + | ||
607 | + if (((flags = VEC_index (insn_flag_t, insn_flags, uid)) & set_p) == set_p) | ||
608 | + return true; | ||
609 | + | ||
610 | + return false; | ||
611 | +} | ||
612 | + | ||
613 | +/* Set the insn flags */ | ||
614 | + | ||
615 | +static void | ||
616 | +insn_flag_set (insn_flag_t flags, extelim_uid_t uid) | ||
617 | +{ | ||
618 | + insn_flag_t set; | ||
619 | + set = VEC_index (insn_flag_t, insn_flags, uid); | ||
620 | + set |= flags; | ||
621 | + VEC_replace (insn_flag_t, insn_flags, uid, set); | ||
622 | +} | ||
623 | + | ||
624 | +/* Clear insn flags */ | ||
625 | + | ||
626 | +static void | ||
627 | +insn_flag_clear (insn_flag_t flags, extelim_uid_t uid) | ||
628 | +{ | ||
629 | + insn_flag_t clear; | ||
630 | + clear = VEC_index (insn_flag_t, insn_flags, uid); | ||
631 | + clear &= ~flags; | ||
632 | + VEC_replace (insn_flag_t, insn_flags, uid, clear); | ||
633 | +} | ||
634 | + | ||
635 | +/* Set static variable max_uid to the largest | ||
636 | + insn uid found in the module plus 1. This will be the | ||
637 | + size of the vector for insn flags. */ | ||
638 | + | ||
639 | +static void | ||
640 | +set_max_uid (void) | ||
641 | +{ | ||
642 | + basic_block bb; | ||
643 | + rtx insn; | ||
644 | + extelim_uid_t lmax_uid = 0; | ||
645 | + | ||
646 | + FOR_EACH_BB (bb) FOR_BB_INSNS (bb, insn) | ||
647 | + { | ||
648 | + if (INSN_P (insn)) | ||
649 | + { | ||
650 | + if (INSN_UID (insn) > lmax_uid) | ||
651 | + lmax_uid = INSN_UID (insn); | ||
652 | + } | ||
653 | + } | ||
654 | + max_uid = lmax_uid + 1; | ||
655 | +} | ||
656 | + | ||
657 | +/* Re-initializes the requested insn flags to their reset state */ | ||
658 | + | ||
659 | +static void | ||
660 | +reinit_insn_flags (insn_flag_t flags_to_be_reset) | ||
661 | +{ | ||
662 | + extelim_uid_t i; | ||
663 | + | ||
664 | + /* Account for new insns */ | ||
665 | + set_max_uid (); | ||
666 | + | ||
667 | + for (i = 0; i < max_uid; i++) | ||
668 | + { | ||
669 | + insn_flag_clear (flags_to_be_reset, i); | ||
670 | + } | ||
671 | +} | ||
672 | + | ||
673 | +/* Init the vector for insn flags. One | ||
674 | + vector element per insn is created. | ||
675 | + The flags are init'd to EXTELIM_NONE. */ | ||
676 | + | ||
677 | +static void | ||
678 | +init_flags_vector (void) | ||
679 | +{ | ||
680 | + extelim_uid_t i; | ||
681 | + /* Get the maximum uid value. We'll use this | ||
682 | + information to set up a vector of max_uid | ||
683 | + length. Each element of the vector will hold | ||
684 | + the pass-specific flags for each insn. */ | ||
685 | + max_uid = 0; | ||
686 | + set_max_uid (); | ||
687 | + | ||
688 | + /* Allocate the vector of insn flags */ | ||
689 | + insn_flags = VEC_alloc (insn_flag_t, heap, max_uid); | ||
690 | + | ||
691 | + /* Initialize the insn flags vector */ | ||
692 | + for (i = 0; i < max_uid; i++) | ||
693 | + { | ||
694 | + VEC_quick_insert (insn_flag_t, insn_flags, i, EXTELIM_NONE); | ||
695 | + } | ||
696 | +} | ||
697 | + | ||
698 | +/* Initialize this pass */ | ||
699 | + | ||
700 | +static void | ||
701 | +init_pass (void) | ||
702 | +{ | ||
703 | + /* Init insn flags vector */ | ||
704 | + init_flags_vector (); | ||
705 | + | ||
706 | + /* This pass requires def-use chain information */ | ||
707 | + df_chain_add_problem (DF_DU_CHAIN + DF_UD_CHAIN); | ||
708 | + df_analyze (); | ||
709 | +} | ||
710 | + | ||
711 | +static void | ||
712 | +free_extensions (void) | ||
713 | +{ | ||
714 | + ext_record_t ext_record; | ||
715 | + unsigned i; | ||
716 | + | ||
717 | + FOR_EACH_VEC_ELT (ext_record_t, extensions, i, ext_record) | ||
718 | + { | ||
719 | + if (!VEC_empty (rtx, ext_record->ext_uses)) | ||
720 | + VEC_free (rtx, heap, ext_record->ext_uses); | ||
721 | + | ||
722 | + if (!VEC_empty (rtx, ext_record->ext_updates)) | ||
723 | + VEC_free (rtx, heap, ext_record->ext_updates); | ||
724 | + } | ||
725 | + VEC_free (ext_record_t, heap, extensions); | ||
726 | +} | ||
727 | + | ||
728 | +/* Clean up this pass */ | ||
729 | + | ||
730 | +static void | ||
731 | +finish_pass (void) | ||
732 | +{ | ||
733 | + free_extensions (); | ||
734 | + VEC_free (insn_flag_t, heap, insn_flags); | ||
735 | + VEC_free (rtx, heap, returns); | ||
736 | +} | ||
737 | + | ||
738 | +static void | ||
739 | +update_uid_vectors (extelim_uid_t uid) | ||
740 | +{ | ||
741 | + VEC_safe_grow_cleared (insn_flag_t, heap, insn_flags, uid + 1); | ||
742 | +} | ||
743 | + | ||
744 | +/* Emit a insn before a given insn, update vector lengths | ||
745 | + of those vectors that are indexed by uid. Return uid | ||
746 | + of the inserted insn. */ | ||
747 | + | ||
748 | +static extelim_uid_t | ||
749 | +extelim_emit_before (rtx new_insn, rtx before_insn) | ||
750 | +{ | ||
751 | + rtx seq; | ||
752 | + extelim_uid_t new_uid; | ||
753 | + | ||
754 | + start_sequence (); | ||
755 | + emit_insn (new_insn); | ||
756 | + seq = get_insns (); | ||
757 | + end_sequence (); | ||
758 | + new_insn = emit_insn_before (seq, before_insn); | ||
759 | + | ||
760 | + /* Expand the flags vector to hold the new insn and set the | ||
761 | + inserted flag on the insn. */ | ||
762 | + new_uid = INSN_UID (new_insn); | ||
763 | + update_uid_vectors (new_uid); | ||
764 | + return new_uid; | ||
765 | +} | ||
766 | + | ||
767 | +/* Utility function to find the REG exp | ||
768 | + given an rtx */ | ||
769 | + | ||
770 | +static rtx | ||
771 | +register_exp (rtx exp) | ||
772 | +{ | ||
773 | + if (REG_P (exp)) | ||
774 | + { | ||
775 | + return exp; | ||
776 | + } | ||
777 | + else if (GET_CODE (exp) == SUBREG) | ||
778 | + { | ||
779 | + return SUBREG_REG (exp); | ||
780 | + } | ||
781 | + else | ||
782 | + return NULL; | ||
783 | +} | ||
784 | + | ||
785 | +/* Check whether this is a sign extension. */ | ||
786 | + | ||
787 | +static bool | ||
788 | +extension_p (rtx insn, rtx * dest, rtx * inner, int *preserved_size) | ||
789 | +{ | ||
790 | + rtx src, op0; | ||
791 | + | ||
792 | + /* Detect set of reg. */ | ||
793 | + if (GET_CODE (PATTERN (insn)) != SET) | ||
794 | + return false; | ||
795 | + | ||
796 | + src = SET_SRC (PATTERN (insn)); | ||
797 | + *dest = SET_DEST (PATTERN (insn)); | ||
798 | + | ||
799 | + if (!REG_P (*dest)) | ||
800 | + return false; | ||
801 | + | ||
802 | + if (GET_CODE (src) == SIGN_EXTEND || GET_CODE (src) == ZERO_EXTEND) | ||
803 | + { | ||
804 | + op0 = XEXP (src, 0); | ||
805 | + | ||
806 | + /* Determine amount of least significant bits preserved by operation. */ | ||
807 | + if (GET_CODE (src) == AND) | ||
808 | + *preserved_size = ctz_hwi (~UINTVAL (XEXP (src, 1))); | ||
809 | + else | ||
810 | + *preserved_size = GET_MODE_BITSIZE (GET_MODE (op0)); | ||
811 | + | ||
812 | + if (GET_CODE (op0) == SUBREG) | ||
813 | + { | ||
814 | + if (subreg_lsb (op0) != 0) | ||
815 | + return false; | ||
816 | + | ||
817 | + *inner = SUBREG_REG (op0); | ||
818 | + return true; | ||
819 | + } | ||
820 | + else if (REG_P (op0)) | ||
821 | + { | ||
822 | + *inner = op0; | ||
823 | + return true; | ||
824 | + } | ||
825 | + } | ||
826 | + | ||
827 | + return false; | ||
828 | +} | ||
829 | + | ||
830 | +/* Return true if this is the last use of a | ||
831 | + register, false otherwise. */ | ||
832 | + | ||
833 | +static bool | ||
834 | +reg_is_dead_p (rtx insn, rtx reg_expr) | ||
835 | +{ | ||
836 | + rtx link; | ||
837 | + gcc_assert (REG_P (reg_expr)); | ||
838 | + | ||
839 | + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | ||
840 | + { | ||
841 | + if (REG_NOTE_KIND (link) == REG_DEAD && REG_P (XEXP (link, 0))) | ||
842 | + { | ||
843 | + if (REGNO (XEXP (link, 0)) == REGNO (reg_expr)) | ||
844 | + return true; | ||
845 | + } | ||
846 | + } | ||
847 | + return false; | ||
848 | +} | ||
849 | + | ||
850 | +/* Return true if we don't want to place this | ||
851 | + extension in the candidate extensions list because of the | ||
852 | + previous insn. Return false otherwise. */ | ||
853 | + | ||
854 | +static bool | ||
855 | +ignore_extension_prev_p (rtx ext_insn, rtx prev_insn) | ||
856 | +{ | ||
857 | + rtx prev_dest, prev_src, prev = PATTERN (prev_insn); | ||
858 | + rtx ext_src, ext = PATTERN (ext_insn); | ||
859 | + | ||
860 | + /* It's OK to allow extension with no accompanying prev real insn */ | ||
861 | + if (!NONDEBUG_INSN_P (prev_insn) || NOTE_P (prev_insn)) | ||
862 | + return false; | ||
863 | + | ||
864 | + if (GET_CODE (prev) != SET) | ||
865 | + return false; | ||
866 | + | ||
867 | + if (GET_CODE (ext) != SET) | ||
868 | + return false; | ||
869 | + | ||
870 | + prev_dest = SET_DEST (prev); | ||
871 | + prev_src = SET_SRC (prev); | ||
872 | + | ||
873 | + /* Source register of sign extension */ | ||
874 | + ext_src = XEXP (SET_SRC (ext), 0); | ||
875 | + | ||
876 | + /* Check previous insns */ | ||
877 | + | ||
878 | + /* Previous insn is a load whose dest is the | ||
879 | + extension's source and the dest reg is | ||
880 | + dead */ | ||
881 | + if (MEM_P (prev_src) && (prev_dest = register_exp (prev_dest))) | ||
882 | + { | ||
883 | + if ((ext_src = register_exp (ext_src))) | ||
884 | + { | ||
885 | + if ((REGNO (prev_dest) == REGNO (ext_src)) | ||
886 | + && reg_is_dead_p (ext_insn, ext_src)) | ||
887 | + return true; | ||
888 | + } | ||
889 | + } | ||
890 | + return false; | ||
891 | +} | ||
892 | + | ||
893 | +/* Return true if we don't want to place this | ||
894 | + extension in the candidate extensions list because of the | ||
895 | + next insn. Return false otherwise. */ | ||
896 | + | ||
897 | +static bool | ||
898 | +ignore_extension_next_p (rtx ext_insn, rtx next_insn) | ||
899 | +{ | ||
900 | + rtx next = PATTERN (next_insn); | ||
901 | + rtx ext_src, ext = PATTERN (ext_insn); | ||
902 | + | ||
903 | + if (GET_CODE (ext) != SET) | ||
904 | + return false; | ||
905 | + | ||
906 | + /* Check next insns */ | ||
907 | + if (!NONDEBUG_INSN_P (next_insn) || NOTE_P (next_insn)) | ||
908 | + return false; | ||
909 | + | ||
910 | + if (GET_CODE (next) != SET) | ||
911 | + return false; | ||
912 | + | ||
913 | + /* zero-extend followed by left shift by 1 -- this sequence will be | ||
914 | + detected by the insn selection. */ | ||
915 | + if (GET_CODE (SET_SRC (ext)) == ZERO_EXTEND) | ||
916 | + { | ||
917 | + if (GET_CODE (SET_SRC (next)) == ASHIFT | ||
918 | + && CONST_INT_P (XEXP (SET_SRC (next), 1)) | ||
919 | + && UINTVAL (XEXP (SET_SRC (next), 1)) == 0x1) | ||
920 | + return true; | ||
921 | + } | ||
922 | + | ||
923 | + return false; | ||
924 | +} | ||
925 | + | ||
926 | +/* Find extensions and store them in the extensions vector. */ | ||
927 | + | ||
928 | +static bool | ||
929 | +find_extensions (void) | ||
930 | +{ | ||
931 | + basic_block bb; | ||
932 | + rtx insn, dest, inner; | ||
933 | + int preserved_size; | ||
934 | + ext_record_t extrec; | ||
935 | + | ||
936 | + /* For all insns, call note_use for each use in insn. */ | ||
937 | + FOR_EACH_BB (bb) | ||
938 | + { | ||
939 | + FOR_BB_INSNS (bb, insn) | ||
940 | + { | ||
941 | + if (!NONDEBUG_INSN_P (insn)) | ||
942 | + continue; | ||
943 | + | ||
944 | + if (!extension_p (insn, &dest, &inner, &preserved_size)) | ||
945 | + { | ||
946 | + continue; | ||
947 | + } | ||
948 | + | ||
949 | + /* We do not consider extensions that follow a load for | ||
950 | + this target, as the code selector optimizes the sequence | ||
951 | + to a load with sign extend or load with zero extend. */ | ||
952 | + if (PREV_INSN (insn) | ||
953 | + && ignore_extension_prev_p (insn, PREV_INSN (insn))) | ||
954 | + { | ||
955 | + if (dump_file) | ||
956 | + fprintf (dump_file, "extension at uid=%d ignored\n", | ||
957 | + INSN_UID (insn)); | ||
958 | + num_cand_ignored++; | ||
959 | + continue; | ||
960 | + } | ||
961 | + /* We don't consider certain sequences that are picked up by | ||
962 | + insn selection. */ | ||
963 | + if (NEXT_INSN (insn) | ||
964 | + && ignore_extension_next_p (insn, NEXT_INSN (insn))) | ||
965 | + { | ||
966 | + if (dump_file) | ||
967 | + fprintf (dump_file, "extension at uid=%d ignored\n", | ||
968 | + INSN_UID (insn)); | ||
969 | + num_cand_ignored++; | ||
970 | + continue; | ||
971 | + } | ||
972 | + | ||
973 | + /* Only looking at sign extensions to DImode, SImode, or HImode */ | ||
974 | + if (GET_MODE_BITSIZE (SImode) != preserved_size | ||
975 | + && GET_MODE_BITSIZE (HImode) != preserved_size | ||
976 | + && GET_MODE_BITSIZE (QImode) != preserved_size) | ||
977 | + continue; | ||
978 | + | ||
979 | + extrec = (ext_record_t) xmalloc (sizeof (struct ext_record)); | ||
980 | + extrec->ext = insn; | ||
981 | + extrec->ext_uses = NULL; | ||
982 | + extrec->ext_updates = NULL; | ||
983 | + VEC_safe_push (ext_record_t, heap, extensions, extrec); | ||
984 | + num_cand++; | ||
985 | + } | ||
986 | + } | ||
987 | + | ||
988 | + if (dump_file) | ||
989 | + { | ||
990 | + if (!VEC_empty (ext_record_t, extensions)) | ||
991 | + fprintf (dump_file, "\n"); | ||
992 | + else | ||
993 | + fprintf (dump_file, "no extensions found.\n"); | ||
994 | + } | ||
995 | + | ||
996 | + return !VEC_empty (ext_record_t, extensions); | ||
997 | +} | ||
998 | + | ||
999 | +/* Return true if the rtx mode is a supported mode for | ||
1000 | + this optimization, false otherwise. */ | ||
1001 | + | ||
1002 | +static bool | ||
1003 | +mode_supported_p (rtx exp) | ||
1004 | +{ | ||
1005 | + if (GET_MODE (exp) != QImode | ||
1006 | + && GET_MODE (exp) != HImode | ||
1007 | + && GET_MODE (exp) != SImode | ||
1008 | + && GET_MODE (exp) != DImode | ||
1009 | + && GET_MODE (exp) != CCmode | ||
1010 | + && GET_MODE (exp) != CCUNSmode) | ||
1011 | + return false; | ||
1012 | + | ||
1013 | + return true; | ||
1014 | +} | ||
1015 | + | ||
1016 | +/* Return true if the rtx is a function return expr, false otherwise */ | ||
1017 | + | ||
1018 | +static bool | ||
1019 | +return_val_p (rtx dest) | ||
1020 | +{ | ||
1021 | + if ((REG_P (dest) || GET_CODE (dest) == PARALLEL) && | ||
1022 | + REG_FUNCTION_VALUE_P (dest)) | ||
1023 | + { | ||
1024 | + return true; | ||
1025 | + } | ||
1026 | + return false; | ||
1027 | +} | ||
1028 | + | ||
1029 | + | ||
1030 | +/* A 'for_each_rtx' callback returning 1 if the rtx is a | ||
1031 | + REG or SUBREG rtx. The first matching rtx found stops the | ||
1032 | + rtx traversal. */ | ||
1033 | + | ||
1034 | +static int | ||
1035 | +reg_or_subreg_rtx (rtx * x, void *data) | ||
1036 | +{ | ||
1037 | + regspec_cb_data_t *ldata = (regspec_cb_data_t *) data; | ||
1038 | + | ||
1039 | + if (REG_P (*x)) | ||
1040 | + { | ||
1041 | + ldata->exp = *x; | ||
1042 | + return 1; | ||
1043 | + } | ||
1044 | + | ||
1045 | + if (GET_CODE (*x) == SUBREG) | ||
1046 | + { | ||
1047 | + ldata->exp = SUBREG_REG (*x); | ||
1048 | + return 1; | ||
1049 | + } | ||
1050 | + | ||
1051 | + return 0; | ||
1052 | +} | ||
1053 | + | ||
1054 | +/* A 'for_each_rtx' callback returning 1 if the rtx is a | ||
1055 | + REG or SUBREG rtx whose register number is that passed | ||
1056 | + in the data parameter. Data parameter's rtx value is | ||
1057 | + set to the matching rtx if found. */ | ||
1058 | + | ||
1059 | +static int | ||
1060 | +reg_or_subreg_rtx_regno (rtx * x, void *data) | ||
1061 | +{ | ||
1062 | + regspec_cb_data_t *ldata = (regspec_cb_data_t *) data; | ||
1063 | + | ||
1064 | + if (REG_P (*x) && (REGNO (*x) == ldata->regno)) | ||
1065 | + { | ||
1066 | + ldata->exp = *x; | ||
1067 | + return 1; | ||
1068 | + } | ||
1069 | + if (GET_CODE (*x) == SUBREG && (REGNO (SUBREG_REG (*x)) == ldata->regno)) | ||
1070 | + { | ||
1071 | + ldata->exp = SUBREG_REG (*x); | ||
1072 | + return 1; | ||
1073 | + } | ||
1074 | + return 0; | ||
1075 | +} | ||
1076 | + | ||
1077 | +/* Callback that counts the number of register operands | ||
1078 | + in an expression. Return 0 to allow all rtxs to be | ||
1079 | + traversed. */ | ||
1080 | + | ||
1081 | +static int | ||
1082 | +count_reg_operands (rtx * x, void *data) | ||
1083 | +{ | ||
1084 | + regspec_cb_data_t *ldata = (regspec_cb_data_t *) data; | ||
1085 | + | ||
1086 | + if (register_exp (*x) != NULL) | ||
1087 | + { | ||
1088 | + ldata->regno++; | ||
1089 | + } | ||
1090 | + return 0; | ||
1091 | +} | ||
1092 | + | ||
1093 | +/* Count the number of register operands in an expression. | ||
1094 | + We use the regspec_cb_data_t regno field as the number | ||
1095 | + of register operands we found in an expression. */ | ||
1096 | + | ||
1097 | +static int | ||
1098 | +num_reg_operands (rtx x) | ||
1099 | +{ | ||
1100 | + int rv; | ||
1101 | + regspec_cb_data_t data; | ||
1102 | + data.regno = 0; | ||
1103 | + data.exp = NULL_RTX; | ||
1104 | + | ||
1105 | + if ((rv = for_each_rtx (&x, count_reg_operands, (void *) &data)) == 0) | ||
1106 | + return (data.regno); /* contains the count */ | ||
1107 | + else | ||
1108 | + return 0; | ||
1109 | +} | ||
1110 | + | ||
1111 | +/* Find the SUBREG or REG rtx corresponding to regno in the given rtx. | ||
1112 | + Return NULL_RTX if the regno rtx is not found. */ | ||
1113 | + | ||
1114 | +static rtx | ||
1115 | +find_regspec_regno (unsigned int regno, rtx x) | ||
1116 | +{ | ||
1117 | + int rv; | ||
1118 | + regspec_cb_data_t data; | ||
1119 | + data.regno = regno; | ||
1120 | + data.exp = NULL_RTX; | ||
1121 | + | ||
1122 | + if ((rv = for_each_rtx (&x, reg_or_subreg_rtx_regno, (void *) &data)) != 0) | ||
1123 | + return (data.exp); | ||
1124 | + else | ||
1125 | + return NULL_RTX; | ||
1126 | +} | ||
1127 | + | ||
1128 | +/* Find a REG or SUBREG rtx, starting at expr x. | ||
1129 | + Return NULL_RTX if no REG or SUBREG rtx is found. | ||
1130 | + If found, the rtx returned is a REG (not SUBREG) */ | ||
1131 | + | ||
1132 | +static rtx | ||
1133 | +find_regspec (rtx x) | ||
1134 | +{ | ||
1135 | + int rv; | ||
1136 | + regspec_cb_data_t data; | ||
1137 | + data.regno = -1; /* not used */ | ||
1138 | + data.exp = NULL_RTX; | ||
1139 | + | ||
1140 | + if ((rv = for_each_rtx (&x, reg_or_subreg_rtx, (void *) &data)) != 0) | ||
1141 | + return (data.exp); | ||
1142 | + else | ||
1143 | + return NULL_RTX; | ||
1144 | +} | ||
1145 | + | ||
1146 | +/* Return true if the expression defines single register, regno. */ | ||
1147 | + | ||
1148 | +static bool | ||
1149 | +expr_defines_regno_p (rtx insn, unsigned int regno) | ||
1150 | +{ | ||
1151 | + rtx reg; | ||
1152 | + if (GET_CODE (insn) == SET) | ||
1153 | + { | ||
1154 | + reg = SET_DEST (insn); | ||
1155 | + if (find_regspec_regno (regno, reg) != NULL_RTX) | ||
1156 | + return true; | ||
1157 | + } | ||
1158 | + return false; | ||
1159 | +} | ||
1160 | + | ||
1161 | +/* Return true if the insn defines a single register, regno. | ||
1162 | + Return false otherwise */ | ||
1163 | + | ||
1164 | +static bool | ||
1165 | +defines_regno_p (rtx insn_insn, unsigned int regno, int indent) | ||
1166 | +{ | ||
1167 | + extelim_uid_t uid = INSN_UID (insn_insn); | ||
1168 | + df_ref *p_def; | ||
1169 | + | ||
1170 | + /* Get the operands defined */ | ||
1171 | + p_def = DF_INSN_UID_DEFS (uid); | ||
1172 | + | ||
1173 | + if (!p_def) | ||
1174 | + return false; | ||
1175 | + | ||
1176 | + if (*(p_def + 1) != NULL) | ||
1177 | + { | ||
1178 | + if (dump_file) | ||
1179 | + fprintf (dump_file, "%*suid=%d defines multiple registers\n", | ||
1180 | + indent, " ", uid); | ||
1181 | + return false; | ||
1182 | + } | ||
1183 | + | ||
1184 | + if (DF_REF_REGNO (*p_def) != regno) | ||
1185 | + { | ||
1186 | + if (dump_file) | ||
1187 | + fprintf (dump_file, "%*suid=%d defines does not define %d\n", | ||
1188 | + indent, " ", uid, regno); | ||
1189 | + return false; | ||
1190 | + } | ||
1191 | + | ||
1192 | + return true; | ||
1193 | +} | ||
1194 | + | ||
1195 | +/* The operand is already extended and the extension is compatible with | ||
1196 | + the originating extension with respect to type and size. | ||
1197 | + E.g. zero_extend:HI meets and AND r,#0xffff. Another example | ||
1198 | + is LSHIFT:SI left or right and zero_extend:SI, because the | ||
1199 | + instruction selected is rlwinm and clears the upper 32 bits. | ||
1200 | + Other examples in the code. Return true if a compatible extension | ||
1201 | + is found, false otherwise. */ | ||
1202 | + | ||
1203 | +static bool | ||
1204 | +operand_is_extended (rtx dest, rtx srcexp, int indent) | ||
1205 | +{ | ||
1206 | + /* Output of a CALL is already extended. | ||
1207 | + To ensure that the return value is not modified by the extend, | ||
1208 | + the extend from mode size must be at least the size of the CALL output. | ||
1209 | + Example - this is redundant since output of CALL is extended. | ||
1210 | + X:SI = CALL ... | ||
1211 | + Y:DI = sign_extend:DI (X:SI) */ | ||
1212 | + if (GET_CODE (srcexp) == CALL | ||
1213 | + && (GET_MODE_BITSIZE (ext_from_mode)) >= | ||
1214 | + GET_MODE_BITSIZE (GET_MODE (dest))) | ||
1215 | + { | ||
1216 | + if (dump_file) | ||
1217 | + fprintf (dump_file, | ||
1218 | + "%*s...is extended already (CALL insn output)\n", indent, | ||
1219 | + " "); | ||
1220 | + return true; | ||
1221 | + } | ||
1222 | + | ||
1223 | + /* Output is load immediate or load constant */ | ||
1224 | + if (CONST_INT_P (srcexp)) | ||
1225 | + { | ||
1226 | + bool is_extended; | ||
1227 | + if (ext_from_mode == QImode && (UINTVAL (srcexp) <= 0xff)) | ||
1228 | + is_extended = true; | ||
1229 | + else if (ext_from_mode == HImode && (UINTVAL (srcexp) <= 0xffff)) | ||
1230 | + is_extended = true; | ||
1231 | + else if (ext_from_mode == SImode && (UINTVAL (srcexp) <= 0xffffffff)) | ||
1232 | + is_extended = true; | ||
1233 | + else | ||
1234 | + is_extended = false; | ||
1235 | + | ||
1236 | + if (is_extended) | ||
1237 | + { | ||
1238 | + if (dump_file) | ||
1239 | + fprintf (dump_file, | ||
1240 | + "%*s... is extended already (CONST_INT load)\n", indent, | ||
1241 | + " "); | ||
1242 | + return true; | ||
1243 | + } | ||
1244 | + } | ||
1245 | + | ||
1246 | + /* Sign extension of the same type as the originating extension. | ||
1247 | + Here the candidate defines the register used in the originating extension. | ||
1248 | + The originating extension will be replaced by a copy if it is found to be | ||
1249 | + redundant with respect to the candidate extension. | ||
1250 | + The candidate (this extension dest,src) must write the at least the same bits as the | ||
1251 | + originating extension in order to be redundant. So, we follow these rules: | ||
1252 | + | ||
1253 | + cand_to_mode == machine mode of the destination for this candidate extension | ||
1254 | + cand_from_mode == machine mode of the source for this candidate extension | ||
1255 | + ext_to_mode == machine mode of the originating extension output | ||
1256 | + ext_from_mode == machine mode of the originating extension input | ||
1257 | + | ||
1258 | + SIZE(cand_to_mode) >= SIZE(extend_to_mode) && SIZE(cand_from_mode) <= SIZE(extend_from_mode) | ||
1259 | + | ||
1260 | + Example 1: | ||
1261 | + Candidate (HI->SI extension) | ||
1262 | + DI SI HI QI 0 | ||
1263 | + | |<---| | | | ||
1264 | + | ||
1265 | + Originating (SI->DI) | ||
1266 | + DI SI HI QI 0 | ||
1267 | + |<-------| | | | | ||
1268 | + | ||
1269 | + Not redundant, candidate does not cover the original bits: | ||
1270 | + SIZE(cand_to_mode)[SI] !>= SIZE(extend_to_mode)[DI] | ||
1271 | + | ||
1272 | + Example 2: | ||
1273 | + Candidate (QI->DI extension) | ||
1274 | + DI SI HI QI 0 | ||
1275 | + |<-------|----|--| | | ||
1276 | + | ||
1277 | + Originating (HI->SI) | ||
1278 | + DI SI HI QI 0 | ||
1279 | + | |<---| | | | ||
1280 | + | ||
1281 | + Redundant, candidate covers the original bits: | ||
1282 | + SIZE(cand_to_mode) [DI] >= SIZE(extend_to_mode) [SI] | ||
1283 | + AND | ||
1284 | + SIZE(cand_from_mode) [QI] <= SIZE(extend_from_mode) [HI] | ||
1285 | + */ | ||
1286 | + if (GET_CODE (srcexp) == ext_code) | ||
1287 | + { | ||
1288 | + enum machine_mode cand_from_mode = GET_MODE (XEXP (srcexp, 0)); | ||
1289 | + enum machine_mode cand_to_mode = GET_MODE (dest); | ||
1290 | + if ((GET_MODE_BITSIZE (cand_to_mode) >= GET_MODE_BITSIZE (ext_to_mode)) | ||
1291 | + && (GET_MODE_BITSIZE (cand_from_mode) <= | ||
1292 | + GET_MODE_BITSIZE (ext_from_mode))) | ||
1293 | + { | ||
1294 | + if (dump_file) | ||
1295 | + fprintf (dump_file, | ||
1296 | + "%*s...is already extended (redundant extension)\n", | ||
1297 | + indent, " "); | ||
1298 | + return true; | ||
1299 | + } | ||
1300 | + } | ||
1301 | + | ||
1302 | + /* Encountered an insn with the same effect as extension, e.g. | ||
1303 | + AND (regspec) (const_int). E.g. AND (reg:SI) (0x7fff) is equivalent | ||
1304 | + to ZERO_EXTEND:DI (reg:HI) or SIGN_EXTEND:DI (reg:HI). The code selection | ||
1305 | + for AND zero extends the entire register, so we don't have to | ||
1306 | + check that srcexp extends to at least ext_to_mode size. */ | ||
1307 | + if ((GET_CODE (srcexp) == AND) && CONST_INT_P (XEXP (srcexp, 1))) | ||
1308 | + { | ||
1309 | + if (ext_from_mode == QImode && (UINTVAL (XEXP (srcexp, 1)) <= 0x7f)) | ||
1310 | + return true; | ||
1311 | + else if (ext_from_mode == HImode | ||
1312 | + && (UINTVAL (XEXP (srcexp, 1)) <= 0x7fff)) | ||
1313 | + return true; | ||
1314 | + else if (ext_from_mode == SImode | ||
1315 | + && (UINTVAL (XEXP (srcexp, 1)) <= 0x7fffffff)) | ||
1316 | + return true; | ||
1317 | + } | ||
1318 | + | ||
1319 | + return false; | ||
1320 | +} | ||
1321 | + | ||
1322 | +/* Determine if the operation allows us to continue the propagation. | ||
1323 | + We kill the propagation for all operations except copy. This | ||
1324 | + ensures that the extended operand that we may find eventually | ||
1325 | + is not modified by insns in the def-use chain. It's harsh, | ||
1326 | + but it's safest eliminate all but the most benign (copy) operations | ||
1327 | + in the propagation chain. */ | ||
1328 | + | ||
1329 | +static bool | ||
1330 | +continue_def_propagation (rtx dest, rtx srcexp, rtx src_operand, int indent) | ||
1331 | +{ | ||
1332 | + /* Only continue if its a copy -- that is, the srcexp is a register expression */ | ||
1333 | + if ( register_exp (srcexp) ) | ||
1334 | + return true; | ||
1335 | + | ||
1336 | + return false; | ||
1337 | +} | ||
1338 | + | ||
1339 | +/* Helper for insn_def_analysis_result. | ||
1340 | + The register operand, src is set here. Recall we | ||
1341 | + can only handle one register operand in the src expression. | ||
1342 | + We one of 3 states: | ||
1343 | + 1) Determine the operand is extended, ...DEF_EXTENDED returned. | ||
1344 | + 2) Determine the propagation can continue, ...DEF_CONTINUE_RECURSION returned. | ||
1345 | + 3) Otherwise, ...DEF_STOP_RECURSION is returned. */ | ||
1346 | +static enum insn_def_results | ||
1347 | +insn_def_analysis_result_1 (rtx insn, bool treat_as_copy, | ||
1348 | + unsigned int regno_def ATTRIBUTE_UNUSED, | ||
1349 | + rtx * src, int indent) | ||
1350 | +{ | ||
1351 | + rtx dest, srcexp; | ||
1352 | + int num_operands; | ||
1353 | + | ||
1354 | + /* Insn has to be an expression we can analyze */ | ||
1355 | + if (GET_CODE (insn) != SET) | ||
1356 | + { | ||
1357 | + if (dump_file) | ||
1358 | + fprintf (dump_file, "%*s...is not a SET expression\n", indent, " "); | ||
1359 | + return EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION; | ||
1360 | + } | ||
1361 | + dest = SET_DEST (insn); | ||
1362 | + srcexp = SET_SRC (insn); | ||
1363 | + | ||
1364 | + /* Dest must be a reg, not expression */ | ||
1365 | + if (!REG_P (dest)) | ||
1366 | + { | ||
1367 | + if (dump_file) | ||
1368 | + fprintf (dump_file, | ||
1369 | + "%*s...dest is not a simple register\n", indent, " "); | ||
1370 | + return EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION; | ||
1371 | + } | ||
1372 | + | ||
1373 | + /* First check whether the operand is extended already. If so, | ||
1374 | + we can leave immediately successfully. */ | ||
1375 | + if (operand_is_extended (dest, srcexp, indent) && !treat_as_copy) | ||
1376 | + return (EXTELIM_ANALYSIS_RESULT_DEF_EXTENDED); | ||
1377 | + | ||
1378 | + | ||
1379 | + /* Failing to determine that the operand is already extended, | ||
1380 | + we have to validate that we have register operands to propagate. */ | ||
1381 | + num_operands = num_reg_operands (srcexp); | ||
1382 | + | ||
1383 | + /* At least one register operand required for propagation. */ | ||
1384 | + if (num_operands == 0) | ||
1385 | + { | ||
1386 | + if (dump_file) | ||
1387 | + fprintf (dump_file, | ||
1388 | + "%*s...no register operands in RHS\n", indent, " "); | ||
1389 | + return EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION; | ||
1390 | + } | ||
1391 | + | ||
1392 | + /* Only one register operand is allowed in the RHS since we can't | ||
1393 | + can't propagate more than one register. */ | ||
1394 | + if (num_operands > 1) | ||
1395 | + { | ||
1396 | + if (dump_file) | ||
1397 | + fprintf (dump_file, | ||
1398 | + "%*s...found multiple register operands in RHS\n", indent, | ||
1399 | + " "); | ||
1400 | + return EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION; | ||
1401 | + } | ||
1402 | + | ||
1403 | + /* Find the used operand in the src expression */ | ||
1404 | + *src = find_regspec (srcexp); | ||
1405 | + if (*src == NULL_RTX || !mode_supported_p (*src)) | ||
1406 | + { | ||
1407 | + if (dump_file) | ||
1408 | + fprintf (dump_file, | ||
1409 | + "%*s...src operand reg=%d cannot be found or is unsupported mode\n", | ||
1410 | + indent, " ", regno_def); | ||
1411 | + return EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION; | ||
1412 | + } | ||
1413 | + | ||
1414 | + /* This is an extension, but it is previously marked to be transformed to a copy. | ||
1415 | + We just treat it as a copy even though it hasn't been transformed yet. So | ||
1416 | + continue the propagation. */ | ||
1417 | + if (treat_as_copy) | ||
1418 | + { | ||
1419 | + if (dump_file) | ||
1420 | + fprintf (dump_file, | ||
1421 | + "%*s...%s is treated as a copy (marked for replace)\n", | ||
1422 | + indent, " ", GET_RTX_NAME (GET_CODE (srcexp))); | ||
1423 | + return (EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION); | ||
1424 | + } | ||
1425 | + | ||
1426 | + /* Validate that it's ok to continue propagation with this operand. */ | ||
1427 | + if (continue_def_propagation (dest, srcexp, *src, indent)) | ||
1428 | + return (EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION); | ||
1429 | + | ||
1430 | + /* Else we default to halting the search for a redundant extension */ | ||
1431 | + return (EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION); | ||
1432 | +} | ||
1433 | + | ||
1434 | +/* Determine if the insn extends it's destination register in | ||
1435 | + a manner such that the original extension is redundant. */ | ||
1436 | + | ||
1437 | +static enum insn_def_results | ||
1438 | +insn_def_analysis_result (rtx insn_insn, unsigned int regno_def, rtx * src, | ||
1439 | + int indent) | ||
1440 | +{ | ||
1441 | + bool treat_as_copy = false; | ||
1442 | + | ||
1443 | + /* Insn must only define one output */ | ||
1444 | + if (!defines_regno_p (insn_insn, regno_def, indent)) | ||
1445 | + { | ||
1446 | + if (dump_file) | ||
1447 | + fprintf (dump_file, | ||
1448 | + "%*s...defines more than 1 output\n", indent, " "); | ||
1449 | + return EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION; | ||
1450 | + } | ||
1451 | + | ||
1452 | + /* We want to treat this extension as a copy and continue propagation. | ||
1453 | + Otherwise, it would be detected again as redundant. */ | ||
1454 | + if (insn_flag_p (EXTELIM_REPLACE_COPY, INSN_UID (insn_insn))) | ||
1455 | + { | ||
1456 | + if (dump_file) | ||
1457 | + fprintf (dump_file, | ||
1458 | + "%*suse at uid=%d is marked to transform to copy\n", indent, | ||
1459 | + " ", INSN_UID (insn_insn)); | ||
1460 | + treat_as_copy = true; | ||
1461 | + } | ||
1462 | + | ||
1463 | + /* Do the analysis */ | ||
1464 | + return (insn_def_analysis_result_1 | ||
1465 | + (PATTERN (insn_insn), treat_as_copy, regno_def, src, indent)); | ||
1466 | +} | ||
1467 | + | ||
1468 | +/* Analyze each of the expressions in a PARALLEL expression. As each of | ||
1469 | + the expressions may yield a different state, select the most conservative | ||
1470 | + state to return. */ | ||
1471 | + | ||
1472 | +static enum insn_def_results | ||
1473 | +insn_def_analysis_2 (rtx insn_def, unsigned int regno_def, rtx * src, | ||
1474 | + int indent) | ||
1475 | +{ | ||
1476 | + int i; | ||
1477 | + rtx insn = PATTERN (insn_def); | ||
1478 | + enum insn_def_results action; | ||
1479 | + enum insn_def_results return_action = | ||
1480 | + EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION; | ||
1481 | + | ||
1482 | + gcc_assert (GET_CODE (insn) == PARALLEL); | ||
1483 | + | ||
1484 | + for (i = XVECLEN (insn, 0) - 1; i >= 0; i--) | ||
1485 | + { | ||
1486 | + rtx body = XVECEXP (insn, 0, i); | ||
1487 | + /* Only act on the expressions that define regno_def */ | ||
1488 | + if (!expr_defines_regno_p (body, regno_def)) | ||
1489 | + continue; | ||
1490 | + /* Determine the next action */ | ||
1491 | + action = insn_def_analysis_result_1 (body, false /* treat_as_copy */ , | ||
1492 | + regno_def, src, indent); | ||
1493 | + /* The result of this expression stops the recursion, i.e. no | ||
1494 | + longer reasonable to continue looking at further recursion. */ | ||
1495 | + if (action == EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION) | ||
1496 | + return action; | ||
1497 | + /* Only return EXTENDED if there are no other different actions | ||
1498 | + in the series. Otherwise, CONTINUE_RECURSION is returned. */ | ||
1499 | + if (action == EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION) | ||
1500 | + return_action = action; | ||
1501 | + else if (return_action == | ||
1502 | + EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION) | ||
1503 | + return_action = EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION; | ||
1504 | + else | ||
1505 | + return_action = action; | ||
1506 | + } | ||
1507 | + return (return_action); | ||
1508 | +} | ||
1509 | + | ||
1510 | +/* Helper 1 for insn_def_analysis */ | ||
1511 | + | ||
1512 | +static enum insn_def_results | ||
1513 | +insn_def_analysis_1 (rtx insn_def, unsigned int regno_def, rtx * src, | ||
1514 | + int indent) | ||
1515 | +{ | ||
1516 | + rtx def = PATTERN (insn_def); | ||
1517 | + enum insn_def_results action; | ||
1518 | + | ||
1519 | + switch (GET_CODE (def)) | ||
1520 | + { | ||
1521 | + case PARALLEL: | ||
1522 | + action = insn_def_analysis_2 (insn_def, regno_def, src, indent); | ||
1523 | + break; | ||
1524 | + default: | ||
1525 | + action = insn_def_analysis_result (insn_def, regno_def, src, indent); | ||
1526 | + break; | ||
1527 | + } | ||
1528 | + return action; | ||
1529 | +} | ||
1530 | + | ||
1531 | +/* We look at the definition of a register that is either the | ||
1532 | + sign or zero extend source register or a definition that that | ||
1533 | + has been propagated to here via analyze_ext_def. The objective | ||
1534 | + is to determine, by looking at the operation and operands, whether | ||
1535 | + the register is sign/zero extended by virtue of the operation and/or | ||
1536 | + operands. If so, the original extension is redundant. | ||
1537 | + The function returns one of 3 possible states after analyzing the | ||
1538 | + insn: | ||
1539 | + 1. EXTELIM_ANALYSIS_RESULT_DEF_EXTENDED - we determined that the | ||
1540 | + insn does indeed extend the original source extension register. | ||
1541 | + analyze_ext_def returns FALSE, therefore, ending the recursion | ||
1542 | + and propagation. | ||
1543 | + 2. EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION - we determined that | ||
1544 | + the insn does not meet the criteria to continue the recursive search. | ||
1545 | + Some conditions causing this may be multiple operands defining this | ||
1546 | + register (we only propagate on a single input operand) or the insn | ||
1547 | + defines more than one output or the operation does not allow | ||
1548 | + a previous extension to propagate, e.g. an arithmetic shift on | ||
1549 | + a SI value clears the upper bits using rlwinm. MUL, DIV, MOD | ||
1550 | + stop recursion because the result is longer than the input size, | ||
1551 | + thus impacting the possible previous extension. | ||
1552 | + 3. EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION - we found an | ||
1553 | + operation with one register operand and the operation will not | ||
1554 | + affect a previous extension if one exists. ADD, SUB are examples. | ||
1555 | + We continue looking up the chain at the definition of the operand | ||
1556 | + for an extended result. | ||
1557 | + If we run into a previous extension marked for replacement during | ||
1558 | + recursion, we treat it as a copy (CONTINUE_RECURSION since the | ||
1559 | + extension is preserved by the copy). */ | ||
1560 | + | ||
1561 | +static enum insn_def_results | ||
1562 | +insn_def_analysis (rtx insn_def, unsigned int regno_def, rtx * src, | ||
1563 | + int indent) | ||
1564 | +{ | ||
1565 | + return (insn_def_analysis_1 (insn_def, regno_def, src, indent)); | ||
1566 | +} | ||
1567 | + | ||
1568 | +/* Analyze the insn defining the source of the sign extension. | ||
1569 | + If it can be determined that the definition is already | ||
1570 | + sign extended, return false. Otherwise, return true if | ||
1571 | + extension is needed. */ | ||
1572 | + | ||
1573 | +static bool | ||
1574 | +analyze_ext_def (rtx insn_def, unsigned int regno_def, int indent) | ||
1575 | +{ | ||
1576 | + extelim_uid_t uid; | ||
1577 | + rtx def = PATTERN (insn_def); | ||
1578 | + rtx src; | ||
1579 | + df_ref df_def, *p_use; | ||
1580 | + bool ext_needed, indent_once; | ||
1581 | + struct df_link *link; | ||
1582 | + enum insn_def_results analysis_result; | ||
1583 | + | ||
1584 | + gcc_assert (def != NULL); | ||
1585 | + | ||
1586 | + uid = INSN_UID (insn_def); | ||
1587 | + | ||
1588 | + /* If we seen the originating extension again, return false (ext not needed) */ | ||
1589 | + if (current_ext_record->ext == insn_def) | ||
1590 | + { | ||
1591 | + if (dump_file) | ||
1592 | + fprintf (dump_file, | ||
1593 | + "%*sdef at uid=%d is original extension\n", indent, " ", uid); | ||
1594 | + return false; | ||
1595 | + } | ||
1596 | + | ||
1597 | + /* The recursion has to definitively end with an operand being | ||
1598 | + extended (and compatible with the originating extension). If | ||
1599 | + we see the insn again, this could return a faulty positive (false), | ||
1600 | + so we return true here instead of false. See pr43017 (-funroll-loops) | ||
1601 | + as an example. */ | ||
1602 | + if (insn_flag_p (EXTELIM_SEEN, uid)) | ||
1603 | + { | ||
1604 | + if (dump_file) | ||
1605 | + fprintf (dump_file, | ||
1606 | + "%*sdef at uid=%d is visited already\n", indent, " ", uid); | ||
1607 | + return true; | ||
1608 | + } | ||
1609 | + | ||
1610 | + /* Mark this insn as seen */ | ||
1611 | + insn_flag_set (EXTELIM_SEEN, uid); | ||
1612 | + | ||
1613 | + analysis_result = insn_def_analysis (insn_def, regno_def, &src, indent); | ||
1614 | + switch (analysis_result) | ||
1615 | + { | ||
1616 | + /* We know conclusively that the register defined in this expression | ||
1617 | + is already extended. */ | ||
1618 | + case EXTELIM_ANALYSIS_RESULT_DEF_EXTENDED: | ||
1619 | + if (dump_file) | ||
1620 | + fprintf (dump_file, "%*sdef at uid=%d is extended\n", indent, " ", | ||
1621 | + uid); | ||
1622 | + return false; | ||
1623 | + break; | ||
1624 | + /* We know conclusively that we cannot continue the recursion. Perhaps | ||
1625 | + the expression defines multiple registers, etc. */ | ||
1626 | + case EXTELIM_ANALYSIS_RESULT_DEF_STOP_RECURSION: | ||
1627 | + if (dump_file) | ||
1628 | + fprintf (dump_file, "%*sdef at uid=%d cannot be propagated\n", indent, | ||
1629 | + " ", uid); | ||
1630 | + return true; | ||
1631 | + break; | ||
1632 | + /* Continue to look at the operands of this expression. They may be extended | ||
1633 | + already. */ | ||
1634 | + case EXTELIM_ANALYSIS_RESULT_DEF_CONTINUE_RECURSION: | ||
1635 | + break; | ||
1636 | + default: | ||
1637 | + gcc_unreachable (); | ||
1638 | + } | ||
1639 | + | ||
1640 | + /* This is the operand for which we want to find definitions. There should | ||
1641 | + only be one operand as we have previously checked for operations with only | ||
1642 | + one register operand as the src previously. */ | ||
1643 | + p_use = DF_INSN_UID_USES (uid); | ||
1644 | + gcc_assert (p_use != NULL); | ||
1645 | + | ||
1646 | + /* Make sure that this use is the one returned in src. Otherwise we simply | ||
1647 | + stop the propagation. Note the DF_INSN_UID_USES works at the insn | ||
1648 | + level, so a PARALLEL pattern may return many uses, hence the need | ||
1649 | + to validate the correct use here. */ | ||
1650 | + if ((*p_use == NULL) || (DF_REF_REGNO (*p_use) != REGNO (src))) | ||
1651 | + return true; | ||
1652 | + | ||
1653 | + ext_needed = true; | ||
1654 | + indent_once = true; | ||
1655 | + for (link = DF_REF_CHAIN (*p_use); link; link = link->next) | ||
1656 | + { | ||
1657 | + rtx insn_def; | ||
1658 | + df_def = link->ref; | ||
1659 | + if (!df_def) | ||
1660 | + continue; | ||
1661 | + /* Link must be to a definition of the use */ | ||
1662 | + if (!DF_REF_REG_DEF_P (df_def)) | ||
1663 | + continue; | ||
1664 | + /* Ignore ARTIFICIAL defs */ | ||
1665 | + if (DF_REF_IS_ARTIFICIAL (df_def)) | ||
1666 | + continue; | ||
1667 | + insn_def = DF_REF_INSN (df_def); | ||
1668 | + /* Don't consider debug_insns */ | ||
1669 | + if (!NONDEBUG_INSN_P (insn_def)) | ||
1670 | + continue; | ||
1671 | + if (dump_file) | ||
1672 | + fprintf (dump_file, | ||
1673 | + "%*sdef of reg=%d at uid=%d\n", indent, " ", | ||
1674 | + DF_REF_REGNO (df_def), INSN_UID (insn_def)); | ||
1675 | + /* Set indent for dump formatting */ | ||
1676 | + if (indent_once) | ||
1677 | + { | ||
1678 | + ++indent; | ||
1679 | + indent_once = false; | ||
1680 | + } | ||
1681 | + ext_needed = analyze_ext_def (insn_def, DF_REF_REGNO (df_def), indent); | ||
1682 | + if (ext_needed) | ||
1683 | + break; | ||
1684 | + } | ||
1685 | + | ||
1686 | + if (dump_file) | ||
1687 | + fprintf (dump_file, | ||
1688 | + "%*sext %s needed\n", indent, " ", ext_needed ? "" : "not"); | ||
1689 | + | ||
1690 | + return ext_needed; | ||
1691 | +} | ||
1692 | + | ||
1693 | +/* Determine whether the expression needs to be saved for this extension. | ||
1694 | + The expression will be updated in some way if the extension is ultimately | ||
1695 | + eliminated. */ | ||
1696 | + | ||
1697 | +static bool | ||
1698 | +exp_needs_update_p (rtx exp) | ||
1699 | +{ | ||
1700 | + if (GET_CODE (exp) == SUBREG | ||
1701 | + && (SUBREG_PROMOTED_VAR_P (exp))) | ||
1702 | + { | ||
1703 | + return true; | ||
1704 | + } | ||
1705 | + return false; | ||
1706 | +} | ||
1707 | + | ||
1708 | +/* Some expressions may need to be updated if the originating extension | ||
1709 | + is eliminated. For example, SUBREG_PROMOTED flags on uses are no longer | ||
1710 | + valid if the extension is eliminated. Save the expression here. */ | ||
1711 | + | ||
1712 | +static void | ||
1713 | +save_ext_update (ext_record_t extrec, rtx exp) | ||
1714 | +{ | ||
1715 | + /* Save this expression to be updated if the extension is eliminated. */ | ||
1716 | + VEC_safe_push (rtx, heap, extrec->ext_updates, exp); | ||
1717 | +} | ||
1718 | + | ||
1719 | +/* Check a compare operation to determine whether the operands | ||
1720 | + of the compare use the upper bits of the extension. Return | ||
1721 | + true if the upper bits are not relevant in the compare, false | ||
1722 | + otherwise. */ | ||
1723 | + | ||
1724 | +static bool | ||
1725 | +check_compare (rtx dest, rtx src) | ||
1726 | +{ | ||
1727 | + /* Detect | ||
1728 | + (set (reg:CC r0) (compare:CC (REGSPEC) (REGSPEC))) | ||
1729 | + or | ||
1730 | + (set (reg:CC r0) (compare:CC (REGSPEC) (CONST))) | ||
1731 | + where REGSPEC is (reg:mm r) or (subreg:mm (reg:MM r) n) | ||
1732 | + CONST is a constant integer. | ||
1733 | + The mode size of compare ops must be less than the | ||
1734 | + mode of the original extension for the upper bits to | ||
1735 | + be irrelevant. | ||
1736 | + An exception is made for mode sizes less than a word size. | ||
1737 | + For our targets, there is no 'cmph' insn, so we bail out | ||
1738 | + if we see a comparison of sizes less than a word (SI). */ | ||
1739 | + if (REG_P (dest) | ||
1740 | + && (GET_MODE (dest) == CCmode || GET_MODE (dest) == CCUNSmode) | ||
1741 | + && GET_CODE (src) == COMPARE | ||
1742 | + && (GET_MODE (src) == CCmode || GET_MODE (src) == CCUNSmode)) | ||
1743 | + { | ||
1744 | + rtx compare_op0 = XEXP (src, 0); | ||
1745 | + rtx compare_op1 = XEXP (src, 1); | ||
1746 | + | ||
1747 | + /* Check the first operand, op0, size. */ | ||
1748 | + if ((REG_P (compare_op0) || GET_CODE (compare_op0) == SUBREG) | ||
1749 | + && (GET_MODE_BITSIZE (GET_MODE (compare_op0)) <= | ||
1750 | + GET_MODE_BITSIZE (ext_from_mode))) | ||
1751 | + { | ||
1752 | + /* Half word compares and smaller are performed as word compares, so upper bits are used. */ | ||
1753 | + if (GET_MODE_BITSIZE (GET_MODE (compare_op0)) < SImode) | ||
1754 | + return false; | ||
1755 | + | ||
1756 | + /* Now check the other operand, op1. */ | ||
1757 | + if ((REG_P (compare_op1) || GET_CODE (compare_op1) == SUBREG) | ||
1758 | + && (GET_MODE_BITSIZE (GET_MODE (compare_op1)) <= | ||
1759 | + GET_MODE_BITSIZE (ext_from_mode))) | ||
1760 | + return true; | ||
1761 | + | ||
1762 | + /* Compare to constant, we know op0 already meets size constraints. */ | ||
1763 | + if (CONST_INT_P (compare_op1)) | ||
1764 | + return true; | ||
1765 | + } | ||
1766 | + } | ||
1767 | + return false; | ||
1768 | +} | ||
1769 | + | ||
1770 | +/* Determine condition a, whether the upper bits are relevant to the operation. | ||
1771 | + Return false if we prove the upper bits are not relevant in the operation, | ||
1772 | + true otherwise. */ | ||
1773 | + | ||
1774 | +static bool | ||
1775 | +operation_uses_upper_bits (rtx dest, rtx src, unsigned int regno_use, | ||
1776 | + int indent ATTRIBUTE_UNUSED) | ||
1777 | +{ | ||
1778 | + rtx regspec_src = find_regspec_regno (regno_use, src); | ||
1779 | + | ||
1780 | + if (check_compare (dest, src)) | ||
1781 | + return false; | ||
1782 | + | ||
1783 | + /* Store of regno to mem, size stored is the same or smaller than the extended from size */ | ||
1784 | + if (MEM_P (dest) | ||
1785 | + && (GET_MODE_BITSIZE (GET_MODE (dest)) <= | ||
1786 | + GET_MODE_BITSIZE (ext_from_mode)) | ||
1787 | + /* Ensure the used register is being stored and not used in another capacity, say, as a pointer. */ | ||
1788 | + && (regspec_src)) | ||
1789 | + return false; | ||
1790 | + | ||
1791 | + /* Operation operand size is the same or smaller than the extended from size */ | ||
1792 | + if (regspec_src) | ||
1793 | + { | ||
1794 | + if (GET_MODE_BITSIZE (GET_MODE (regspec_src)) <= | ||
1795 | + GET_MODE_BITSIZE (ext_from_mode)) | ||
1796 | + return false; | ||
1797 | + } | ||
1798 | + | ||
1799 | + /* Default to the safest result */ | ||
1800 | + return true; | ||
1801 | +} | ||
1802 | + | ||
1803 | +/* Determine if this insn also extends to the size or greater of the original extension. | ||
1804 | + Sign extend can propagate to zero extend and vice-versa because the upper bits | ||
1805 | + haven't affected the low bits up to now throughout the propagation. */ | ||
1806 | + | ||
1807 | +static bool | ||
1808 | +operation_extends_to_upper_bits_size (rtx src, int indent ATTRIBUTE_UNUSED) | ||
1809 | +{ | ||
1810 | + /* Sign extension of the same type as the originating extension. | ||
1811 | + Here the candidate uses the register defined by the originating extension. | ||
1812 | + If the candidate is found to be redundant, the originating extension is | ||
1813 | + replaced with a copy. | ||
1814 | + | ||
1815 | + We follow these rules: | ||
1816 | + | ||
1817 | + dest_mode == machine mode of the destination for this candidate extension | ||
1818 | + (it's the same mode as the src, e,g, reg:DI = sign_extend:DI ...) | ||
1819 | + src_mode == machine mode of the source for this candidate extension | ||
1820 | + (the mode of the used register, SI in this case, e.g. reg:DI = sign_extend:DI (subreg:SI (reg:DI)) | ||
1821 | + ext_to_mode == machine mode of the originating extension output | ||
1822 | + ext_from_mode == machine mode of the originating extension input | ||
1823 | + | ||
1824 | + SIZE(cand_from_mode) >= SIZE(extend_from_mode) && SIZE(cand_to_mode) <= SIZE(extend_to_mode) | ||
1825 | + | ||
1826 | + Example 1: | ||
1827 | + Originating (SI->DI) | ||
1828 | + DI SI HI QI 0 | ||
1829 | + |<-------| | | | | ||
1830 | + | ||
1831 | + Candidate (HI->SI extension) | ||
1832 | + DI SI HI QI 0 | ||
1833 | + | |<---| | | | ||
1834 | + | ||
1835 | + Not redundant, candidate does not cover the original bits: | ||
1836 | + SIZE(dest_mode)[SI] !<= SIZE(extend_to_mode)[DI] | ||
1837 | + | ||
1838 | + Example 2: | ||
1839 | + Originating (HI->SI) | ||
1840 | + DI SI HI QI 0 | ||
1841 | + | |<---| | | | ||
1842 | + | ||
1843 | + Candidate (QI->DI extension) | ||
1844 | + DI SI HI QI 0 | ||
1845 | + |<-------|----|--| | | ||
1846 | + | ||
1847 | + Redundant, candidate covers the original bits: | ||
1848 | + SIZE(cand_to_mode) [DI] >= SIZE(extend_to_mode) [SI] | ||
1849 | + AND | ||
1850 | + SIZE(cand_from_mode) [QI] <= SIZE(extend_from_mode) [HI] */ | ||
1851 | + if (GET_CODE (src) == ext_code) | ||
1852 | + { | ||
1853 | + /* Extend is redundant if we don't overwrite the source of the | ||
1854 | + previous extension and extends to at least the extent of the original. */ | ||
1855 | + enum machine_mode cand_from_mode = GET_MODE (XEXP (src, 0)); | ||
1856 | + enum machine_mode cand_to_mode = GET_MODE (src); | ||
1857 | + if (GET_MODE_BITSIZE (cand_from_mode) >= | ||
1858 | + GET_MODE_BITSIZE (ext_from_mode) | ||
1859 | + && (GET_MODE_BITSIZE (cand_to_mode) <= | ||
1860 | + GET_MODE_BITSIZE (ext_to_mode))) | ||
1861 | + return true; | ||
1862 | + } | ||
1863 | + | ||
1864 | + /* Encountered an insn with the same effect as extension, e.g. | ||
1865 | + AND (regspec) (const_int). E.g. AND (reg:SI) (0xffff) is equivalent | ||
1866 | + to ZERO_EXTEND:DI (reg:HI) */ | ||
1867 | + if ((GET_CODE (src) == AND) && CONST_INT_P (XEXP (src, 1))) | ||
1868 | + { | ||
1869 | + /* Extends to at least the original extension size */ | ||
1870 | + if (GET_MODE_BITSIZE (GET_MODE (src)) >= GET_MODE_BITSIZE (ext_to_mode)) | ||
1871 | + { | ||
1872 | + if (ext_from_mode == QImode && (UINTVAL (XEXP (src, 1)) <= 0xff)) | ||
1873 | + return true; | ||
1874 | + else if (ext_from_mode == HImode | ||
1875 | + && (UINTVAL (XEXP (src, 1)) <= 0xffff)) | ||
1876 | + return true; | ||
1877 | + else if (ext_from_mode == SImode | ||
1878 | + && (UINTVAL (XEXP (src, 1)) <= 0xffffffff)) | ||
1879 | + return true; | ||
1880 | + else | ||
1881 | + return false; | ||
1882 | + } | ||
1883 | + } | ||
1884 | + return false; | ||
1885 | +} | ||
1886 | + | ||
1887 | +/* Determine whether the operation's upper bits subtly or overtly affects the low bits. */ | ||
1888 | + | ||
1889 | +static bool | ||
1890 | +operation_implicitly_affects_lowbits (rtx dest, rtx src, | ||
1891 | + unsigned int regno_use, int indent) | ||
1892 | +{ | ||
1893 | + rtx regspec = find_regspec_regno (regno_use, src); | ||
1894 | + | ||
1895 | + /* First, a return expression must be assumed to affect the lowbits as the return value | ||
1896 | + must be extended properly. */ | ||
1897 | + if (return_val_p (dest)) | ||
1898 | + { | ||
1899 | + if (dump_file) | ||
1900 | + { | ||
1901 | + fprintf (dump_file, "%*sDestination is a return value\n", indent, | ||
1902 | + " "); | ||
1903 | + } | ||
1904 | + return true; | ||
1905 | + } | ||
1906 | + | ||
1907 | + /* These operations implicitly affect the lowbits, except where noted. */ | ||
1908 | + switch (GET_CODE (src)) | ||
1909 | + { | ||
1910 | + case MULT: | ||
1911 | + case DIV: | ||
1912 | + case UDIV: | ||
1913 | + case UMOD: | ||
1914 | + case MOD: | ||
1915 | + /* Normally, yes, these operations return true (affects low bits). But when the | ||
1916 | + the operand size is less than or equal to the "low bits" size AND the operation size | ||
1917 | + is the same as the operand size, the operation is performed only on the "low bits" | ||
1918 | + and the "upper bits" do not contribute to the output. */ | ||
1919 | + if (regspec | ||
1920 | + && (GET_MODE_BITSIZE (GET_MODE (regspec)) <= | ||
1921 | + GET_MODE_BITSIZE (ext_from_mode)) | ||
1922 | + && GET_MODE_BITSIZE (GET_MODE (src)) == | ||
1923 | + GET_MODE_BITSIZE (GET_MODE (regspec))) | ||
1924 | + return false; | ||
1925 | + return true; | ||
1926 | + | ||
1927 | + break; | ||
1928 | + /* Shift rights normally affect the low bits. There can be special cases where this | ||
1929 | + is not true, such a the operand size is smaller than the extended from size, e.g. | ||
1930 | + set (reg:SI Y) (zero_extend:SI (subreg:HI (reg:SI X))) | ||
1931 | + set (reg:QI Z) (lshiftrt (subreg:QI (reg:SI Y)) | ||
1932 | + The shift of the QI data is not affected by the extension of HI data unless the | ||
1933 | + shift is large enough to encroach into the QI bits. This seems rare and I do not | ||
1934 | + check for it. */ | ||
1935 | + case LSHIFTRT: | ||
1936 | + case ASHIFTRT: | ||
1937 | + return true; | ||
1938 | + break; | ||
1939 | + /* Other operations are known not to impact the low bits */ | ||
1940 | + default: | ||
1941 | + return false; | ||
1942 | + } | ||
1943 | + | ||
1944 | +} | ||
1945 | + | ||
1946 | +/* The operation directly defines a propagatable output. Several | ||
1947 | + operations do not define such output. E.g. MEM (loads) do not | ||
1948 | + define an output based on the operation. USE is another example, | ||
1949 | + as it isn't a real operation. */ | ||
1950 | + | ||
1951 | +static bool | ||
1952 | +operation_directly_defines_an_output (rtx dest, rtx src, | ||
1953 | + int indent ATTRIBUTE_UNUSED) | ||
1954 | +{ | ||
1955 | + switch (GET_CODE (src)) | ||
1956 | + { | ||
1957 | + case REG: | ||
1958 | + case SUBREG: | ||
1959 | + case PLUS: | ||
1960 | + case MINUS: | ||
1961 | + case NEG: | ||
1962 | + case MULT: | ||
1963 | + case DIV: | ||
1964 | + case MOD: | ||
1965 | + case UDIV: | ||
1966 | + case UMOD: | ||
1967 | + case AND: | ||
1968 | + case IOR: | ||
1969 | + case XOR: | ||
1970 | + case NOT: | ||
1971 | + case ASHIFT: | ||
1972 | + case ROTATE: | ||
1973 | + case ASHIFTRT: | ||
1974 | + case LSHIFTRT: | ||
1975 | + case ROTATERT: | ||
1976 | + case SIGN_EXTEND: | ||
1977 | + case ZERO_EXTEND: | ||
1978 | + case TRUNCATE: | ||
1979 | + return true; | ||
1980 | + break; | ||
1981 | + /* OK to propagate if the output of IF_THEN_ELSE is a register */ | ||
1982 | + case IF_THEN_ELSE: | ||
1983 | + if (REG_P (dest)) | ||
1984 | + return true; | ||
1985 | + break; | ||
1986 | + /* All others are assumed not to generate a normal output */ | ||
1987 | + default: | ||
1988 | + break; | ||
1989 | + } | ||
1990 | + return false; | ||
1991 | +} | ||
1992 | + | ||
1993 | +/* Helper for insn_use_analysis_result */ | ||
1994 | + | ||
1995 | +static enum insn_use_results | ||
1996 | +insn_use_analysis_result_1 (rtx insn, bool treat_as_copy, | ||
1997 | + unsigned int regno_use, rtx * dest, int indent) | ||
1998 | +{ | ||
1999 | + rtx src; | ||
2000 | + bool cond_a, cond_b, cond_c, cond_d; | ||
2001 | + | ||
2002 | + if (GET_CODE (insn) != SET) | ||
2003 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED; | ||
2004 | + | ||
2005 | + *dest = SET_DEST (insn); | ||
2006 | + src = SET_SRC (insn); | ||
2007 | + | ||
2008 | + /* Bail out on inline assembly also */ | ||
2009 | + if (GET_CODE (src) == ASM_INPUT || GET_CODE (src) == ASM_OPERANDS) | ||
2010 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED; | ||
2011 | + | ||
2012 | + /* Bail out on non supported types */ | ||
2013 | + if (!mode_supported_p (*dest)) | ||
2014 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED; | ||
2015 | + | ||
2016 | + /* First, we determine cond_c (is a redundant extension) because it gates the | ||
2017 | + other conditions. */ | ||
2018 | + if ((cond_c = operation_extends_to_upper_bits_size (src, indent))) | ||
2019 | + { | ||
2020 | + if (treat_as_copy) | ||
2021 | + { | ||
2022 | + if (dump_file) | ||
2023 | + fprintf (dump_file, | ||
2024 | + "%*s...%s is treated as a copy (marked for replace)\n", | ||
2025 | + indent, " ", GET_RTX_NAME (GET_CODE (src))); | ||
2026 | + return EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION; | ||
2027 | + } | ||
2028 | + | ||
2029 | + if (dump_file) | ||
2030 | + fprintf (dump_file, | ||
2031 | + "%*s...%s is a redundant extension\n", | ||
2032 | + indent, " ", GET_RTX_NAME (GET_CODE (src))); | ||
2033 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_NOT_AFFECTED; | ||
2034 | + } | ||
2035 | + | ||
2036 | + cond_a = operation_uses_upper_bits (*dest, src, regno_use, indent); | ||
2037 | + | ||
2038 | + cond_b = | ||
2039 | + operation_implicitly_affects_lowbits (*dest, src, regno_use, indent); | ||
2040 | + | ||
2041 | + cond_d = operation_directly_defines_an_output (*dest, src, indent); | ||
2042 | + | ||
2043 | + /* Operation implicitly affects low bits */ | ||
2044 | + if (cond_b) | ||
2045 | + { | ||
2046 | + if (dump_file) | ||
2047 | + fprintf (dump_file, | ||
2048 | + "%*s...%s implicitly affects low bits\n", | ||
2049 | + indent, " ", GET_RTX_NAME (GET_CODE (src))); | ||
2050 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED; | ||
2051 | + } | ||
2052 | + | ||
2053 | + /* Neither cond_a nor cond_b affects the low bits */ | ||
2054 | + if (!cond_a) | ||
2055 | + { | ||
2056 | + if (dump_file) | ||
2057 | + fprintf (dump_file, | ||
2058 | + "%*s...%s does not use upper bits\n", | ||
2059 | + indent, " ", GET_RTX_NAME (GET_CODE (src))); | ||
2060 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_NOT_AFFECTED; | ||
2061 | + } | ||
2062 | + | ||
2063 | + /* To continue recursion, the operation must define a | ||
2064 | + meaningful output. */ | ||
2065 | + if (!cond_d) | ||
2066 | + { | ||
2067 | + if (dump_file) | ||
2068 | + fprintf (dump_file, | ||
2069 | + "%*s...%s does not define a propagatable output\n", | ||
2070 | + indent, " ", GET_RTX_NAME (GET_CODE (src))); | ||
2071 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED; | ||
2072 | + } | ||
2073 | + | ||
2074 | + /* This leaves cond_a, meaning we need to continue down the chain | ||
2075 | + to see if the low bits are ultimately affected by the upper bits. */ | ||
2076 | + return EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION; | ||
2077 | +} | ||
2078 | + | ||
2079 | +/* Determine the action based on the insn conditions. The truth table is | ||
2080 | + simplified using if statements. Insns previously marked for replace by copy | ||
2081 | + are identified, these will be essentially be treated as copies now and not | ||
2082 | + be detected as redundant for this use. */ | ||
2083 | +static enum insn_use_results | ||
2084 | +insn_use_analysis_result (rtx insn_insn, unsigned int regno_use, rtx * dest, | ||
2085 | + int indent) | ||
2086 | +{ | ||
2087 | + bool treat_as_copy = false; | ||
2088 | + if (insn_flag_p (EXTELIM_REPLACE_COPY, INSN_UID (insn_insn))) | ||
2089 | + { | ||
2090 | + if (dump_file) | ||
2091 | + fprintf (dump_file, | ||
2092 | + "%*suse at uid=%d is marked to transform to copy\n", indent, | ||
2093 | + " ", INSN_UID (insn_insn)); | ||
2094 | + treat_as_copy = true; | ||
2095 | + } | ||
2096 | + return (insn_use_analysis_result_1 | ||
2097 | + (PATTERN (insn_insn), treat_as_copy, regno_use, dest, indent)); | ||
2098 | +} | ||
2099 | + | ||
2100 | +/* We have to analyze each expression action in a PARALLEL series. | ||
2101 | + Return the appropriate action for a series of expressions in a PARALLEL insn. | ||
2102 | + LOWBITS_AFFECTED stops the loop. This leaves only CONTINUE_RECURSION | ||
2103 | + or LOWBITS_NOT_AFFECTED. LOWBITS_NOT_AFFECTED is only returned | ||
2104 | + if there are no other different actions in the series (no CONTINUE_RECURSION | ||
2105 | + states). For each CONTINUE_RECURSION action we encounter, the destination | ||
2106 | + registers must be identical since we can only propagate one use (one definition | ||
2107 | + of dest) should CONTINUE_RECURSION be returned. */ | ||
2108 | + | ||
2109 | +static enum insn_use_results | ||
2110 | +analyze_action (enum insn_use_results cur_action, | ||
2111 | + enum insn_use_results prev_action, | ||
2112 | + rtx * dest, rtx * prev_dest) | ||
2113 | +{ | ||
2114 | + enum insn_use_results return_action; | ||
2115 | + | ||
2116 | + if (cur_action == EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED) | ||
2117 | + return cur_action; | ||
2118 | + | ||
2119 | + if (cur_action == EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION) | ||
2120 | + return_action = cur_action; | ||
2121 | + else if (prev_action == EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION) | ||
2122 | + return_action = EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION; | ||
2123 | + else | ||
2124 | + return_action = cur_action; | ||
2125 | + | ||
2126 | + if (return_action == EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION) | ||
2127 | + { | ||
2128 | + if (*prev_dest) | ||
2129 | + { | ||
2130 | + /* All bets off if the series defines multiple outputs */ | ||
2131 | + if (*prev_dest != *dest) | ||
2132 | + return_action = EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED; | ||
2133 | + } | ||
2134 | + } | ||
2135 | + /* Set prev_dest */ | ||
2136 | + *prev_dest = *dest; | ||
2137 | + | ||
2138 | + return return_action; | ||
2139 | +} | ||
2140 | + | ||
2141 | +/* Helper 2 for insn_use_analysis. Return the appropriate action | ||
2142 | + for a series of expressions in a PARALLEL insn. */ | ||
2143 | + | ||
2144 | +static enum insn_use_results | ||
2145 | +insn_use_analysis_2 (rtx insn_use, unsigned int regno_use, rtx * dest, | ||
2146 | + int indent) | ||
2147 | +{ | ||
2148 | + int i; | ||
2149 | + rtx insn = PATTERN (insn_use); | ||
2150 | + rtx prev_dest = NULL_RTX; | ||
2151 | + enum insn_use_results action; | ||
2152 | + enum insn_use_results return_action = | ||
2153 | + EXTELIM_ANALYSIS_RESULT_LOWBITS_NOT_AFFECTED; | ||
2154 | + | ||
2155 | + gcc_assert (GET_CODE (insn) == PARALLEL); | ||
2156 | + | ||
2157 | + /* We make a quick decision about call_insns here. Since the use reached | ||
2158 | + a call, we assume it's an outgoing parameter and thus must be extended | ||
2159 | + as per the ABI. */ | ||
2160 | + if (CALL_P (insn_use)) | ||
2161 | + { | ||
2162 | + if (dump_file) | ||
2163 | + fprintf (dump_file, "%*s...is a call parameter\n", indent, " "); | ||
2164 | + return EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED; | ||
2165 | + } | ||
2166 | + | ||
2167 | + for (i = XVECLEN (insn, 0) - 1; i >= 0; i--) | ||
2168 | + { | ||
2169 | + rtx body = XVECEXP (insn, 0, i); | ||
2170 | + /* Only act on the expressions containing a use of regno_use. */ | ||
2171 | + if (regno_use_in (regno_use, body) == NULL_RTX) | ||
2172 | + continue; | ||
2173 | + | ||
2174 | + /* Determine the next action */ | ||
2175 | + action = insn_use_analysis_result_1 (body, false /* treat as copy */ , | ||
2176 | + regno_use, dest, indent); | ||
2177 | + | ||
2178 | + /* Here we make a decision on the return action based on the previous actions. | ||
2179 | + This is done to accomodate different actions from different elements in the | ||
2180 | + PARALLEL series of expressions. */ | ||
2181 | + return_action = | ||
2182 | + analyze_action (action, return_action, dest, &prev_dest); | ||
2183 | + | ||
2184 | + /* The result of this expression stops the recursion, i.e. "low bits" | ||
2185 | + are affected by the operation. */ | ||
2186 | + if (return_action == EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED) | ||
2187 | + break; | ||
2188 | + } | ||
2189 | + return (return_action); | ||
2190 | +} | ||
2191 | + | ||
2192 | +/* Helper 1 for insn_use_analysis */ | ||
2193 | + | ||
2194 | +static enum insn_use_results | ||
2195 | +insn_use_analysis_1 (rtx insn_use, unsigned int regno_use, rtx * dest, | ||
2196 | + int indent) | ||
2197 | +{ | ||
2198 | + rtx use = PATTERN (insn_use); | ||
2199 | + enum insn_use_results action; | ||
2200 | + | ||
2201 | + switch (GET_CODE (use)) | ||
2202 | + { | ||
2203 | + case PARALLEL: | ||
2204 | + action = insn_use_analysis_2 (insn_use, regno_use, dest, indent); | ||
2205 | + break; | ||
2206 | + default: | ||
2207 | + action = insn_use_analysis_result (insn_use, regno_use, dest, indent); | ||
2208 | + break; | ||
2209 | + } | ||
2210 | + | ||
2211 | + return action; | ||
2212 | +} | ||
2213 | + | ||
2214 | +/* Analyze the insn and determine the next course of action in the | ||
2215 | + use analysis loop. | ||
2216 | + There are several conditions to consider: | ||
2217 | + | ||
2218 | + 1. The "extended from" mode. This is an enum machine_mode value | ||
2219 | + that determines what is the size extended. It is derived from the | ||
2220 | + source of the original extension. It is the "low bits" value. | ||
2221 | + It is these range of bits that cannot be affected by the operation's | ||
2222 | + "upper bits" in order to determine whether the extend is useful or not. | ||
2223 | + Examples: | ||
2224 | + (1) set (reg:DI Y (zero_extend:DI (subreg:QI (reg:DI X))) ==> low bits = QI | ||
2225 | + (2) set (reg:SI Y (sign_extend:SI (reg:HI X) ==> low bits = HI | ||
2226 | + | ||
2227 | + 2. The "extend to" mode. This is the size extended to in the original | ||
2228 | + extension. It is the "upper bits" value. The entire extended to size may | ||
2229 | + be used subsequently or it may be subreg'd to a smaller or larger sizes | ||
2230 | + later in the propagation. | ||
2231 | + For example (1) above, "upper bits" is DI, and (2) "upper bits" is SI. | ||
2232 | + | ||
2233 | + 3. The code, ext_code, of the original extension, either ZERO_EXTEND or SIGN_EXTEND. | ||
2234 | + | ||
2235 | + 4. Operation code. For an insn, the actual operation code corresponding to | ||
2236 | + a machine instruction. For certain codes, we know that the "low bits" of the | ||
2237 | + result are modified by the insn because of the values in the "upper bits" of the | ||
2238 | + input operand. We say the operation implicitly uses the "upper bits" to modify the | ||
2239 | + "low bits". For other codes, the "upper bits" do not affect the output result | ||
2240 | + in the "low bits". | ||
2241 | + | ||
2242 | + If the operation does implicitly use the "upper bits" to modify | ||
2243 | + the "low bits", it is instantly a deal killer. The original extension must be | ||
2244 | + preserved. | ||
2245 | + | ||
2246 | + If the operation does not implicitly use "upper bits" to modify the "low bits", | ||
2247 | + then the action to take depends on the operation operand size relative to | ||
2248 | + "low bits" size. | ||
2249 | + | ||
2250 | + We only want to deal with codes that map to real instructions, | ||
2251 | + like ADD, SUB, MULT, LSHIFTRT, etc. Codes such as PARALLEL, etc. do not map to | ||
2252 | + instruction and must be dissected to extract the real instructions. | ||
2253 | + | ||
2254 | + Furthermode, for recursion to continue, the operation and operand must define | ||
2255 | + an output related to the input operand (the use register). This doesn't happen | ||
2256 | + for operations such as "mem" where the output is indirectly related to the | ||
2257 | + input operand. | ||
2258 | + | ||
2259 | + 5. Operation mode. The operation mode of the operation code. This sometimes impacts | ||
2260 | + the effect of the operation. For example MULT:SI and MULT:DI map to two different | ||
2261 | + machine instructions and both may have operands of SI mode. However, the MULT:SI | ||
2262 | + results will be oblivious to the upper bits of the DI register whereas, SI part of | ||
2263 | + MULT:DI result will be affected by the upper bits of the DI register. | ||
2264 | + | ||
2265 | + Several conditions determine the action to take based on the various inputs. | ||
2266 | + | ||
2267 | + The truth table inputs are A, B, and C. The truth table output is the action to take. | ||
2268 | + | ||
2269 | + A. True if the used operand mode size is greater than the extended_from ("low bits") mode size. | ||
2270 | + B. True if the operation implicitly uses upper bits to define the low bits | ||
2271 | + C. True if the operation also extends the output to upper bits size | ||
2272 | + D. True if the operation and input operand directly define an output operand. | ||
2273 | + | ||
2274 | + Condition A. means the upper bits are in use in the operation. The extend _may_ be needed, | ||
2275 | + all things being equal, so the action would be to continue recursion to the use of the | ||
2276 | + defined operand, i.e. return CONTINUE_RECURSION. | ||
2277 | + | ||
2278 | + Condition B. means the "low bits" are modified by the extended portion of the register | ||
2279 | + by virtue of the operation. For example, logical shift right, where the extended | ||
2280 | + portion is shifted into the "low bits". Another example, multiply, where the machine | ||
2281 | + uses the extended portion implicitly to calculate the results, some of which are | ||
2282 | + reflected in the "low bits" of the result. The extension is definitely needed in these | ||
2283 | + cases for this use, so return LOWBITS_AFFECTED. Recursion is stopped and analysis of | ||
2284 | + this extension is halted. | ||
2285 | + | ||
2286 | + Condition C. means the operation and it's operands perform the same extension as | ||
2287 | + the originating extension. The operation must extend to the same size _or higher_ of | ||
2288 | + the original extension. In this case, the original extension is truly redundant and | ||
2289 | + we return LOWBITS_NOT_AFFECTED for this use. | ||
2290 | + | ||
2291 | + Condtion D. means the operation and operand directly define an output operand. For most | ||
2292 | + arithmetic and unary operations this is true. For mem and other internal operations, | ||
2293 | + e.g. USE, this is false. | ||
2294 | + | ||
2295 | + Condition Action Comments | ||
2296 | + ================================================================== | ||
2297 | + A. B. C. D. | ||
2298 | + ------------------------------------------------------------------ | ||
2299 | + X X true true LOW_BITS_NOT_AFFECTED extend is redundant | ||
2300 | + ------------------------------------------------------------------ | ||
2301 | + false false false X LOW_BITS_NOT_AFFECTED used operand is smaller than "low bits" | ||
2302 | + ------------------------------------------------------------------ | ||
2303 | + false true false true LOW_BITS_AFFECTED "low bits" modified implicitly by operation | ||
2304 | + ------------------------------------------------------------------ | ||
2305 | + true false false true CONTINUE_RECURSION "low bits" _may_ be impacted by next uses | ||
2306 | + ------------------------------------------------------------------ | ||
2307 | + true true false true LOW_BITS_AFFECTED "low bits" modified implicitly by operation */ | ||
2308 | + | ||
2309 | +static enum insn_use_results | ||
2310 | +insn_use_analysis (rtx insn_use, unsigned int regno_use, rtx * dest, | ||
2311 | + int indent) | ||
2312 | +{ | ||
2313 | + return (insn_use_analysis_1 (insn_use, regno_use, dest, indent)); | ||
2314 | +} | ||
2315 | + | ||
2316 | +/* Analyze the operation and operands of this use of a sign extension | ||
2317 | + target register. If the target register's upper bits do not | ||
2318 | + affect the result of the operation, then the sign extension is | ||
2319 | + useless. Returns true if the extension is needed, false | ||
2320 | + otherwise. */ | ||
2321 | + | ||
2322 | +static bool | ||
2323 | +analyze_ext_use (rtx insn_use, unsigned int regno_use, int indent) | ||
2324 | +{ | ||
2325 | + bool ext_needed, indent_once; | ||
2326 | + unsigned int dest_target_regno; | ||
2327 | + extelim_uid_t uid; | ||
2328 | + rtx use = PATTERN (insn_use), dest; | ||
2329 | + df_ref df_use, *p_def; | ||
2330 | + struct df_link *link; | ||
2331 | + enum insn_use_results analysis_result; | ||
2332 | + | ||
2333 | + gcc_assert (use != NULL); | ||
2334 | + | ||
2335 | + uid = INSN_UID (insn_use); | ||
2336 | + | ||
2337 | + if (insn_flag_p (EXTELIM_SEEN, uid)) | ||
2338 | + { | ||
2339 | + if (dump_file) | ||
2340 | + fprintf (dump_file, | ||
2341 | + "%*suse at uid=%d is visited already\n", indent, " ", uid); | ||
2342 | + return false; | ||
2343 | + } | ||
2344 | + | ||
2345 | + /* Mark this insn as seen */ | ||
2346 | + insn_flag_set (EXTELIM_SEEN, uid); | ||
2347 | + | ||
2348 | + analysis_result = insn_use_analysis (insn_use, regno_use, &dest, indent); | ||
2349 | + switch (analysis_result) | ||
2350 | + { | ||
2351 | + /* We know conclusively that the "upper bits" of the extended | ||
2352 | + entity do not impact the "low bits" of the output of the operation. */ | ||
2353 | + case EXTELIM_ANALYSIS_RESULT_LOWBITS_NOT_AFFECTED: | ||
2354 | + if (dump_file) | ||
2355 | + fprintf (dump_file, "%*suse at uid=%d is not affected\n", indent, " ", | ||
2356 | + uid); | ||
2357 | + return false; | ||
2358 | + break; | ||
2359 | + /* We know conclusively that the "upper bits" of the extended | ||
2360 | + entity _do_ impact the "low bits" of the output of the operation. */ | ||
2361 | + case EXTELIM_ANALYSIS_RESULT_LOWBITS_AFFECTED: | ||
2362 | + if (dump_file) | ||
2363 | + fprintf (dump_file, "%*suse at uid=%d is affected\n", indent, " ", | ||
2364 | + uid); | ||
2365 | + return true; | ||
2366 | + break; | ||
2367 | + /* Continue to look at the uses of the result to determine the impact | ||
2368 | + of the "upper bits" */ | ||
2369 | + case EXTELIM_ANALYSIS_RESULT_CONTINUE_RECURSION: | ||
2370 | + break; | ||
2371 | + default: | ||
2372 | + gcc_unreachable (); | ||
2373 | + } | ||
2374 | + | ||
2375 | + /* We reach here because the action taken is CONTINUE_RECURSION. | ||
2376 | + Continue to look at the uses of the destination register recursively. | ||
2377 | + If the propagation ultimately ends where the upper bits are not significant | ||
2378 | + to the final output, then the extension can be removed. */ | ||
2379 | + if (!REG_P (dest)) | ||
2380 | + { | ||
2381 | + if (dump_file) | ||
2382 | + fprintf (dump_file, | ||
2383 | + "%*sdest of uid=%d (SET) is not a register\n", indent, " ", | ||
2384 | + uid); | ||
2385 | + return true; | ||
2386 | + } | ||
2387 | + | ||
2388 | + dest_target_regno = REGNO (dest); | ||
2389 | + | ||
2390 | + /* What this insn defines */ | ||
2391 | + p_def = DF_INSN_UID_DEFS (uid); | ||
2392 | + | ||
2393 | + /* Ref must be valid and there must be only one definition and it must be the | ||
2394 | + destination */ | ||
2395 | + if ((*p_def == NULL) || (*(p_def + 1) != NULL)) | ||
2396 | + return true; | ||
2397 | + | ||
2398 | + gcc_assert (DF_REF_REGNO (*p_def) == dest_target_regno); | ||
2399 | + | ||
2400 | + ext_needed = true; | ||
2401 | + indent_once = true; | ||
2402 | + for (link = DF_REF_CHAIN (*p_def); link; link = link->next) | ||
2403 | + { | ||
2404 | + rtx insn_use, use_exp; | ||
2405 | + df_use = link->ref; | ||
2406 | + if (!df_use) | ||
2407 | + continue; | ||
2408 | + /* Link must be a USE of the DEF */ | ||
2409 | + if (!DF_REF_REG_USE_P (df_use)) | ||
2410 | + continue; | ||
2411 | + /* Ignore ARTIFICIAL USES */ | ||
2412 | + if (DF_REF_IS_ARTIFICIAL (df_use)) | ||
2413 | + continue; | ||
2414 | + insn_use = DF_REF_INSN (df_use); | ||
2415 | + /* Don't consider debug_insns */ | ||
2416 | + if (!NONDEBUG_INSN_P (insn_use)) | ||
2417 | + continue; | ||
2418 | + use_exp = DF_REF_REG (df_use); | ||
2419 | + | ||
2420 | + if (exp_needs_update_p (use_exp)) | ||
2421 | + { | ||
2422 | + if (dump_file) | ||
2423 | + fprintf (dump_file, | ||
2424 | + "%*ssaved reg=%d expression for update\n", indent, " ", DF_REF_REGNO (df_use)); | ||
2425 | + save_ext_update (current_ext_record, use_exp); | ||
2426 | + } | ||
2427 | + | ||
2428 | + if (dump_file) | ||
2429 | + fprintf (dump_file, | ||
2430 | + "%*suse at uid=%d of reg=%d\n", indent, " ", | ||
2431 | + INSN_UID (insn_use), DF_REF_REGNO (df_use)); | ||
2432 | + /* Set indent for dump formatting */ | ||
2433 | + if (indent_once) | ||
2434 | + { | ||
2435 | + ++indent; | ||
2436 | + indent_once = false; | ||
2437 | + } | ||
2438 | + ext_needed = analyze_ext_use (insn_use, DF_REF_REGNO (df_use), indent); | ||
2439 | + if (ext_needed) | ||
2440 | + break; | ||
2441 | + } | ||
2442 | + | ||
2443 | + if (dump_file) | ||
2444 | + fprintf (dump_file, | ||
2445 | + "%*sext %s needed\n", indent, " ", ext_needed ? "" : "not"); | ||
2446 | + | ||
2447 | + return ext_needed; | ||
2448 | +} | ||
2449 | + | ||
2450 | +/* Set a flag on an insn indicating that it is | ||
2451 | + marked for replacement by a copy insn or for | ||
2452 | + deletion. */ | ||
2453 | + | ||
2454 | +static void | ||
2455 | +mark_replace_with_copy (rtx ext) | ||
2456 | +{ | ||
2457 | + extelim_uid_t uid = INSN_UID (ext); | ||
2458 | + insn_flag_set (EXTELIM_REPLACE_COPY, uid); | ||
2459 | +} | ||
2460 | + | ||
2461 | +/* Get the mode that we are sign/zero extending from */ | ||
2462 | + | ||
2463 | +static enum machine_mode | ||
2464 | +get_ext_from_mode (rtx src) | ||
2465 | +{ | ||
2466 | + rtx regexp; | ||
2467 | + gcc_assert (GET_CODE (src) == ZERO_EXTEND || GET_CODE (src) == SIGN_EXTEND); | ||
2468 | + | ||
2469 | + /* The SUBREG or REG mode of the extend operand */ | ||
2470 | + regexp = XEXP (src, 0); | ||
2471 | + return (GET_MODE (regexp)); | ||
2472 | +} | ||
2473 | + | ||
2474 | +/* Perform the action on the expression. Return true | ||
2475 | + if any action performed, false otherwise. */ | ||
2476 | + | ||
2477 | +static bool | ||
2478 | +process_ext_update (rtx exp) | ||
2479 | +{ | ||
2480 | + /* Reset SUBREG_PROMOTED state to false */ | ||
2481 | + if (GET_CODE (exp) == SUBREG | ||
2482 | + && SUBREG_PROMOTED_VAR_P (exp)) | ||
2483 | + { | ||
2484 | + SUBREG_PROMOTED_VAR_P (exp) = 0; | ||
2485 | + return true; | ||
2486 | + } | ||
2487 | + | ||
2488 | + return false; | ||
2489 | +} | ||
2490 | + | ||
2491 | +/* Process the current extension record, looking at all the | ||
2492 | + the expressions that need to be updated because this | ||
2493 | + extension will be replaced by a copy. */ | ||
2494 | + | ||
2495 | +static void | ||
2496 | +process_ext_updates (ext_record_t extrec) | ||
2497 | +{ | ||
2498 | + unsigned i; | ||
2499 | + rtx exp; | ||
2500 | + bool updated=false; | ||
2501 | + | ||
2502 | + | ||
2503 | + FOR_EACH_VEC_ELT (rtx, extrec->ext_updates, i, exp) | ||
2504 | + { | ||
2505 | + updated |= process_ext_update (exp); | ||
2506 | + } | ||
2507 | + | ||
2508 | + if (dump_file && updated) | ||
2509 | + fprintf (dump_file, " updates processed for extension at uid=%d\n", | ||
2510 | + INSN_UID (extrec->ext)); | ||
2511 | +} | ||
2512 | + | ||
2513 | +/* Try to eliminate the sign extension by examining the | ||
2514 | + definitions of the extension source and the uses | ||
2515 | + of the extension destination. */ | ||
2516 | + | ||
2517 | +static void | ||
2518 | +eliminate_one_extend (rtx ext) | ||
2519 | +{ | ||
2520 | + rtx src, dest, regexp; | ||
2521 | + df_ref df_use, df_def, *ext_use, *ext_def; | ||
2522 | + unsigned int ext_dest_regno, ext_src_regno, def_use_count = 1; | ||
2523 | + bool ext_needed = true; | ||
2524 | + extelim_uid_t uid = INSN_UID (ext); | ||
2525 | + struct df_link *link; | ||
2526 | + const char *inserted = | ||
2527 | + insn_flag_p (EXTELIM_INSERTED, uid) ? "inserted" : ""; | ||
2528 | + | ||
2529 | + /* Reset desired per insn flags for each extension analyzed */ | ||
2530 | + reinit_insn_flags (EXTELIM_SEEN); | ||
2531 | + | ||
2532 | + gcc_assert (GET_CODE (PATTERN (ext)) == SET); | ||
2533 | + src = SET_SRC (PATTERN (ext)); | ||
2534 | + dest = SET_DEST (PATTERN (ext)); | ||
2535 | + | ||
2536 | + /* Save the basic information about the extension in a file global */ | ||
2537 | + ext_to_mode = GET_MODE (dest); | ||
2538 | + ext_from_mode = get_ext_from_mode (src); | ||
2539 | + ext_code = GET_CODE (src); | ||
2540 | + | ||
2541 | + /* Also mark this original extension as "SEEN" so we don't recurse into it. */ | ||
2542 | + insn_flag_set (EXTELIM_SEEN, INSN_UID (ext)); | ||
2543 | + | ||
2544 | + /* Find the target of the extension */ | ||
2545 | + if (!REG_P (dest)) | ||
2546 | + return; | ||
2547 | + ext_dest_regno = REGNO (dest); | ||
2548 | + | ||
2549 | + /* Find the source of the extension: set (REG:MODE (sign_extend (REG|SUBREG:MODE ... */ | ||
2550 | + if ((regexp = register_exp (XEXP (src, 0))) == NULL) | ||
2551 | + return; | ||
2552 | + ext_src_regno = REGNO (regexp); | ||
2553 | + | ||
2554 | + /* Iterate through the reaching definitions of the source of the extension | ||
2555 | + recursively. If the source if already sign extended, mark the | ||
2556 | + extension for replacement with a copy or deletion (deletion if it was | ||
2557 | + inserted in the duplication pass). */ | ||
2558 | + ext_use = DF_INSN_UID_USES (uid); | ||
2559 | + /* There is only one use in a sign/zero extension insn and it must be the | ||
2560 | + source register */ | ||
2561 | + gcc_assert (*(ext_use + 1) == NULL); | ||
2562 | + gcc_assert (DF_REF_REGNO (*ext_use) == ext_src_regno); | ||
2563 | + | ||
2564 | + /* Now look at all the reaching definitions of this use */ | ||
2565 | + for (link = DF_REF_CHAIN (*ext_use); link; link = link->next) | ||
2566 | + { | ||
2567 | + rtx insn_def; | ||
2568 | + df_def = link->ref; | ||
2569 | + if (!df_def) | ||
2570 | + continue; | ||
2571 | + /* Link must be to a definition of the use */ | ||
2572 | + if (!DF_REF_REG_DEF_P (df_def)) | ||
2573 | + continue; | ||
2574 | + /* Ignore ARTIFICIAL defs */ | ||
2575 | + if (DF_REF_IS_ARTIFICIAL (df_def)) | ||
2576 | + continue; | ||
2577 | + insn_def = DF_REF_INSN (df_def); | ||
2578 | + /* Don't consider debug_insns */ | ||
2579 | + if (!NONDEBUG_INSN_P (insn_def)) | ||
2580 | + continue; | ||
2581 | + if (dump_file) | ||
2582 | + fprintf (dump_file, | ||
2583 | + " analyze def #%d of reg=%d at uid=%u\n", | ||
2584 | + def_use_count, DF_REF_REGNO (*ext_use), INSN_UID (insn_def)); | ||
2585 | + ext_needed = analyze_ext_def (insn_def, DF_REF_REGNO (*ext_use), 2); | ||
2586 | + if (ext_needed) | ||
2587 | + break; | ||
2588 | + def_use_count++; | ||
2589 | + } | ||
2590 | + | ||
2591 | + /* Try the def-use chains if the extension wasn't marked by the | ||
2592 | + previous pass. */ | ||
2593 | + if (ext_needed) | ||
2594 | + { | ||
2595 | + /* Defs of the sign extension */ | ||
2596 | + ext_def = DF_INSN_UID_DEFS (uid); | ||
2597 | + /* There is only one def in a sign extension insn and it must be the | ||
2598 | + destination */ | ||
2599 | + gcc_assert (*(ext_def + 1) == NULL); | ||
2600 | + gcc_assert (DF_REF_REGNO (*ext_def) == ext_dest_regno); | ||
2601 | + | ||
2602 | + /* Counter for debug dump */ | ||
2603 | + def_use_count = 1; | ||
2604 | + /* Reset desired per insn flags for each extension analyzed */ | ||
2605 | + reinit_insn_flags (EXTELIM_SEEN); | ||
2606 | + /* Also mark this original extension as "SEEN" so we don't recurse into it. */ | ||
2607 | + insn_flag_set (EXTELIM_SEEN, INSN_UID (ext)); | ||
2608 | + | ||
2609 | + /* Iterate over the reached uses of extension destination register recursively. | ||
2610 | + If the destination register's upper bits are ultimately not | ||
2611 | + relevant, the extension can be marked for replacement with a | ||
2612 | + copy. */ | ||
2613 | + for (link = DF_REF_CHAIN (*ext_def); link; link = link->next) | ||
2614 | + { | ||
2615 | + rtx insn_use, use_exp; | ||
2616 | + df_use = link->ref; | ||
2617 | + if (!df_use) | ||
2618 | + continue; | ||
2619 | + /* Link must be a USE of the DEF */ | ||
2620 | + if (!DF_REF_REG_USE_P (df_use)) | ||
2621 | + continue; | ||
2622 | + /* Ignore ARTIFICIAL USES */ | ||
2623 | + if (DF_REF_IS_ARTIFICIAL (df_use)) | ||
2624 | + continue; | ||
2625 | + insn_use = DF_REF_INSN (df_use); | ||
2626 | + /* Don't consider debug_insns */ | ||
2627 | + if (!NONDEBUG_INSN_P (insn_use)) | ||
2628 | + continue; | ||
2629 | + use_exp = DF_REF_REG (df_use); | ||
2630 | + | ||
2631 | + if (exp_needs_update_p (use_exp)) | ||
2632 | + { | ||
2633 | + if (dump_file) | ||
2634 | + fprintf (dump_file, | ||
2635 | + " saved reg=%d expression for update\n", DF_REF_REGNO (df_use)); | ||
2636 | + save_ext_update (current_ext_record, use_exp); | ||
2637 | + } | ||
2638 | + | ||
2639 | + if (dump_file) | ||
2640 | + fprintf (dump_file, | ||
2641 | + " analyze use #%d at uid=%u of reg=%d\n", | ||
2642 | + def_use_count, INSN_UID (insn_use), | ||
2643 | + DF_REF_REGNO (*ext_def)); | ||
2644 | + ext_needed = analyze_ext_use (insn_use, DF_REF_REGNO (*ext_def), 2); | ||
2645 | + if (ext_needed) | ||
2646 | + break; | ||
2647 | + def_use_count++; | ||
2648 | + } | ||
2649 | + } | ||
2650 | + | ||
2651 | + /* The extension is not needed. The rtl for the extension is marked | ||
2652 | + for replace by copy. */ | ||
2653 | + if (!ext_needed) | ||
2654 | + { | ||
2655 | + process_ext_updates (current_ext_record); | ||
2656 | + | ||
2657 | + if (dump_file) | ||
2658 | + fprintf (dump_file, | ||
2659 | + ":) mark %s extension insn uid=%d for copy replacement\n", | ||
2660 | + inserted, INSN_UID (ext)); | ||
2661 | + mark_replace_with_copy (ext); | ||
2662 | + num_cand_transformed++; | ||
2663 | + } | ||
2664 | + else | ||
2665 | + { | ||
2666 | + if (dump_file) | ||
2667 | + fprintf (dump_file, | ||
2668 | + ":( %s extension insn uid=%d is needed\n", inserted, | ||
2669 | + INSN_UID (ext)); | ||
2670 | + } | ||
2671 | +} | ||
2672 | + | ||
2673 | +/* Replace the sign extension with a copy instruction | ||
2674 | + | ||
2675 | + example 1: | ||
2676 | + from: | ||
2677 | + dest src | ||
2678 | + (set (reg:DI destreg) (sign_extend:DI (reg:SI srcreg))) | ||
2679 | + to: | ||
2680 | + (clobber (reg:DI destreg)) | ||
2681 | + (set (subreg:SI (reg:DI destreg) 4) (reg:SI srcreg)) | ||
2682 | + | ||
2683 | + or | ||
2684 | + | ||
2685 | + example 2: | ||
2686 | + from: | ||
2687 | + dest src | ||
2688 | + (set (reg:DI destreg) (sign_extend:DI (subreg:SI (reg:DI srcreg) 4))) | ||
2689 | + to: | ||
2690 | + (clobber (reg:DI destreg)) | ||
2691 | + (set (subreg:SI (reg:DI destreg) 4) (subreg:SI (reg:DI srcreg) 4)) | ||
2692 | + | ||
2693 | + or | ||
2694 | + | ||
2695 | + example 3: | ||
2696 | + from: | ||
2697 | + dest src | ||
2698 | + (set (reg:SI destreg) (sign_extend:SI (subreg:HI (reg:SI srcreg) 2))) | ||
2699 | + to: | ||
2700 | + (clobber (reg:SI destreg)) | ||
2701 | + (set (subreg:HI (reg:SI destreg) 2) (subreg:HI (reg:SI srcreg) 2)) */ | ||
2702 | + | ||
2703 | +static void | ||
2704 | +replace_with_copy (rtx ext) | ||
2705 | +{ | ||
2706 | + rtx extension = PATTERN (ext); | ||
2707 | + rtx ext_op, src, dest, insns, cp_dest, cp_src; | ||
2708 | + enum machine_mode inner_mode; | ||
2709 | + gcc_assert (GET_CODE (extension) == SET); | ||
2710 | + | ||
2711 | + dest = SET_DEST (extension); | ||
2712 | + src = SET_SRC (extension); | ||
2713 | + | ||
2714 | + /* The sign extension operand */ | ||
2715 | + ext_op = XEXP (src, 0); | ||
2716 | + /* Get the inner mode */ | ||
2717 | + inner_mode = GET_MODE (ext_op); | ||
2718 | + gcc_assert (inner_mode == SImode || inner_mode == HImode | ||
2719 | + || inner_mode == QImode); | ||
2720 | + | ||
2721 | + /* Make dest a SUBREG:mm */ | ||
2722 | + cp_dest = gen_lowpart_SUBREG (inner_mode, dest); | ||
2723 | + | ||
2724 | + /* Copy src is the sign extension target register */ | ||
2725 | + cp_src = ext_op; | ||
2726 | + | ||
2727 | + /* ??? clobber is needed for rtl consistency, don't know why */ | ||
2728 | + start_sequence (); | ||
2729 | + emit_clobber (dest); | ||
2730 | + emit_move_insn (cp_dest, cp_src); | ||
2731 | + insns = get_insns (); | ||
2732 | + end_sequence (); | ||
2733 | + emit_insn_before (insns, ext); | ||
2734 | + | ||
2735 | + delete_insn (ext); | ||
2736 | +} | ||
2737 | + | ||
2738 | +/* Iterate through extensions, replace those extensions | ||
2739 | + that are marked as so with a copy insn. */ | ||
2740 | + | ||
2741 | +static void | ||
2742 | +replace_ext_with_copy (void) | ||
2743 | +{ | ||
2744 | + ext_record_t extrec; | ||
2745 | + unsigned i; | ||
2746 | + | ||
2747 | + FOR_EACH_VEC_ELT (ext_record_t, extensions, i, extrec) | ||
2748 | + { | ||
2749 | + const char *inserted = insn_flag_p (EXTELIM_INSERTED, | ||
2750 | + INSN_UID (extrec-> | ||
2751 | + ext)) ? "inserted" : ""; | ||
2752 | + if (insn_flag_p (EXTELIM_REPLACE_COPY, INSN_UID (extrec->ext))) | ||
2753 | + { | ||
2754 | + if (dump_file) | ||
2755 | + fprintf (dump_file, | ||
2756 | + " replace %s extension uid=%d with a copy\n", inserted, | ||
2757 | + INSN_UID (extrec->ext)); | ||
2758 | + replace_with_copy (extrec->ext); | ||
2759 | + } | ||
2760 | + } | ||
2761 | +} | ||
2762 | + | ||
2763 | + | ||
2764 | +/* Copy the RTX flags from old to new */ | ||
2765 | + | ||
2766 | +static void | ||
2767 | +copy_flags (rtx oldrtx, rtx newrtx) | ||
2768 | +{ | ||
2769 | + if (RTX_FLAG (oldrtx, in_struct)) | ||
2770 | + RTX_FLAG (newrtx, in_struct) = true; | ||
2771 | + | ||
2772 | + if (RTX_FLAG (oldrtx, volatil)) | ||
2773 | + RTX_FLAG (newrtx, volatil) = true; | ||
2774 | + | ||
2775 | + if (RTX_FLAG (oldrtx, unchanging)) | ||
2776 | + RTX_FLAG (newrtx, unchanging) = true; | ||
2777 | + | ||
2778 | + if (RTX_FLAG (oldrtx, frame_related)) | ||
2779 | + RTX_FLAG (newrtx, frame_related) = true; | ||
2780 | + | ||
2781 | + if (RTX_FLAG (oldrtx, jump)) | ||
2782 | + RTX_FLAG (newrtx, jump) = true; | ||
2783 | + | ||
2784 | + if (RTX_FLAG (oldrtx, call)) | ||
2785 | + RTX_FLAG (newrtx, call) = true; | ||
2786 | + | ||
2787 | + if (RTX_FLAG (oldrtx, return_val)) | ||
2788 | + RTX_FLAG (newrtx, return_val) = true; | ||
2789 | +} | ||
2790 | + | ||
2791 | +/* Iterate through the insn notes looking for 'kind'. If | ||
2792 | + found replace the register rtx with the new rtx. */ | ||
2793 | + | ||
2794 | +static void | ||
2795 | +update_notes (enum reg_note kind, rtx insn, rtx reg, rtx new_reg) | ||
2796 | +{ | ||
2797 | + rtx link; | ||
2798 | + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | ||
2799 | + if (REG_NOTE_KIND (link) == kind) | ||
2800 | + { | ||
2801 | + rtx op0 = XEXP (link, 0); | ||
2802 | + if (kind == REG_DEAD) | ||
2803 | + if (REG_P (op0) && op0 == reg) | ||
2804 | + XEXP (link, 0) = new_reg; | ||
2805 | + } | ||
2806 | +} | ||
2807 | + | ||
2808 | + | ||
2809 | + | ||
2810 | +#if EXTELIM_DUPLICATE_EXTS_AT_USES | ||
2811 | +/* Insert a duplicate sign extension at the use point. | ||
2812 | + Add a flag indicating this extension is algorithmically | ||
2813 | + added. Since the "inserted" extensions have the form | ||
2814 | + regX = sign_extend (subreg:mm (reg:MM regX), offset), | ||
2815 | + they can simply be deleted if they are redundant since we | ||
2816 | + are at a reaching use of the original definition. We also | ||
2817 | + mark the use insn where the insert occurs so we don't insert | ||
2818 | + the same extension from another def at this use. */ | ||
2819 | + | ||
2820 | +static void | ||
2821 | +insert_duplicate_ext_at_use (rtx ext_insn, rtx use_insn) | ||
2822 | +{ | ||
2823 | + rtx ext = PATTERN (ext_insn), ext_src, ext_dest; | ||
2824 | + rtx new_ext_src_inner, new_ext_src_outer, new_ext_part; | ||
2825 | + rtx new_ext_dest, new_ext_insn; | ||
2826 | + extelim_uid_t new_uid; | ||
2827 | + df_ref *p_df_uses; | ||
2828 | + unsigned int ext_dest_regno; | ||
2829 | + enum machine_mode inner_mode; | ||
2830 | + bool sign_extend_p = | ||
2831 | + GET_CODE (SET_SRC (PATTERN (ext_insn))) == SIGN_EXTEND ? true : false; | ||
2832 | + | ||
2833 | + /* This new extension must be of the form: | ||
2834 | + set (reg:MM X (sign_extend:MM (subreg:mm (reg:MM X)))) | ||
2835 | + where mm is smaller than MM. */ | ||
2836 | + ext_dest = SET_DEST (ext); | ||
2837 | + ext_src = SET_SRC (ext); | ||
2838 | + | ||
2839 | + gcc_assert (REG_P (register_exp (ext_dest))); | ||
2840 | + | ||
2841 | + /* A copy of the extend destination register to a new virtual register */ | ||
2842 | + new_ext_dest = gen_reg_rtx (GET_MODE (ext_dest)); | ||
2843 | + /* A copy of the extend source (same reg as dest), REG_P */ | ||
2844 | + new_ext_src_inner = copy_rtx (ext_dest); | ||
2845 | + /* Get inner mode, either mm for SUBREG:mm (REG:MM) or MM for (REG:MM) */ | ||
2846 | + if (GET_CODE (XEXP (ext_src, 0)) == SUBREG) | ||
2847 | + inner_mode = GET_MODE (XEXP (ext_src, 0)); | ||
2848 | + else if (REG_P (XEXP (ext_src, 0))) | ||
2849 | + inner_mode = GET_MODE (XEXP (ext_src, 0)); | ||
2850 | + else | ||
2851 | + /* Can't determine sign_extend operand */ | ||
2852 | + gcc_unreachable (); | ||
2853 | + | ||
2854 | + /* Make a subreg rtx */ | ||
2855 | + new_ext_src_outer = gen_lowpart_SUBREG (inner_mode, new_ext_src_inner); | ||
2856 | + /* Make a sign/zero extend insn */ | ||
2857 | + new_ext_part = sign_extend_p | ||
2858 | + ? gen_rtx_SIGN_EXTEND (GET_MODE (ext_dest), new_ext_src_outer) | ||
2859 | + : gen_rtx_ZERO_EXTEND (GET_MODE (ext_dest), new_ext_src_outer); | ||
2860 | + /* (set (new:MM (sign_extend:MM (subreg:mm (reg:MM ext_dest))))) */ | ||
2861 | + new_ext_insn = gen_rtx_SET (VOIDmode, new_ext_dest, new_ext_part); | ||
2862 | + | ||
2863 | + /* Now update the use */ | ||
2864 | + /* Operands used by this the use_insn */ | ||
2865 | + ext_dest_regno = REGNO (register_exp (ext_dest)); | ||
2866 | + for (p_df_uses = DF_INSN_UID_USES (INSN_UID (use_insn)); *p_df_uses; | ||
2867 | + p_df_uses++) | ||
2868 | + { | ||
2869 | + if (DF_REF_REGNO (*p_df_uses) == ext_dest_regno) | ||
2870 | + { | ||
2871 | + rtx use_reg = DF_REF_REG (*p_df_uses); | ||
2872 | + | ||
2873 | + /* Replace the register use in use_insn with the new register. If the use | ||
2874 | + is a subreg pattern, replace the innermost reg. */ | ||
2875 | + replace_rtx (PATTERN (use_insn), register_exp (use_reg), | ||
2876 | + new_ext_dest); | ||
2877 | + /* Update flags on new dest reg */ | ||
2878 | + copy_flags (register_exp (use_reg), new_ext_dest); | ||
2879 | + /* Update any notes associated with use reg and use_insn */ | ||
2880 | + update_notes (REG_DEAD, use_insn, register_exp (use_reg), new_ext_dest); | ||
2881 | + /* DF info must be updated since existing insn is changed */ | ||
2882 | + df_insn_rescan (use_insn); | ||
2883 | + } | ||
2884 | + } | ||
2885 | + | ||
2886 | + new_uid = extelim_emit_before (new_ext_insn, use_insn); | ||
2887 | + insn_flag_set (EXTELIM_INSERTED, new_uid); | ||
2888 | +} | ||
2889 | + | ||
2890 | +/* Allow the duplication of the extension even if the extension | ||
2891 | + and the duplication use are in the same block. */ | ||
2892 | + | ||
2893 | +static bool | ||
2894 | +allow_same_block_duplication_p (rtx ext_insn, rtx use_insn) | ||
2895 | +{ | ||
2896 | + rtx ext = PATTERN (ext_insn); | ||
2897 | + rtx use = PATTERN (use_insn); | ||
2898 | + | ||
2899 | + if (GET_CODE (SET_SRC (use)) == ASHIFT && GET_CODE (SET_SRC (ext)) == ZERO_EXTEND) | ||
2900 | + return true; | ||
2901 | + return false; | ||
2902 | +} | ||
2903 | + | ||
2904 | +/* Determine if the extension should be duplicated at this use point. | ||
2905 | + Return true if yes, false otherwise. */ | ||
2906 | + | ||
2907 | +static bool | ||
2908 | +save_ext_use_p (ext_record_t extrec, rtx use_insn) | ||
2909 | +{ | ||
2910 | + rtx ext_insn, ext, ext_dest, use = PATTERN (use_insn), use_src; | ||
2911 | + df_ref df_use; | ||
2912 | + | ||
2913 | + ext_insn = extrec->ext; | ||
2914 | + ext = PATTERN (ext_insn); | ||
2915 | + ext_dest = SET_DEST (ext); | ||
2916 | + | ||
2917 | + if (GET_CODE (use) != SET) | ||
2918 | + { | ||
2919 | + if (dump_file) | ||
2920 | + fprintf (dump_file, " no -- use is not a SET code\n"); | ||
2921 | + return false; | ||
2922 | + } | ||
2923 | + | ||
2924 | + /* Check for obviousness */ | ||
2925 | + /* 1. The use is only reached by the a single definition of the extension. | ||
2926 | + Otherwise, it wouldn't be legal to insert a duplicate extension | ||
2927 | + as other defs reaching this use may not need it. Certainly not all | ||
2928 | + other defs may reach here, but this is the conservative approximation. | ||
2929 | + Found in nof/muldf3.c */ | ||
2930 | + df_use = df_find_use (use_insn, ext_dest); | ||
2931 | + if ( df_use && DF_REF_CHAIN (df_use)->next) | ||
2932 | + { | ||
2933 | + if (dump_file) | ||
2934 | + fprintf (dump_file, | ||
2935 | + " no -- there are multiple definitions of reg=%d reaching this use\n", | ||
2936 | + (REGNO (register_exp (ext_dest)))); | ||
2937 | + return false; | ||
2938 | + } | ||
2939 | + | ||
2940 | + /* 2. The extension and use are in the same block. Since | ||
2941 | + this is a reached use, it's obvious we don't need another | ||
2942 | + extension. The exception is this -- we are trying to set | ||
2943 | + up a specific extension,insn pattern that will be recognized | ||
2944 | + by the insn selector. This pattern will also be ignored when | ||
2945 | + the next extension candidate list is created in the next pass. */ | ||
2946 | + if (INSN_P (ext_insn) && INSN_P (use_insn)) | ||
2947 | + { | ||
2948 | + if (BLOCK_FOR_INSN (ext_insn) == BLOCK_FOR_INSN (use_insn)) | ||
2949 | + { | ||
2950 | + if (allow_same_block_duplication_p (ext_insn, use_insn)) | ||
2951 | + ; | ||
2952 | + else | ||
2953 | + { | ||
2954 | + if (dump_file) | ||
2955 | + fprintf (dump_file, | ||
2956 | + " no -- ext and use are in the same block\n"); | ||
2957 | + return false; | ||
2958 | + } | ||
2959 | + } | ||
2960 | + } | ||
2961 | + | ||
2962 | + /* 3. The use is a sign extension of the extension destination reg */ | ||
2963 | + use_src = SET_SRC (use); | ||
2964 | + if (GET_CODE (use_src) == SIGN_EXTEND | ||
2965 | + && REG_P (register_exp (XEXP (use_src, 0))) | ||
2966 | + && REG_P (register_exp (ext_dest))) | ||
2967 | + if (GET_MODE (use_src) == GET_MODE (ext_dest) | ||
2968 | + && REGNO (register_exp (XEXP (use_src, 0))) == | ||
2969 | + REGNO (register_exp (ext_dest))) | ||
2970 | + { | ||
2971 | + if (dump_file) | ||
2972 | + fprintf (dump_file, | ||
2973 | + " no -- the use is a sign extension of reg=%d\n", | ||
2974 | + REGNO (register_exp (XEXP (use_src, 0)))); | ||
2975 | + return false; | ||
2976 | + } | ||
2977 | + | ||
2978 | + /* 4. The use already has an extension inserted and one of the use's operands | ||
2979 | + is a register matching the reaching definition. So don't reinsert the same | ||
2980 | + extension. */ | ||
2981 | + if (insn_flag_p (EXTELIM_INSERTED_FOR, INSN_UID (use_insn))) | ||
2982 | + { | ||
2983 | + df_ref *p_df_uses; | ||
2984 | + /* Operands used by this the use_insn */ | ||
2985 | + for (p_df_uses = DF_INSN_UID_USES (INSN_UID (use_insn)); *p_df_uses; | ||
2986 | + p_df_uses++) | ||
2987 | + { | ||
2988 | + if (REG_P (register_exp (ext_dest)) && | ||
2989 | + DF_REF_REGNO (*p_df_uses) == REGNO (register_exp (ext_dest))) | ||
2990 | + { | ||
2991 | + if (dump_file) | ||
2992 | + fprintf (dump_file, | ||
2993 | + " no -- this use is marked for sign extension insertion already\n"); | ||
2994 | + return false; | ||
2995 | + } | ||
2996 | + } | ||
2997 | + } | ||
2998 | + | ||
2999 | + /* 5. There is also a definition of the ext dest register at this use (as can occur in self assignment). */ | ||
3000 | + if (register_exp (SET_DEST (use)) && REG_P (ext_dest) | ||
3001 | + && REGNO (register_exp (SET_DEST (use))) == REGNO (ext_dest)) | ||
3002 | + { | ||
3003 | + if (dump_file) | ||
3004 | + fprintf (dump_file, | ||
3005 | + " no -- this use also assigns the used register\n"); | ||
3006 | + return false; | ||
3007 | + } | ||
3008 | + | ||
3009 | + | ||
3010 | + if (dump_file) | ||
3011 | + fprintf (dump_file, " yes\n"); | ||
3012 | + return true; | ||
3013 | +} | ||
3014 | + | ||
3015 | +/* Save the use insn in the extension records list of | ||
3016 | + uses. At the next phase, we will duplicate the extension | ||
3017 | + at these use points. */ | ||
3018 | + | ||
3019 | +static void | ||
3020 | +save_ext_use (ext_record_t extrec, rtx use_insn) | ||
3021 | +{ | ||
3022 | + /* Mark the use insn, it will have a duplicate inserted */ | ||
3023 | + insn_flag_set (EXTELIM_INSERTED_FOR, INSN_UID (use_insn)); | ||
3024 | + /* Save use to the list of uses to be duplicated for this extension. */ | ||
3025 | + VEC_safe_push (rtx, heap, extrec->ext_uses, use_insn); | ||
3026 | +} | ||
3027 | + | ||
3028 | + | ||
3029 | +/* Save the qualified use of an extension to a list */ | ||
3030 | + | ||
3031 | +static void | ||
3032 | +gather_ext_uses_info (ext_record_t extrec) | ||
3033 | +{ | ||
3034 | + rtx ext; | ||
3035 | + df_ref *ext_def, df_use; | ||
3036 | + unsigned int def_use_count = 1; | ||
3037 | + extelim_uid_t uid; | ||
3038 | + struct df_link *link; | ||
3039 | + | ||
3040 | + gcc_assert (extrec != NULL); | ||
3041 | + ext = extrec->ext; | ||
3042 | + uid = INSN_UID (ext); | ||
3043 | + | ||
3044 | + /* Insn level defs of the sign extension */ | ||
3045 | + ext_def = DF_INSN_UID_DEFS (uid); | ||
3046 | + /* There is only one def in a sign extension insn */ | ||
3047 | + gcc_assert (*(ext_def + 1) == NULL); | ||
3048 | + | ||
3049 | + /* Iterate over the reached uses of extension destination register. | ||
3050 | + Duplicate the extension at the use point. */ | ||
3051 | + for (link = DF_REF_CHAIN (*ext_def); link; link = link->next) | ||
3052 | + { | ||
3053 | + rtx insn_use; | ||
3054 | + df_use = link->ref; | ||
3055 | + if (!df_use) | ||
3056 | + continue; | ||
3057 | + /* Link must be a USE of the DEF */ | ||
3058 | + if (!DF_REF_REG_USE_P (df_use)) | ||
3059 | + continue; | ||
3060 | + /* Ignore ARTIFICIAL USES */ | ||
3061 | + if (DF_REF_IS_ARTIFICIAL (df_use)) | ||
3062 | + continue; | ||
3063 | + insn_use = DF_REF_INSN (df_use); | ||
3064 | + | ||
3065 | + /* Don't consider debug_insns */ | ||
3066 | + if (!NONDEBUG_INSN_P (insn_use)) | ||
3067 | + continue; | ||
3068 | + | ||
3069 | + if (dump_file) | ||
3070 | + fprintf (dump_file, | ||
3071 | + " use #%d duplicate ext of reg=%d at uid=%u?\n", | ||
3072 | + def_use_count, DF_REF_REGNO (*ext_def), INSN_UID (insn_use)); | ||
3073 | + if (save_ext_use_p (extrec, insn_use)) | ||
3074 | + save_ext_use (extrec, insn_use); | ||
3075 | + def_use_count++; | ||
3076 | + } | ||
3077 | +} | ||
3078 | + | ||
3079 | +/* At each use point of the sign extension, unless the | ||
3080 | + use is obviously already sign extended, insert a | ||
3081 | + sign extension insn before the use. We do this in two | ||
3082 | + passes to avoid confusing the dataflow information. */ | ||
3083 | + | ||
3084 | +static void | ||
3085 | +duplicate_exts_at_uses (void) | ||
3086 | +{ | ||
3087 | + unsigned i, j; | ||
3088 | + ext_record_t extrec; | ||
3089 | + rtx use_insn; | ||
3090 | + | ||
3091 | + /* Get the uses where the extensions will be duplicated */ | ||
3092 | + FOR_EACH_VEC_ELT (ext_record_t, extensions, i, extrec) | ||
3093 | + { | ||
3094 | + if (dump_file) | ||
3095 | + fprintf (dump_file, "gathering extension uid=%u use information\n", | ||
3096 | + INSN_UID (extrec->ext)); | ||
3097 | + gather_ext_uses_info (extrec); | ||
3098 | + } | ||
3099 | + | ||
3100 | + /* Now duplicate the extensions at the appropriate use points */ | ||
3101 | + FOR_EACH_VEC_ELT (ext_record_t, extensions, i, extrec) | ||
3102 | + { | ||
3103 | + if (dump_file) | ||
3104 | + fprintf (dump_file, "extension uid=%u\n", INSN_UID (extrec->ext)); | ||
3105 | + | ||
3106 | + FOR_EACH_VEC_ELT (rtx, extrec->ext_uses, j, use_insn) | ||
3107 | + { | ||
3108 | + if (dump_file) | ||
3109 | + fprintf (dump_file, " duplicated at use uid=%u\n", | ||
3110 | + INSN_UID (use_insn)); | ||
3111 | + insert_duplicate_ext_at_use (extrec->ext, use_insn); | ||
3112 | + } | ||
3113 | + } | ||
3114 | +} | ||
3115 | +#endif /* EXTELIM_DUPLICATE_EXTS_AT_USES */ | ||
3116 | + | ||
3117 | +/* Determine if an instruction is a return insn */ | ||
3118 | + | ||
3119 | +static rtx | ||
3120 | +return_p (rtx rtn_insn) | ||
3121 | +{ | ||
3122 | + rtx rtn = PATTERN (rtn_insn), dest; | ||
3123 | + int i; | ||
3124 | + | ||
3125 | + if (GET_CODE (rtn) != SET) | ||
3126 | + return false; | ||
3127 | + | ||
3128 | + dest = SET_DEST (rtn); | ||
3129 | + | ||
3130 | + /* Is a return value? */ | ||
3131 | + if ((REG_P (dest) || GET_CODE (dest) == PARALLEL) && | ||
3132 | + REG_FUNCTION_VALUE_P (dest)) | ||
3133 | + { | ||
3134 | + /* Simple SET, return the insn */ | ||
3135 | + if (REG_P (dest)) | ||
3136 | + return rtn_insn; | ||
3137 | + /* PARALLEL, find the embedded rtx */ | ||
3138 | + if (GET_CODE (dest) == PARALLEL) | ||
3139 | + for (i = XVECLEN (rtn_insn, 0) - 1; i >= 0; i--) | ||
3140 | + { | ||
3141 | + rtx body = XVECEXP (rtn_insn, 0, i); | ||
3142 | + if (GET_CODE (body) == SET) | ||
3143 | + { | ||
3144 | + dest = SET_DEST (body); | ||
3145 | + if (REG_FUNCTION_VALUE_P (dest)) | ||
3146 | + return body; | ||
3147 | + } | ||
3148 | + } | ||
3149 | + } | ||
3150 | + /* Not a return */ | ||
3151 | + return NULL; | ||
3152 | +} | ||
3153 | + | ||
3154 | +/* Find all return RTLs in the function and save them in | ||
3155 | + a list. */ | ||
3156 | + | ||
3157 | +static bool | ||
3158 | +find_returns (void) | ||
3159 | +{ | ||
3160 | + basic_block bb; | ||
3161 | + rtx insn, rtn_insn; | ||
3162 | + bool found = false; | ||
3163 | + | ||
3164 | + /* For all insns */ | ||
3165 | + FOR_EACH_BB (bb) | ||
3166 | + { | ||
3167 | + FOR_BB_INSNS (bb, insn) | ||
3168 | + { | ||
3169 | + if (!NONDEBUG_INSN_P (insn)) | ||
3170 | + continue; | ||
3171 | + | ||
3172 | + if ((rtn_insn = return_p (insn)) == NULL) | ||
3173 | + { | ||
3174 | + continue; | ||
3175 | + } | ||
3176 | + if (dump_file) | ||
3177 | + fprintf (dump_file, " found return at uid=%u\n", INSN_UID (rtn_insn)); | ||
3178 | + | ||
3179 | + VEC_safe_push (rtx, heap, returns, rtn_insn); | ||
3180 | + found = true; | ||
3181 | + } | ||
3182 | + } | ||
3183 | + | ||
3184 | + return (found); | ||
3185 | +} | ||
3186 | + | ||
3187 | +/* Get the signedness and machine mode of the function */ | ||
3188 | + | ||
3189 | +static bool | ||
3190 | +get_return_info (bool * signed_p, enum machine_mode *return_mode) | ||
3191 | +{ | ||
3192 | + tree rtninfo; | ||
3193 | + | ||
3194 | + if ((rtninfo = DECL_RESULT (current_function_decl)) != NULL) | ||
3195 | + { | ||
3196 | + *signed_p = !TYPE_UNSIGNED (TREE_TYPE (rtninfo)); | ||
3197 | + *return_mode = DECL_MODE (rtninfo); | ||
3198 | + return true; | ||
3199 | + } | ||
3200 | + return false; | ||
3201 | +} | ||
3202 | + | ||
3203 | +/* If the dest mode of the return is larger than | ||
3204 | + the function return mode, we can subreg the return | ||
3205 | + insn to the return mode and extend to the destination. | ||
3206 | + E.g. unsigned, return mode: HImode | ||
3207 | + set (reg/i:DI Y) (reg:DI X) | ||
3208 | + becomes | ||
3209 | + set (reg:DI new) (zero_extend:DI (subreg:HI (reg:DI X))) | ||
3210 | + set (reg/i:DI Y) (reg:DI new) */ | ||
3211 | + | ||
3212 | +static void | ||
3213 | +make_ext_at_rtn (rtx rtn_insn, bool fun_signed_p, enum machine_mode fun_mode) | ||
3214 | +{ | ||
3215 | + rtx rtn = PATTERN (rtn_insn); | ||
3216 | + rtx dest, src, new_ext_dest, new_ext_src, new_ext_outer, new_ext_part, | ||
3217 | + new_ext_insn; | ||
3218 | + extelim_uid_t new_uid; | ||
3219 | + gcc_assert (GET_CODE (rtn) == SET); | ||
3220 | + | ||
3221 | + dest = SET_DEST (rtn); | ||
3222 | + src = SET_SRC (rtn); | ||
3223 | + | ||
3224 | + /* Deal with scalar rtn values only */ | ||
3225 | + if (fun_mode != DImode | ||
3226 | + && fun_mode != SImode && fun_mode != HImode && fun_mode != QImode) | ||
3227 | + { | ||
3228 | + if (dump_file) | ||
3229 | + fprintf (dump_file, "failed-- not scalar return mode\n"); | ||
3230 | + return; | ||
3231 | + } | ||
3232 | + | ||
3233 | + /* Dest and src have to have the same mode. This should always be | ||
3234 | + true for well formed rtl, but we check anyway. */ | ||
3235 | + if (GET_MODE (dest) != GET_MODE (src)) | ||
3236 | + { | ||
3237 | + if (dump_file) | ||
3238 | + fprintf (dump_file, "failed-- dest and src modes differ\n"); | ||
3239 | + return; | ||
3240 | + } | ||
3241 | + | ||
3242 | + /* Also check that we are dealing with simple regs here. */ | ||
3243 | + if (!REG_P (dest) || !REG_P (src)) | ||
3244 | + { | ||
3245 | + if (dump_file) | ||
3246 | + fprintf (dump_file, "failed-- dest or src is not REG_P\n"); | ||
3247 | + return; | ||
3248 | + } | ||
3249 | + | ||
3250 | + /* The return reg mode should never be smaller than fun return mode. If the | ||
3251 | + same size, however, we can't subreg either, so return */ | ||
3252 | + if (GET_MODE_BITSIZE (GET_MODE (dest)) <= GET_MODE_BITSIZE (fun_mode)) | ||
3253 | + { | ||
3254 | + if (dump_file) | ||
3255 | + fprintf (dump_file, | ||
3256 | + "failed-- dest size mode is smaller or equal to function mode size\n"); | ||
3257 | + return; | ||
3258 | + } | ||
3259 | + | ||
3260 | + /* From here we should be able to build a subreg since the function return mode | ||
3261 | + size is smaller than the return register mode size */ | ||
3262 | + new_ext_dest = gen_reg_rtx (GET_MODE (src)); /* set (reg:MM new) */ | ||
3263 | + new_ext_src = copy_rtx (src); /* copy of X, copyX */ | ||
3264 | + new_ext_outer = gen_lowpart_SUBREG (fun_mode, new_ext_src); /* subreg:mm (reg:MM copyX) */ | ||
3265 | + new_ext_part = fun_signed_p /* extend:MM (subreg:mm (reg:MM copyX)) */ | ||
3266 | + ? gen_rtx_SIGN_EXTEND (GET_MODE (src), new_ext_outer) | ||
3267 | + : gen_rtx_ZERO_EXTEND (GET_MODE (src), new_ext_outer); | ||
3268 | + /* Put it together */ | ||
3269 | + new_ext_insn = gen_rtx_SET (VOIDmode, new_ext_dest, new_ext_part); | ||
3270 | + | ||
3271 | + /* Modify src of return insn to use new pseudo */ | ||
3272 | + replace_rtx (PATTERN (rtn_insn), src, new_ext_dest); | ||
3273 | + /* Update flags on new dest reg */ | ||
3274 | + copy_flags (src, new_ext_dest); | ||
3275 | + /* Update any notes associated with replaced register */ | ||
3276 | + update_notes (REG_DEAD, rtn_insn, src, new_ext_dest); | ||
3277 | + /* Rescan the modified insn */ | ||
3278 | + df_insn_rescan (rtn_insn); | ||
3279 | + /* Insert the new insn */ | ||
3280 | + new_uid = extelim_emit_before (new_ext_insn, rtn_insn); | ||
3281 | + | ||
3282 | + if (dump_file) | ||
3283 | + fprintf (dump_file, "success\n"); | ||
3284 | +} | ||
3285 | + | ||
3286 | +/* Insert extensions at return points. Scan the RTL | ||
3287 | + for the return statements. Determine if the RTL | ||
3288 | + can be modified to insert an extension. Modify the | ||
3289 | + return to insert the extension. */ | ||
3290 | + | ||
3291 | +static void | ||
3292 | +insert_ext_at_returns (void) | ||
3293 | +{ | ||
3294 | + bool signed_p; | ||
3295 | + enum machine_mode return_mode; | ||
3296 | + rtx rtn_insn; | ||
3297 | + int i; | ||
3298 | + | ||
3299 | + /* Generate list of return rtls for the function */ | ||
3300 | + if (dump_file) | ||
3301 | + fprintf (dump_file, "gathering return insns...\n"); | ||
3302 | + | ||
3303 | + if (!find_returns ()) | ||
3304 | + return; | ||
3305 | + | ||
3306 | + if (!get_return_info (&signed_p, &return_mode)) | ||
3307 | + return; | ||
3308 | + | ||
3309 | + /* For each return instruction, generate a sign/zero extend | ||
3310 | + if the current return size is larger than the function | ||
3311 | + return mode. */ | ||
3312 | + FOR_EACH_VEC_ELT (rtx, returns, i, rtn_insn) | ||
3313 | + { | ||
3314 | + if (dump_file) | ||
3315 | + fprintf (dump_file, " making extension at return uid=%u...", | ||
3316 | + INSN_UID (rtn_insn)); | ||
3317 | + make_ext_at_rtn (rtn_insn, signed_p, return_mode); | ||
3318 | + } | ||
3319 | +} | ||
3320 | + | ||
3321 | +/* Compare two extension records by loop depth. | ||
3322 | + Used by VEC_qsort to sort the order in which extensions | ||
3323 | + are processed. */ | ||
3324 | + | ||
3325 | +static int | ||
3326 | +ext_record_compare (const void *p_er1, const void *p_er2) | ||
3327 | +{ | ||
3328 | + const ext_record_t er1 = *(const ext_record_t *) p_er1; | ||
3329 | + const ext_record_t er2 = *(const ext_record_t *) p_er2; | ||
3330 | + basic_block bb1, bb2; | ||
3331 | + rtx ext1, ext2; | ||
3332 | + | ||
3333 | + if (er1 == er2) | ||
3334 | + return 0; | ||
3335 | + | ||
3336 | + ext1 = er1->ext; | ||
3337 | + ext2 = er2->ext; | ||
3338 | + | ||
3339 | + bb1 = BLOCK_FOR_INSN (ext1); | ||
3340 | + bb2 = BLOCK_FOR_INSN (ext2); | ||
3341 | + | ||
3342 | + /* Sort high to low */ | ||
3343 | + return (bb2->loop_depth - bb1->loop_depth); | ||
3344 | +} | ||
3345 | + | ||
3346 | +/* The main interface to this optimization. */ | ||
3347 | + | ||
3348 | +static void | ||
3349 | +extension_elimination (void) | ||
3350 | +{ | ||
3351 | + ext_record_t ext; | ||
3352 | + unsigned i; | ||
3353 | + | ||
3354 | + init_pass (); | ||
3355 | + | ||
3356 | + /* Find initial sign extension candidates */ | ||
3357 | + if (!find_extensions ()) | ||
3358 | + { | ||
3359 | + finish_pass (); | ||
3360 | + return; | ||
3361 | + } | ||
3362 | + | ||
3363 | + /* Insert sign extension at return points in | ||
3364 | + the function. */ | ||
3365 | + insert_ext_at_returns (); | ||
3366 | + | ||
3367 | + /* Duplicate the sign extensions at their use | ||
3368 | + points unless the use is already obviously sign | ||
3369 | + extended or extension is already added. */ | ||
3370 | +#if EXTELIM_DUPLICATE_EXTS_AT_USES | ||
3371 | + duplicate_exts_at_uses (); | ||
3372 | +#endif | ||
3373 | + | ||
3374 | + /* Update DF information since now have new insns. */ | ||
3375 | + df_finish_pass (true); | ||
3376 | + df_chain_add_problem (DF_DU_CHAIN + DF_UD_CHAIN); | ||
3377 | + df_analyze (); | ||
3378 | + | ||
3379 | +#if EXTELIM_DF_DUMP | ||
3380 | + if (dump_file) | ||
3381 | + df_dump (dump_file); | ||
3382 | +#endif | ||
3383 | + | ||
3384 | + /* Init statistics */ | ||
3385 | + num_cand = 0; | ||
3386 | + num_cand_ignored = 0; | ||
3387 | + num_cand_transformed = 0; | ||
3388 | + | ||
3389 | + /* Free old extensions list, generate new one that includes | ||
3390 | + the new extensions. */ | ||
3391 | + free_extensions (); | ||
3392 | + | ||
3393 | + if (!find_extensions ()) | ||
3394 | + { | ||
3395 | + finish_pass (); | ||
3396 | + return; | ||
3397 | + } | ||
3398 | + | ||
3399 | + if (dump_file) | ||
3400 | + { | ||
3401 | + fprintf (dump_file, "\nRTL After Extension Duplication\n"); | ||
3402 | + print_rtl (dump_file, get_insns ()); | ||
3403 | + } | ||
3404 | + | ||
3405 | + if (dump_file) | ||
3406 | + fprintf (dump_file, "Begin extension elimination analysis\n"); | ||
3407 | + | ||
3408 | + /* Sort the extensions by loop depth. We want to try to eliminate | ||
3409 | + those in innermost loops (highest loop depth) first. */ | ||
3410 | + VEC_qsort (ext_record_t, extensions, ext_record_compare); | ||
3411 | + | ||
3412 | + /* Iterate through extension worklist */ | ||
3413 | + FOR_EACH_VEC_ELT (ext_record_t, extensions, i, ext) | ||
3414 | + { | ||
3415 | + rtx ext_insn = ext->ext; | ||
3416 | + rtx ext_src = SET_SRC (PATTERN (ext_insn)); | ||
3417 | + const char *ext_name = | ||
3418 | + GET_CODE (ext_src) == SIGN_EXTEND ? "sign" : "zero"; | ||
3419 | + const char *inserted = | ||
3420 | + insn_flag_p (EXTELIM_INSERTED, INSN_UID (ext_insn)) ? "inserted" : ""; | ||
3421 | + extelim_uid_t uid = INSN_UID (ext_insn); | ||
3422 | + | ||
3423 | + if (dump_file) | ||
3424 | + fprintf (dump_file, | ||
3425 | + "<analyzing %s %s extension uid=%u> (loop_depth=%d)\n", | ||
3426 | + inserted, ext_name, uid, | ||
3427 | + BLOCK_FOR_INSN (ext_insn)->loop_depth); | ||
3428 | + | ||
3429 | + current_ext_record = ext; | ||
3430 | + eliminate_one_extend (ext->ext); | ||
3431 | + } | ||
3432 | + | ||
3433 | + if (dump_file) | ||
3434 | + fprintf (dump_file, "Begin extension elimination transformations\n"); | ||
3435 | + | ||
3436 | + replace_ext_with_copy (); | ||
3437 | + | ||
3438 | + if (dump_file) | ||
3439 | + fprintf (dump_file, "\nRTL After Extension Elimination\n"); | ||
3440 | + | ||
3441 | + finish_pass (); | ||
3442 | + | ||
3443 | + /* Print statistics */ | ||
3444 | + if (dump_file) | ||
3445 | + { | ||
3446 | + fprintf (dump_file, | ||
3447 | + "Number of extensions ignored: %d (of %d candidiates)\nDETECTION EFFECTIVENESS: %f%%\n", | ||
3448 | + num_cand_ignored, num_cand, | ||
3449 | + ((float) (num_cand - num_cand_ignored) / (float) num_cand) * | ||
3450 | + 100); | ||
3451 | + fprintf (dump_file, | ||
3452 | + "Number of extensions converted to copy: %d (of %d candidiates)\nCONVERSION EFFECTIVENESS: %f%%\n", | ||
3453 | + num_cand_transformed, num_cand, | ||
3454 | + ((float) num_cand_transformed / (float) num_cand) * 100); | ||
3455 | + } | ||
3456 | +} | ||
3457 | + | ||
3458 | +/* Remove redundant extensions. */ | ||
3459 | + | ||
3460 | +static unsigned int | ||
3461 | +rest_of_handle_extelim (void) | ||
3462 | +{ | ||
3463 | + extension_elimination (); | ||
3464 | + return 0; | ||
3465 | +} | ||
3466 | + | ||
3467 | +/* Run extelim pass when flag_extelim is set at optimization level > 0. */ | ||
3468 | + | ||
3469 | +static bool | ||
3470 | +gate_handle_extelim (void) | ||
3471 | +{ | ||
3472 | + return (optimize > 0 && flag_extelim); | ||
3473 | +} | ||
3474 | + | ||
3475 | +struct rtl_opt_pass pass_rtl_extelim = { | ||
3476 | + { | ||
3477 | + RTL_PASS, | ||
3478 | + "extelim", /* name */ | ||
3479 | + gate_handle_extelim, /* gate */ | ||
3480 | + rest_of_handle_extelim, /* execute */ | ||
3481 | + NULL, /* sub */ | ||
3482 | + NULL, /* next */ | ||
3483 | + 0, /* static_pass_number */ | ||
3484 | + TV_EXTELIM, /* tv_id */ | ||
3485 | + 0, /* properties_required */ | ||
3486 | + 0, /* properties_provided */ | ||
3487 | + 0, /* properties_destroyed */ | ||
3488 | + 0, /* todo_flags_start */ | ||
3489 | + TODO_ggc_collect | TODO_dump_func | TODO_df_finish | TODO_verify_rtl_sharing, /* todo_flags_finish */ | ||
3490 | + } | ||
3491 | +}; | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_MTWX51204-dwarf-vector-reg.patch b/recipes-devtools/gcc/files/gcc.fix_MTWX51204-dwarf-vector-reg.patch new file mode 100644 index 0000000..cb34859 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_MTWX51204-dwarf-vector-reg.patch | |||
@@ -0,0 +1,9 @@ | |||
1 | diff -Naur gcc-4.6.2/gcc/config/rs6000/sysv4.h gcc-4.6.2-MTWX51204-dwarf-vector-reg/gcc/config/rs6000/sysv4.h | ||
2 | --- gcc-4.6.2/gcc/config/rs6000/sysv4.h 2011-03-07 01:50:23.000000000 -0600 | ||
3 | +++ gcc-4.6.2-MTWX51204-dwarf-vector-reg/gcc/config/rs6000/sysv4.h 2011-12-16 09:44:18.469039002 -0600 | ||
4 | @@ -1035,5 +1035,3 @@ | ||
5 | |||
6 | /* This target uses the sysv4.opt file. */ | ||
7 | #define TARGET_USES_SYSV4_OPT 1 | ||
8 | - | ||
9 | -#undef DBX_REGISTER_NUMBER | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_SSIZE_MAX_undefine_issue.patch b/recipes-devtools/gcc/files/gcc.fix_SSIZE_MAX_undefine_issue.patch new file mode 100644 index 0000000..51dc558 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_SSIZE_MAX_undefine_issue.patch | |||
@@ -0,0 +1,11 @@ | |||
1 | --- gcc-4_6-branch/gcc/config/host-linux.c.orig 2012-03-08 02:18:57.282190580 -0600 | ||
2 | +++ gcc-4_6-branch/gcc/config/host-linux.c 2012-03-08 02:19:30.930158694 -0600 | ||
3 | @@ -17,6 +17,8 @@ | ||
4 | along with GCC; see the file COPYING3. If not see | ||
5 | <http://www.gnu.org/licenses/>. */ | ||
6 | |||
7 | +#include <bits/posix1_lim.h> | ||
8 | + | ||
9 | #include "config.h" | ||
10 | #include "system.h" | ||
11 | #include "coretypes.h" | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_build-with-cxx.patch b/recipes-devtools/gcc/files/gcc.fix_build-with-cxx.patch new file mode 100644 index 0000000..cfceafd --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_build-with-cxx.patch | |||
@@ -0,0 +1,39 @@ | |||
1 | gcc.fix_build-with-cxx | ||
2 | |||
3 | On native builds, when linking cc1 with static libraries (ppl cloog, | ||
4 | gmp, mpfr), there is c++ code brought in by libppl. Normally cc1 is | ||
5 | linked through "gcc", but in this case it should be linked with "g++". | ||
6 | |||
7 | To work around this, gcc is configured with --enable-build-with-cxx, | ||
8 | which compiles and links the entire compiler with g++. Since g++ is | ||
9 | more rigorous about the use of the "const" keyword, there is a couple | ||
10 | of places that we get syntax errors. This patch fixes them. | ||
11 | |||
12 | --- gcc-4.6.0/gcc/config/rs6000/rs6000.c-orig 2011-05-09 10:35:55.627190744 -0500 | ||
13 | +++ gcc-4.6.0/gcc/config/rs6000/rs6000.c 2011-05-09 10:39:09.232814653 -0500 | ||
14 | @@ -22502,11 +22502,12 @@ | ||
15 | rs6000_xcoff_strip_dollar (const char *name) | ||
16 | { | ||
17 | char *strip, *p; | ||
18 | + const char *q; | ||
19 | int len; | ||
20 | |||
21 | - p = strchr (name, '$'); | ||
22 | + q = strchr (name, '$'); | ||
23 | |||
24 | - if (p == 0 || p == name) | ||
25 | + if (q == 0 || q == name) | ||
26 | return name; | ||
27 | |||
28 | len = strlen (name); | ||
29 | --- gcc-4.6.0/gcc/objc/objc-next-runtime-abi-02.c-orig 2011-05-11 13:46:44.559065173 -0500 | ||
30 | +++ gcc-4.6.0/gcc/objc/objc-next-runtime-abi-02.c 2011-05-11 13:48:34.956939829 -0500 | ||
31 | @@ -1878,7 +1878,7 @@ | ||
32 | static const char * | ||
33 | newabi_append_ro (const char *name) | ||
34 | { | ||
35 | - char *dollar; | ||
36 | + const char *dollar; | ||
37 | char *p; | ||
38 | static char string[BUFSIZE]; | ||
39 | dollar = strchr (name, '$'); | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_cloogstatic2.patch b/recipes-devtools/gcc/files/gcc.fix_cloogstatic2.patch new file mode 100644 index 0000000..afa29d9 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_cloogstatic2.patch | |||
@@ -0,0 +1,18 @@ | |||
1 | gcc.fix_cloogstatic2 | ||
2 | |||
3 | When only static libraries are available (so we can build cc1 without | ||
4 | depending on extras libraries), we get a bunch of undefined symbols | ||
5 | that are defined in libpwl. This patch explicitly adds libpwl to the | ||
6 | linker command. | ||
7 | |||
8 | --- gcc-trunk/configure.orig 2011-03-10 12:48:29.433528020 -0600 | ||
9 | +++ gcc-trunk/configure 2011-03-10 12:52:11.342145967 -0600 | ||
10 | @@ -5770,7 +5770,7 @@ | ||
11 | LDFLAGS="$saved_LDFLAGS" | ||
12 | fi | ||
13 | |||
14 | - ppllibs="$ppllibs -lppl_c -lppl $pwllib -lgmpxx" | ||
15 | + ppllibs="$ppllibs -lppl_c -lppl -lpwl $pwllib -lgmpxx" | ||
16 | |||
17 | if test "$enable_ppl_version_check" != no; then | ||
18 | saved_CFLAGS="$CFLAGS" | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_constvector.patch b/recipes-devtools/gcc/files/gcc.fix_constvector.patch new file mode 100644 index 0000000..c4a2776 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_constvector.patch | |||
@@ -0,0 +1,43 @@ | |||
1 | For altivec targets, 32 bits, the spec2k-gap bmk does not build. The | ||
2 | reason is that at some point the vectorizer creates an CONST_VECTOR | ||
3 | rtl, where the elements are SYMBOL_REFs. | ||
4 | |||
5 | Gcc ICE on simplify_immed_subreg, where it checks that CONST_VECTORS | ||
6 | can be only made of CONST_INT, CONST_DOUBLE, or CONST_FIXED. | ||
7 | |||
8 | I really don't understand what that function does, but since the | ||
9 | vectorizer will bailout later anyway, I think it is safe to treat | ||
10 | SYMBOL_REFs as CONST_INT. (NOT for FSF submission, as I really don't | ||
11 | have a clue) | ||
12 | |||
13 | This problem does not exists on gcc-4.5 | ||
14 | |||
15 | This problem does not exists on 64 bits, since there is no altivec | ||
16 | type that can support 64bit elements. | ||
17 | |||
18 | Here is a simplified test case: | ||
19 | |||
20 | typedef void f_t (void); | ||
21 | extern f_t f; | ||
22 | extern f_t *A[12]; | ||
23 | extern f_t *B[12]; | ||
24 | void bad_vector () | ||
25 | { | ||
26 | int i; | ||
27 | |||
28 | for (i = 0; i < 12; i++ ) { | ||
29 | A[i] = f; | ||
30 | B[i] = f; | ||
31 | } | ||
32 | } | ||
33 | |||
34 | --- gcc-4.6.2/gcc/simplify-rtx.c~ 2011-12-28 12:28:01.700039002 -0600 | ||
35 | +++ gcc-4.6.2/gcc/simplify-rtx.c 2011-12-28 12:38:22.287039002 -0600 | ||
36 | @@ -5001,6 +5001,7 @@ | ||
37 | switch (GET_CODE (el)) | ||
38 | { | ||
39 | case CONST_INT: | ||
40 | + case SYMBOL_REF: | ||
41 | for (i = 0; | ||
42 | i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize; | ||
43 | i += value_bit) | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_header_issue.patch b/recipes-devtools/gcc/files/gcc.fix_header_issue.patch new file mode 100644 index 0000000..e2b9f7f --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_header_issue.patch | |||
@@ -0,0 +1,12 @@ | |||
1 | --- gcc-4_6-branch/gcc/limitx.h.orig 2012-03-08 01:11:23.024440826 -0600 | ||
2 | +++ gcc-4_6-branch/gcc/limitx.h 2012-03-08 01:13:44.372515706 -0600 | ||
3 | @@ -30,6 +30,7 @@ | ||
4 | #define _GCC_LIMITS_H_ | ||
5 | |||
6 | #ifndef _LIBC_LIMITS_H_ | ||
7 | -/* Use "..." so that we find syslimits.h only in this same directory. */ | ||
8 | -#include "syslimits.h" | ||
9 | +#define _GCC_NEXT_LIMITS_H /* tell gcc's limits.h to recurse */ | ||
10 | +#include_next <limits.h> | ||
11 | +#undef _GCC_NEXT_LIMITS_H | ||
12 | #endif | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_ira-loop-pressure.patch b/recipes-devtools/gcc/files/gcc.fix_ira-loop-pressure.patch new file mode 100644 index 0000000..86ad32a --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_ira-loop-pressure.patch | |||
@@ -0,0 +1,12 @@ | |||
1 | diff -Naur gcc-4.6.2/gcc/config/rs6000/rs6000.c gcc-4.6.2-loop_invariant/gcc/config/rs6000/rs6000.c | ||
2 | --- gcc-4.6.2/gcc/config/rs6000/rs6000.c 2011-11-24 00:03:49.709144001 -0600 | ||
3 | +++ gcc-4.6.2-loop_invariant/gcc/config/rs6000/rs6000.c 2011-12-12 23:49:27.901487730 -0600 | ||
4 | @@ -2723,7 +2723,7 @@ | ||
5 | calculation works better for RTL loop invariant motion on targets | ||
6 | with enough (>= 32) registers. It is an expensive optimization. | ||
7 | So it is on only for peak performance. */ | ||
8 | - if (optimize >= 3 && global_init_p) | ||
9 | + if (optimize >= 3 && global_init_p && !global_options_set.x_flag_ira_loop_pressure) | ||
10 | flag_ira_loop_pressure = 1; | ||
11 | |||
12 | /* Set the pointer size. */ | ||
diff --git a/recipes-devtools/gcc/files/gcc.fix_longversionstring.patch b/recipes-devtools/gcc/files/gcc.fix_longversionstring.patch new file mode 100644 index 0000000..2d7fae7 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_longversionstring.patch | |||
@@ -0,0 +1,16 @@ | |||
1 | gcc.fix_longversionstring | ||
2 | |||
3 | Freescale version string is really long, and it can overflow a | ||
4 | buffer. This patch extends the size of the buffer. | ||
5 | |||
6 | --- gcc-4.6.0/gcc/dwarf2out.c-orig 2011-03-18 11:22:01.000000000 -0500 | ||
7 | +++ gcc-4.6.0/gcc/dwarf2out.c 2011-05-06 10:24:24.114277925 -0500 | ||
8 | @@ -20005,7 +20005,7 @@ | ||
9 | gen_compile_unit_die (const char *filename) | ||
10 | { | ||
11 | dw_die_ref die; | ||
12 | - char producer[250]; | ||
13 | + char producer[2500]; | ||
14 | const char *language_string = lang_hooks.name; | ||
15 | int language; | ||
16 | |||
diff --git a/recipes-devtools/gcc/files/gcc.fix_mingw32.patch b/recipes-devtools/gcc/files/gcc.fix_mingw32.patch new file mode 100644 index 0000000..0d8c00e --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.fix_mingw32.patch | |||
@@ -0,0 +1,11 @@ | |||
1 | --- gcc-4.6.0/gcc/configure~ 2011-02-28 09:36:37.000000000 -0600 | ||
2 | +++ gcc-4.6.0/gcc/configure 2011-06-28 10:07:22.430630818 -0500 | ||
3 | @@ -10898,7 +10898,7 @@ | ||
4 | saved_CFLAGS="${CFLAGS}" | ||
5 | CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \ | ||
6 | LDFLAGS="${LDFLAGS_FOR_BUILD}" \ | ||
7 | - ${realsrcdir}/configure \ | ||
8 | + ${realsrcdir}/configure --with-gnu-ld --with-gnu-as --enable-targets=all \ | ||
9 | --enable-languages=${enable_languages-all} \ | ||
10 | --target=$target_alias --host=$build_alias --build=$build_alias | ||
11 | CFLAGS="${saved_CFLAGS}" | ||
diff --git a/recipes-devtools/gcc/files/gcc.ld_unaligned-460.patch b/recipes-devtools/gcc/files/gcc.ld_unaligned-460.patch new file mode 100644 index 0000000..2eb270e --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.ld_unaligned-460.patch | |||
@@ -0,0 +1,32 @@ | |||
1 | gcc.ld_unaligned-460 | ||
2 | |||
3 | Optimization: | ||
4 | Allows a "ld" of an address that is world aligned. There is a penalty | ||
5 | performance, but it still beats a pair of "lwz". | ||
6 | |||
7 | Index: gcc-4.4-e500mc64-20090322/gcc/config/rs6000/rs6000.c | ||
8 | =================================================================== | ||
9 | --- gcc-4.4-e500mc64-20090322/gcc/config/rs6000/rs6000.c (revision 137727) | ||
10 | +++ gcc-4.4-e500mc64-20090322/gcc/config/rs6000/rs6000.c (working copy) | ||
11 | @@ -10640,7 +10667,9 @@ | ||
12 | else if (bytes >= 8 && TARGET_POWERPC64 | ||
13 | /* 64-bit loads and stores require word-aligned | ||
14 | displacements. */ | ||
15 | - && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | ||
16 | + && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32) | ||
17 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
18 | + || rs6000_cpu == PROCESSOR_PPCE6500)) | ||
19 | { | ||
20 | clear_bytes = 8; | ||
21 | mode = DImode; | ||
22 | @@ -10775,7 +10808,9 @@ | ||
23 | else if (bytes >= 8 && TARGET_POWERPC64 | ||
24 | /* 64-bit loads and stores require word-aligned | ||
25 | displacements. */ | ||
26 | - && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | ||
27 | + && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32) | ||
28 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
29 | + || rs6000_cpu == PROCESSOR_PPCE6500)) | ||
30 | { | ||
31 | move_bytes = 8; | ||
32 | mode = DImode; | ||
diff --git a/recipes-devtools/gcc/files/gcc.load_on_store_bypass-462.patch b/recipes-devtools/gcc/files/gcc.load_on_store_bypass-462.patch new file mode 100644 index 0000000..a03a7ff --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.load_on_store_bypass-462.patch | |||
@@ -0,0 +1,138 @@ | |||
1 | |||
2 | This patch implements option -fbypass-load-on-store | ||
3 | |||
4 | A load on store collision causes the load to to be replayed if the store has not completed. | ||
5 | Under -fbypass-load-on-store, GCC will attempt to avoid a load on store collision by trying | ||
6 | to space the load away from the store by scheduling upto 14 instructions in between, to | ||
7 | prevent the load from executing too early. | ||
8 | |||
9 | -fbypass-load-on-store is enabled under -fschedule-insns | ||
10 | |||
11 | Cores supported: e5500, e6500, e500mc | ||
12 | |||
13 | Ref: Load-on-Store Collision Avoidance by Software Stall of Load. James Yang. May 18, 2010 | ||
14 | |||
15 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/common.opt fsl-gcc-4.6.2-new-bypass/gcc/common.opt | ||
16 | --- fsl-gcc-4.6.2-sans-bypass/gcc/common.opt 2011-11-29 11:10:18.967872292 -0600 | ||
17 | +++ fsl-gcc-4.6.2-new-bypass/gcc/common.opt 2011-11-29 14:02:46.765994436 -0600 | ||
18 | @@ -840,6 +840,10 @@ | ||
19 | Common Report Var(flag_btr_bb_exclusive) Optimization | ||
20 | Restrict target load migration not to re-use registers in any basic block | ||
21 | |||
22 | +fbypass-load-on-store | ||
23 | +Common Report Var(flag_bypass_load_on_store) Optimization | ||
24 | +Bypass load on store collision | ||
25 | + | ||
26 | fcall-saved- | ||
27 | Common Joined RejectNegative Var(common_deferred_options) Defer | ||
28 | -fcall-saved-<register> Mark <register> as being preserved across functions | ||
29 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e500mc64.md fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e500mc64.md | ||
30 | --- fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e500mc64.md 2011-11-29 11:11:38.454868780 -0600 | ||
31 | +++ fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e500mc64.md 2011-11-29 17:10:39.849869060 -0600 | ||
32 | @@ -189,3 +189,5 @@ | ||
33 | (and (eq_attr "type" "ddiv") | ||
34 | (eq_attr "cpu" "ppce500mc64")) | ||
35 | "e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*34") | ||
36 | + | ||
37 | +(define_bypass 15 "e500mc64_store" "e500mc64_load" "rs6000_bypass_load_on_store_collision_p") | ||
38 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e500mc.md fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e500mc.md | ||
39 | --- fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e500mc.md 2011-11-29 11:11:38.479869032 -0600 | ||
40 | +++ fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e500mc.md 2011-11-29 17:10:27.810997020 -0600 | ||
41 | @@ -198,3 +198,5 @@ | ||
42 | (and (eq_attr "type" "ddiv") | ||
43 | (eq_attr "cpu" "ppce500mc")) | ||
44 | "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65") | ||
45 | + | ||
46 | +(define_bypass 15 "e500mc_store" "e500mc_load" "rs6000_bypass_load_on_store_collision_p") | ||
47 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e5500.md fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e5500.md | ||
48 | --- fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e5500.md 2011-11-29 11:11:38.321744639 -0600 | ||
49 | +++ fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e5500.md 2011-11-29 17:10:47.255997293 -0600 | ||
50 | @@ -174,3 +174,5 @@ | ||
51 | (and (eq_attr "type" "cr_logical,delayed_cr") | ||
52 | (eq_attr "cpu" "ppce5500")) | ||
53 | "e5500_decode,e5500_bu") | ||
54 | + | ||
55 | +(define_bypass 15 "e5500_store" "e5500_load" "rs6000_bypass_load_on_store_collision_p") | ||
56 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e6500.md fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e6500.md | ||
57 | --- fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/e6500.md 2011-11-29 11:11:37.831996567 -0600 | ||
58 | +++ fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/e6500.md 2011-11-29 17:11:00.902869709 -0600 | ||
59 | @@ -211,3 +211,5 @@ | ||
60 | (and (eq_attr "type" "vecperm") | ||
61 | (eq_attr "cpu" "ppce6500")) | ||
62 | "e6500_decode,e6500_vecperm") | ||
63 | + | ||
64 | +(define_bypass 15 "e6500_store" "e6500_load" "rs6000_bypass_load_on_store_collision_p") | ||
65 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/rs6000.c fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/rs6000.c | ||
66 | --- fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/rs6000.c 2011-11-29 11:11:38.393748363 -0600 | ||
67 | +++ fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/rs6000.c 2011-11-29 17:10:15.740745470 -0600 | ||
68 | @@ -28719,3 +28719,20 @@ | ||
69 | |||
70 | |||
71 | #include "gt-rs6000.h" | ||
72 | + | ||
73 | +bool | ||
74 | +rs6000_bypass_load_on_store_collision_p (rtx out_insn, rtx in_insn) | ||
75 | +{ | ||
76 | + /* The out_insn is a store and the in_insn is a load */ | ||
77 | + if (flag_bypass_load_on_store && | ||
78 | + (GET_CODE (PATTERN (out_insn)) == SET && | ||
79 | + GET_CODE (SET_DEST (PATTERN (out_insn))) == MEM && | ||
80 | + GET_CODE (SET_SRC (PATTERN (out_insn))) == REG) && | ||
81 | + (GET_CODE (PATTERN (in_insn)) == SET && | ||
82 | + GET_CODE (SET_DEST (PATTERN (in_insn))) == REG && | ||
83 | + GET_CODE (SET_SRC (PATTERN (in_insn))) == MEM)) | ||
84 | + return rtx_equal_p (SET_DEST (PATTERN (out_insn)), | ||
85 | + SET_SRC (PATTERN (in_insn))); | ||
86 | + else | ||
87 | + return false; | ||
88 | +} | ||
89 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/rs6000-protos.h fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/rs6000-protos.h | ||
90 | --- fsl-gcc-4.6.2-sans-bypass/gcc/config/rs6000/rs6000-protos.h 2011-11-29 11:11:37.783996630 -0600 | ||
91 | +++ fsl-gcc-4.6.2-new-bypass/gcc/config/rs6000/rs6000-protos.h 2011-11-29 17:42:51.443119385 -0600 | ||
92 | @@ -174,6 +174,8 @@ | ||
93 | |||
94 | extern void rs6000_aix_asm_output_dwarf_table_ref (char *); | ||
95 | |||
96 | +extern bool rs6000_bypass_load_on_store_collision_p (rtx out_insn, rtx in_insn); | ||
97 | + | ||
98 | /* Declare functions in rs6000-c.c */ | ||
99 | |||
100 | extern void rs6000_pragma_longcall (struct cpp_reader *); | ||
101 | diff -ruN fsl-gcc-4.6.2-sans-bypass/gcc/testsuite/gcc.target/powerpc/bypass-load-on-store.c fsl-gcc-4.6.2-new-bypass/gcc/testsuite/gcc.target/powerpc/bypass-load-on-store.c | ||
102 | --- fsl-gcc-4.6.2-sans-bypass/gcc/testsuite/gcc.target/powerpc/bypass-load-on-store.c 1969-12-31 18:00:00.000000000 -0600 | ||
103 | +++ fsl-gcc-4.6.2-new-bypass/gcc/testsuite/gcc.target/powerpc/bypass-load-on-store.c 2011-11-30 16:36:55.168869498 -0600 | ||
104 | @@ -0,0 +1,34 @@ | ||
105 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
106 | +/* { dg-options "-O0 -fschedule-insns -fbypass-load-on-store -fdump-rtl-sched1 -fsched-verbose=2" } */ | ||
107 | + | ||
108 | +void nescaf(void) | ||
109 | +{ | ||
110 | + long a, b, c, d, | ||
111 | + e, f, g, h, | ||
112 | + i, j, k, l, | ||
113 | + m, n, o, p, | ||
114 | + q, r, s, t, | ||
115 | + | ||
116 | + z, w; | ||
117 | + | ||
118 | + a = 41; b = 79; c = 20; d = 11; | ||
119 | + e = 13; f = 43; g = 13; h = 21; | ||
120 | + i = 12; j = 45; k = 55; l = 90; | ||
121 | + m = 23; n = 61; o = 89; p = 53; | ||
122 | + q = 83; r = 52; s = 76; t = 99; | ||
123 | + | ||
124 | + /* Now, we have a store followed by a load. The assignments to a-t are | ||
125 | + * all independent of the store-load computation below. The question is: | ||
126 | + * Under -fschedule-insns -fbypass-load-on-store, are 14 of the above | ||
127 | + * instructions moved between the store-load? | ||
128 | + */ | ||
129 | + z = 121; | ||
130 | + w = z; | ||
131 | +} | ||
132 | + | ||
133 | +/* Note: There is going to be exactly one insn that will be assigned cost 15. | ||
134 | + * Since its insn-number will likely change, we do not include the insn | ||
135 | + * number in the scan - just the part of the dump that'll be invariant. | ||
136 | + */ | ||
137 | +/* { dg-final { scan-rtl-dump "into queue with cost=15" "sched1" { target powerpc*-*-* } } } */ | ||
138 | +/* { dg-final { cleanup-rtl-dump "sched1" } } */ | ||
diff --git a/recipes-devtools/gcc/files/gcc.local_unaligned_altivec.patch b/recipes-devtools/gcc/files/gcc.local_unaligned_altivec.patch new file mode 100644 index 0000000..feee54a --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.local_unaligned_altivec.patch | |||
@@ -0,0 +1,18 @@ | |||
1 | gcc.local_unaligned_altivec | ||
2 | |||
3 | Optimization: | ||
4 | On Altivec targets, make all char arrays 128 bits aligned (instead of | ||
5 | 32 bits aligned) | ||
6 | |||
7 | --- gcc-4.5.0/gcc/config/rs6000/rs6000.h-orig 2010-10-20 10:23:52.000000000 -0500 | ||
8 | +++ gcc-4.5.0/gcc/config/rs6000/rs6000.h 2010-10-20 10:39:14.000000000 -0500 | ||
9 | @@ -768,7 +768,8 @@ | ||
10 | ? 64 \ | ||
11 | : (TREE_CODE (TYPE) == ARRAY_TYPE \ | ||
12 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | ||
13 | - && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))) | ||
14 | + && (ALIGN) < (TARGET_ALTIVEC ? 128 : BITS_PER_WORD)) \ | ||
15 | + ? (TARGET_ALTIVEC ? 128 : BITS_PER_WORD) : (ALIGN))) | ||
16 | |||
17 | /* Nonzero if move instructions will actually fail to work | ||
18 | when given unaligned data. */ | ||
diff --git a/recipes-devtools/gcc/files/gcc.opt-array-offset.patch b/recipes-devtools/gcc/files/gcc.opt-array-offset.patch new file mode 100644 index 0000000..7cdc6f7 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.opt-array-offset.patch | |||
@@ -0,0 +1,350 @@ | |||
1 | Implements a GIMPLE pass to optimize array access by factoring | ||
2 | out expressions that calculate address offset from | ||
3 | multiple array access. Controls with flag -fopt-array-offset | ||
4 | |||
5 | diff -ruN XLMe500mc/gcc/common.opt XLMe5500/gcc/common.opt | ||
6 | --- XLMe500mc/gcc/common.opt 2011-10-18 14:49:23.026644000 -0500 | ||
7 | +++ XLMe5500/gcc/common.opt 2011-10-05 12:39:26.242644101 -0500 | ||
8 | @@ -1992,6 +1992,10 @@ | ||
9 | Common Report Var(flag_tree_vrp) Init(0) Optimization | ||
10 | Perform Value Range Propagation on trees | ||
11 | |||
12 | +fopt-array-offset | ||
13 | +Common Report Var(flag_opt_array_offset) | ||
14 | +Expand array offset address calculations | ||
15 | + | ||
16 | funit-at-a-time | ||
17 | Common Report Var(flag_unit_at_a_time) Init(1) Optimization | ||
18 | Compile whole compilation unit at a time | ||
19 | diff -ruN XLMe500mc/gcc/Makefile.in XLMe5500/gcc/Makefile.in | ||
20 | --- XLMe500mc/gcc/Makefile.in 2011-10-18 14:49:23.028644000 -0500 | ||
21 | +++ XLMe5500/gcc/Makefile.in 2011-10-05 12:08:28.104643898 -0500 | ||
22 | @@ -1306,6 +1306,7 @@ | ||
23 | omp-low.o \ | ||
24 | optabs.o \ | ||
25 | options.o \ | ||
26 | + opt-array-offset.o \ | ||
27 | opts-common.o \ | ||
28 | opts-global.o \ | ||
29 | opts.o \ | ||
30 | @@ -2629,7 +2630,10 @@ | ||
31 | $(FLAGS_H) $(CGRAPH_H) $(PLUGIN_H) \ | ||
32 | $(TREE_INLINE_H) tree-mudflap.h $(GGC_H) graph.h $(CGRAPH_H) \ | ||
33 | $(TREE_PASS_H) $(CFGLOOP_H) $(EXCEPT_H) $(REGSET_H) | ||
34 | - | ||
35 | +opt-array-offset.o : opt-array-offset.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ | ||
36 | + $(TM_H) $(FLAGS_H) $(TREE_H) $(TREE_FLOW_H) $(TIMEVAR_H) \ | ||
37 | + $(TREE_PASS_H) alloc-pool.h $(BASIC_BLOCK_H) $(TARGET_H) \ | ||
38 | + $(DIAGNOSTIC_H) gimple-pretty-print.h tree-pretty-print.h | ||
39 | widen-types.o : widen-types.c $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(GIMPLE_H) \ | ||
40 | $(DIAGNOSTIC_H) $(GIMPLE_H) $(TREE_INLINE_H) langhooks.h \ | ||
41 | $(LANGHOOKS_DEF_H) $(TREE_FLOW_H) $(CGRAPH_H) $(TIMEVAR_H) $(TM_H) \ | ||
42 | diff -ruN XLMe500mc/gcc/opt-array-offset.c XLMe5500/gcc/opt-array-offset.c | ||
43 | --- XLMe500mc/gcc/opt-array-offset.c 1969-12-31 18:00:00.000000000 -0600 | ||
44 | +++ XLMe5500/gcc/opt-array-offset.c 2011-11-01 15:24:21.746039000 -0500 | ||
45 | @@ -0,0 +1,283 @@ | ||
46 | +/* Optimizing array element access | ||
47 | + Copyright (C) 2011 | ||
48 | + Free Software Foundation, Inc. | ||
49 | + | ||
50 | +This file is part of GCC. | ||
51 | + | ||
52 | +GCC is free software; you can redistribute it and/or modify it | ||
53 | +under the terms of the GNU General Public License as published by the | ||
54 | +Free Software Foundation; either version 3, or (at your option) any | ||
55 | +later version. | ||
56 | + | ||
57 | +GCC is distributed in the hope that it will be useful, but WITHOUT | ||
58 | +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
59 | +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
60 | +for more details. | ||
61 | + | ||
62 | +You should have received a copy of the GNU General Public License | ||
63 | +along with GCC; see the file COPYING3. If not see | ||
64 | +<http://www.gnu.org/licenses/>. */ | ||
65 | + | ||
66 | + | ||
67 | +/* This is a GIMPLE pass over basic block which coverts the stmts: | ||
68 | + | ||
69 | + a = b +/- c1; | ||
70 | + c = a * c2; | ||
71 | + | ||
72 | + to: | ||
73 | + | ||
74 | + a = b * c2; | ||
75 | + c = a +/- c1 * c2; | ||
76 | + | ||
77 | + in effect expanding the multiplication across addition/substraction. | ||
78 | + | ||
79 | + Motivating example: | ||
80 | + Consider the following simple integer array access: | ||
81 | + | ||
82 | + a[i] = c; | ||
83 | + a[i + 1] = c; | ||
84 | + | ||
85 | + The following GIMPLE equivalent will be generated: | ||
86 | + | ||
87 | + off_1 = i * 4; | ||
88 | + a_i = a + off_1; | ||
89 | + *a_i = c; | ||
90 | + | ||
91 | + off_1 = i + 1; | ||
92 | + off_2 = off_1 * 4; | ||
93 | + a_i1 = a + off_2; | ||
94 | + *a_i1 = c; | ||
95 | + | ||
96 | + Notice that a_i1 could simply be a_i + 4. But the calcuation of i+1 | ||
97 | + is preventing CSE to perform. This pass will essentially convert the | ||
98 | + second expr into: | ||
99 | + | ||
100 | + off_1 = i * 4; | ||
101 | + off_2 = off_1 + 4; | ||
102 | + a_i1 = a + off_2; | ||
103 | + .... | ||
104 | + | ||
105 | + Thus allowing the previous index i calculation to be reuse. off_1 + 4 | ||
106 | + would also be combined into a_i if offset addressing mode is available. | ||
107 | + This also have side effect of avoiding redundant sign extension on | ||
108 | + i+1 for LP64 model where native integer size is different from pointer size. | ||
109 | + | ||
110 | + The algorithm iterates through all the basic blocks looking for | ||
111 | + the above pattern. Care is taken to make sure off_1 only | ||
112 | + has the single use otherwise the transformation cannot be perform. | ||
113 | +*/ | ||
114 | + | ||
115 | + | ||
116 | +#include "config.h" | ||
117 | +#include "system.h" | ||
118 | +#include "coretypes.h" | ||
119 | +#include "tm.h" | ||
120 | +#include "flags.h" | ||
121 | +#include "tree.h" | ||
122 | +#include "tree-flow.h" | ||
123 | +#include "timevar.h" | ||
124 | +#include "tree-pass.h" | ||
125 | +#include "alloc-pool.h" | ||
126 | +#include "basic-block.h" | ||
127 | +#include "target.h" | ||
128 | +#include "gimple-pretty-print.h" | ||
129 | +#include "tree-pretty-print.h" | ||
130 | + | ||
131 | + | ||
132 | +/* | ||
133 | + We are looking for: | ||
134 | + a = b +/- c1 | ||
135 | + c = a * c2 (stmt incoming) | ||
136 | + d = &arr + c | ||
137 | +*/ | ||
138 | +static bool | ||
139 | +is_candidate (gimple stmt) | ||
140 | +{ | ||
141 | + tree mul_result = gimple_get_lhs (stmt); | ||
142 | + tree rhs1, rhs2; | ||
143 | + gimple rhs1_stmt, use_stmt; | ||
144 | + use_operand_p use_p; | ||
145 | + imm_use_iterator imm_iter; | ||
146 | + | ||
147 | + /* check for a * c2 */ | ||
148 | + if (gimple_assign_rhs_code (stmt) != MULT_EXPR) | ||
149 | + return false; | ||
150 | + | ||
151 | + rhs1 = gimple_assign_rhs1 (stmt); | ||
152 | + rhs2 = gimple_assign_rhs2 (stmt); | ||
153 | + | ||
154 | + if (TREE_CODE (rhs2) != INTEGER_CST) | ||
155 | + return false; | ||
156 | + | ||
157 | + /* check for b + c1 */ | ||
158 | + if (TREE_CODE (rhs1) == SSA_NAME) | ||
159 | + { | ||
160 | + rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); | ||
161 | + if (is_gimple_assign (rhs1_stmt)) | ||
162 | + { | ||
163 | + tree rhs1_2; | ||
164 | + tree plusminus_result; | ||
165 | + | ||
166 | + if (gimple_assign_rhs_code (rhs1_stmt) != PLUS_EXPR | ||
167 | + && gimple_assign_rhs_code (rhs1_stmt) != MINUS_EXPR) | ||
168 | + return false; | ||
169 | + | ||
170 | + rhs1_2 = gimple_assign_rhs2 (rhs1_stmt); | ||
171 | + if (TREE_CODE (rhs1_2) != INTEGER_CST) | ||
172 | + return false; | ||
173 | + | ||
174 | + /* make sure there are no other uses of a | ||
175 | + e.g. if a is used as an indcution variable | ||
176 | + we cannot modified it | ||
177 | + */ | ||
178 | + plusminus_result = gimple_get_lhs (rhs1_stmt); | ||
179 | + FOR_EACH_IMM_USE_FAST (use_p, imm_iter, plusminus_result) | ||
180 | + { | ||
181 | + use_stmt = USE_STMT (use_p); | ||
182 | + | ||
183 | + /* ignore PHI node */ | ||
184 | + if (is_gimple_assign (use_stmt) && | ||
185 | + (gimple_assign_rhs_code (use_stmt) == GIMPLE_PHI)) | ||
186 | + continue; | ||
187 | + if (use_stmt != stmt) | ||
188 | + return false; | ||
189 | + } | ||
190 | + | ||
191 | +#if 0 | ||
192 | + if (gimple_bb(rhs1_stmt) != gimple_bb(stmt)) | ||
193 | + return false; | ||
194 | +#endif | ||
195 | + } | ||
196 | + else | ||
197 | + return false; | ||
198 | + } | ||
199 | + else | ||
200 | + return false; | ||
201 | + | ||
202 | + /* now look for uses of c that is a pointer use */ | ||
203 | + FOR_EACH_IMM_USE_FAST (use_p, imm_iter, mul_result) | ||
204 | + { | ||
205 | + enum tree_code use_code; | ||
206 | + | ||
207 | + use_stmt = USE_STMT (use_p); | ||
208 | + | ||
209 | + if (is_gimple_debug (use_stmt)) | ||
210 | + continue; | ||
211 | + | ||
212 | + if (gimple_bb (use_stmt) != gimple_bb (stmt)) | ||
213 | + return false; | ||
214 | + | ||
215 | + if (!is_gimple_assign (use_stmt)) | ||
216 | + return false; | ||
217 | + | ||
218 | + use_code = gimple_assign_rhs_code (use_stmt); | ||
219 | + if (use_code != POINTER_PLUS_EXPR) | ||
220 | + return false; | ||
221 | + } | ||
222 | + | ||
223 | + if (dump_file) | ||
224 | + { | ||
225 | + fprintf (dump_file, "Found candidate:\n"); | ||
226 | + print_gimple_stmt (dump_file, rhs1_stmt, 0, TDF_SLIM); | ||
227 | + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); | ||
228 | + print_gimple_stmt (dump_file, use_stmt, 0, TDF_SLIM); | ||
229 | + } | ||
230 | + | ||
231 | + return true; | ||
232 | +} | ||
233 | + | ||
234 | +/* Do the actual transformation: | ||
235 | + a = b + c1 ==> a = b * c2 | ||
236 | + c = a * c2 ==> c = a + c1*c2 | ||
237 | +*/ | ||
238 | +static bool | ||
239 | +expand_plusminus_mult (gimple stmt) | ||
240 | +{ | ||
241 | + tree c1, c2, mul_result; | ||
242 | + gimple rhs1_stmt; | ||
243 | + | ||
244 | + /* get c2 */ | ||
245 | + c2 = gimple_assign_rhs2 (stmt); | ||
246 | + | ||
247 | + /* get c1 */ | ||
248 | + rhs1_stmt = SSA_NAME_DEF_STMT (gimple_assign_rhs1 (stmt)); | ||
249 | + c1 = gimple_assign_rhs2 (rhs1_stmt); | ||
250 | + | ||
251 | + /* form c1 * c2 */ | ||
252 | + mul_result = double_int_to_tree (TREE_TYPE(c2), double_int_mul | ||
253 | + (tree_to_double_int (c1), tree_to_double_int (c2))); | ||
254 | + | ||
255 | + /* a = b + c1 ==> a = b * c2 */ | ||
256 | + gimple_assign_set_rhs2 (rhs1_stmt, c2); | ||
257 | + gimple_assign_set_rhs_code (rhs1_stmt, MULT_EXPR); | ||
258 | + update_stmt (rhs1_stmt); | ||
259 | + | ||
260 | + /* c = a * c2 ==> c = a + c1*c2 */ | ||
261 | + gimple_assign_set_rhs2 (stmt, mul_result); | ||
262 | + /* MINUS_EXPR has already been embedded into c1*c2 */ | ||
263 | + gimple_assign_set_rhs_code (stmt, PLUS_EXPR); | ||
264 | + update_stmt (stmt); | ||
265 | + | ||
266 | + return true; | ||
267 | +} | ||
268 | + | ||
269 | + | ||
270 | +static unsigned int | ||
271 | +execute_opt_array_offset (void) | ||
272 | +{ | ||
273 | + basic_block bb; | ||
274 | + tree fndecl; | ||
275 | + | ||
276 | + FOR_EACH_BB (bb) | ||
277 | + { | ||
278 | + gimple_stmt_iterator gsi; | ||
279 | + | ||
280 | + for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next(&gsi)) | ||
281 | + { | ||
282 | + gimple stmt = gsi_stmt (gsi); | ||
283 | + tree lhs,rhs1,rhs2,rhs3; | ||
284 | + enum tree_code code; | ||
285 | + | ||
286 | + /* only interested in assign statement */ | ||
287 | + if (is_gimple_assign (stmt)) | ||
288 | + { | ||
289 | + /* find stmts calculating array offset */ | ||
290 | + if (is_candidate (stmt)) | ||
291 | + /* convert stmt */ | ||
292 | + expand_plusminus_mult(stmt); | ||
293 | + | ||
294 | + } | ||
295 | + } | ||
296 | + } | ||
297 | + | ||
298 | + return 0; | ||
299 | +} | ||
300 | + | ||
301 | +static bool | ||
302 | +gate_opt_array_offset (void) | ||
303 | +{ | ||
304 | + return flag_opt_array_offset && optimize; | ||
305 | +} | ||
306 | + | ||
307 | +struct gimple_opt_pass pass_opt_array_offset = | ||
308 | +{ | ||
309 | + { | ||
310 | + GIMPLE_PASS, | ||
311 | + "opt_array_offset", /* name */ | ||
312 | + gate_opt_array_offset, /* gate */ | ||
313 | + execute_opt_array_offset, /* execute */ | ||
314 | + NULL, /* sub */ | ||
315 | + NULL, /* next */ | ||
316 | + 0, /* static_pass_number */ | ||
317 | + TV_NONE, /* tv_id */ | ||
318 | + PROP_ssa, /* properties_required */ | ||
319 | + 0, /* properties_provided */ | ||
320 | + 0, /* properties_destroyed */ | ||
321 | + 0, /* todo_flags_start */ | ||
322 | + TODO_verify_ssa | ||
323 | + | TODO_verify_stmts | ||
324 | + | TODO_update_ssa | ||
325 | + | TODO_dump_func /* todo_flags_finish */ | ||
326 | + } | ||
327 | +}; | ||
328 | + | ||
329 | diff -ruN XLMe500mc/gcc/passes.c XLMe5500/gcc/passes.c | ||
330 | --- XLMe500mc/gcc/passes.c 2011-10-18 14:49:23.029644000 -0500 | ||
331 | +++ XLMe5500/gcc/passes.c 2011-10-05 11:19:01.168644127 -0500 | ||
332 | @@ -937,6 +937,7 @@ | ||
333 | NEXT_PASS (pass_phiopt); | ||
334 | NEXT_PASS (pass_fold_builtins); | ||
335 | NEXT_PASS (pass_optimize_widening_mul); | ||
336 | + NEXT_PASS (pass_opt_array_offset); | ||
337 | NEXT_PASS (pass_tail_calls); | ||
338 | NEXT_PASS (pass_rename_ssa_copies); | ||
339 | NEXT_PASS (pass_uncprop); | ||
340 | diff -ruN XLMe500mc/gcc/tree-pass.h XLMe5500/gcc/tree-pass.h | ||
341 | --- XLMe500mc/gcc/tree-pass.h 2011-10-18 14:49:23.029644000 -0500 | ||
342 | +++ XLMe5500/gcc/tree-pass.h 2011-10-05 11:19:59.665643705 -0500 | ||
343 | @@ -421,6 +421,7 @@ | ||
344 | extern struct gimple_opt_pass pass_cse_sincos; | ||
345 | extern struct gimple_opt_pass pass_optimize_bswap; | ||
346 | extern struct gimple_opt_pass pass_optimize_widening_mul; | ||
347 | +extern struct gimple_opt_pass pass_opt_array_offset; | ||
348 | extern struct gimple_opt_pass pass_warn_function_return; | ||
349 | extern struct gimple_opt_pass pass_warn_function_noreturn; | ||
350 | extern struct gimple_opt_pass pass_cselim; | ||
diff --git a/recipes-devtools/gcc/files/gcc.remove_CCUNSmode_reference.patch b/recipes-devtools/gcc/files/gcc.remove_CCUNSmode_reference.patch new file mode 100644 index 0000000..03e3ce9 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.remove_CCUNSmode_reference.patch | |||
@@ -0,0 +1,24 @@ | |||
1 | --- gcc-4_6-branch/gcc/extelim.c.orig 2012-03-05 21:42:53.984215949 -0600 | ||
2 | +++ gcc-4_6-branch/gcc/extelim.c 2012-03-05 21:43:27.884394659 -0600 | ||
3 | @@ -922,8 +922,7 @@ | ||
4 | && GET_MODE (exp) != HImode | ||
5 | && GET_MODE (exp) != SImode | ||
6 | && GET_MODE (exp) != DImode | ||
7 | - && GET_MODE (exp) != CCmode | ||
8 | - && GET_MODE (exp) != CCUNSmode) | ||
9 | + && GET_MODE (exp) != CCmode) | ||
10 | return false; | ||
11 | |||
12 | return true; | ||
13 | @@ -1653,9 +1652,9 @@ | ||
14 | For our targets, there is no 'cmph' insn, so we bail out | ||
15 | if we see a comparison of sizes less than a word (SI). */ | ||
16 | if (REG_P (dest) | ||
17 | - && (GET_MODE (dest) == CCmode || GET_MODE (dest) == CCUNSmode) | ||
18 | + && (GET_MODE (dest) == CCmode) | ||
19 | && GET_CODE (src) == COMPARE | ||
20 | - && (GET_MODE (src) == CCmode || GET_MODE (src) == CCUNSmode)) | ||
21 | + && (GET_MODE (src) == CCmode)) | ||
22 | { | ||
23 | rtx compare_op0 = XEXP (src, 0); | ||
24 | rtx compare_op1 = XEXP (src, 1); | ||
diff --git a/recipes-devtools/gcc/files/gcc.rm_slow_tests.patch b/recipes-devtools/gcc/files/gcc.rm_slow_tests.patch new file mode 100644 index 0000000..b02b755 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.rm_slow_tests.patch | |||
@@ -0,0 +1,67 @@ | |||
1 | diff -urN gcc-4.6.0/gcc/testsuite/gfortran.dg/cray_pointers_8.f90 gcc-4.6.0-fixed/gcc/testsuite/gfortran.dg/cray_pointers_8.f90 | ||
2 | --- gcc-4.6.0/gcc/testsuite/gfortran.dg/cray_pointers_8.f90 2009-02-13 15:12:34.000000000 -0600 | ||
3 | +++ gcc-4.6.0-fixed/gcc/testsuite/gfortran.dg/cray_pointers_8.f90 1969-12-31 18:00:00.000000000 -0600 | ||
4 | @@ -1,63 +0,0 @@ | ||
5 | -! { dg-do run } | ||
6 | -! { dg-options "-fcray-pointer" } | ||
7 | -! | ||
8 | -! Test the fix for PR36528 in which the Cray pointer was not passed | ||
9 | -! correctly to 'euler' so that an undefined reference to fcn was | ||
10 | -! generated by the linker. | ||
11 | -! | ||
12 | -! Reported by Tobias Burnus <burnus@gcc.gnu.org> | ||
13 | -! from http://groups.google.com/group/comp.lang.fortran/msg/86b65bad78e6af78 | ||
14 | -! | ||
15 | -real function p1(x) | ||
16 | - real, intent(in) :: x | ||
17 | - p1 = x | ||
18 | -end | ||
19 | - | ||
20 | -real function euler(xp,xk,dx,f) | ||
21 | - real, intent(in) :: xp, xk, dx | ||
22 | - interface | ||
23 | - real function f(x) | ||
24 | - real, intent(in) :: x | ||
25 | - end function | ||
26 | - end interface | ||
27 | - real x, y | ||
28 | - y = 0.0 | ||
29 | - x = xp | ||
30 | - do while (x .le. xk) | ||
31 | - y = y + f(x)*dx | ||
32 | - x = x + dx | ||
33 | - end do | ||
34 | - euler = y | ||
35 | -end | ||
36 | -program main | ||
37 | - interface | ||
38 | - real function p1 (x) | ||
39 | - real, intent(in) :: x | ||
40 | - end function | ||
41 | - real function fcn (x) | ||
42 | - real, intent(in) :: x | ||
43 | - end function | ||
44 | - real function euler (xp,xk,dx,f) | ||
45 | - real, intent(in) :: xp, xk ,dx | ||
46 | - interface | ||
47 | - real function f(x) | ||
48 | - real, intent(in) :: x | ||
49 | - end function | ||
50 | - end interface | ||
51 | - end function | ||
52 | - end interface | ||
53 | - real x, xp, xk, dx, y, z | ||
54 | - pointer (pfcn, fcn) | ||
55 | - pfcn = loc(p1) | ||
56 | - xp = 0.0 | ||
57 | - xk = 1.0 | ||
58 | - dx = 0.0005 | ||
59 | - y = 0.0 | ||
60 | - x = xp | ||
61 | - do while (x .le. xk) | ||
62 | - y = y + fcn(x)*dx | ||
63 | - x = x + dx | ||
64 | - end do | ||
65 | - z = euler(0.0,1.0,0.0005,fcn) | ||
66 | - if (abs (y - z) .gt. 1e-6) call abort | ||
67 | -end | ||
diff --git a/recipes-devtools/gcc/files/gcc.soft_float-460.patch b/recipes-devtools/gcc/files/gcc.soft_float-460.patch new file mode 100644 index 0000000..eafa6ab --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.soft_float-460.patch | |||
@@ -0,0 +1,190 @@ | |||
1 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_data_map_rand.cc | ||
2 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
3 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_data_map_rand.cc 2011-05-11 20:03:39.000000000 -0500 | ||
4 | @@ -46,17 +46,17 @@ | ||
5 | |||
6 | #ifndef ITERATIONS | ||
7 | # ifdef _GLIBCXX_DEBUG | ||
8 | -# define ITERATIONS 100 | ||
9 | +# define ITERATIONS 2 | ||
10 | # else | ||
11 | -# define ITERATIONS 5000 | ||
12 | +# define ITERATIONS 2 | ||
13 | #endif | ||
14 | #endif | ||
15 | |||
16 | #ifndef KEYS | ||
17 | # ifdef _GLIBCXX_DEBUG | ||
18 | -# define KEYS 200 | ||
19 | +# define KEYS 5 | ||
20 | # else | ||
21 | -# define KEYS 10000 | ||
22 | +# define KEYS 5 | ||
23 | # endif | ||
24 | #endif | ||
25 | |||
26 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_no_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_no_data_map_rand.cc | ||
27 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_no_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
28 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/hash_no_data_map_rand.cc 2011-05-11 20:04:00.000000000 -0500 | ||
29 | @@ -46,17 +46,17 @@ | ||
30 | |||
31 | #ifndef ITERATIONS | ||
32 | # ifdef _GLIBCXX_DEBUG | ||
33 | -# define ITERATIONS 100 | ||
34 | +# define ITERATIONS 2 | ||
35 | # else | ||
36 | -# define ITERATIONS 5000 | ||
37 | +# define ITERATIONS 2 | ||
38 | #endif | ||
39 | #endif | ||
40 | |||
41 | #ifndef KEYS | ||
42 | # ifdef _GLIBCXX_DEBUG | ||
43 | -# define KEYS 200 | ||
44 | +# define KEYS 5 | ||
45 | # else | ||
46 | -# define KEYS 10000 | ||
47 | +# define KEYS 5 | ||
48 | # endif | ||
49 | #endif | ||
50 | |||
51 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_data_map_rand.cc | ||
52 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
53 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_data_map_rand.cc 2011-05-11 20:02:23.000000000 -0500 | ||
54 | @@ -47,7 +47,7 @@ | ||
55 | using namespace __gnu_pbds::test; | ||
56 | typedef lu_map_tl_t map_tl_t; | ||
57 | |||
58 | - return rand_regression_test(50, 10, | ||
59 | + return rand_regression_test(2, 5, | ||
60 | "lu_data_map_rand_regression_test", | ||
61 | map_tl_t()); | ||
62 | } | ||
63 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_no_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_no_data_map_rand.cc | ||
64 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_no_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
65 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/list_update_no_data_map_rand.cc 2011-05-11 20:02:23.000000000 -0500 | ||
66 | @@ -47,7 +47,7 @@ | ||
67 | using namespace __gnu_pbds::test; | ||
68 | typedef lu_set_tl_t map_tl_t; | ||
69 | |||
70 | - return rand_regression_test(50, 10, | ||
71 | + return rand_regression_test(2, 5, | ||
72 | "lu_no_data_map_rand_regression_test", | ||
73 | map_tl_t()); | ||
74 | } | ||
75 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/priority_queue_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/priority_queue_rand.cc | ||
76 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/priority_queue_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
77 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/priority_queue_rand.cc 2011-05-11 20:02:23.000000000 -0500 | ||
78 | @@ -45,10 +45,10 @@ | ||
79 | #include <regression/common_type.hpp> | ||
80 | |||
81 | #ifndef ITERATIONS | ||
82 | -#define ITERATIONS 5000 | ||
83 | +#define ITERATIONS 2 | ||
84 | #endif | ||
85 | #ifndef KEYS | ||
86 | -#define KEYS 10000 | ||
87 | +#define KEYS 5 | ||
88 | #endif | ||
89 | int | ||
90 | main(int argc, char* a_p_argv[]) | ||
91 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_data_map_rand.cc | ||
92 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
93 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_data_map_rand.cc 2011-05-11 20:04:21.000000000 -0500 | ||
94 | @@ -46,17 +46,17 @@ | ||
95 | |||
96 | #ifndef ITERATIONS | ||
97 | # ifdef _GLIBCXX_DEBUG | ||
98 | -# define ITERATIONS 100 | ||
99 | +# define ITERATIONS 2 | ||
100 | # else | ||
101 | -# define ITERATIONS 5000 | ||
102 | +# define ITERATIONS 2 | ||
103 | #endif | ||
104 | #endif | ||
105 | |||
106 | #ifndef KEYS | ||
107 | # ifdef _GLIBCXX_DEBUG | ||
108 | -# define KEYS 200 | ||
109 | +# define KEYS 5 | ||
110 | # else | ||
111 | -# define KEYS 10000 | ||
112 | +# define KEYS 5 | ||
113 | # endif | ||
114 | #endif | ||
115 | |||
116 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_no_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_no_data_map_rand.cc | ||
117 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_no_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
118 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/tree_no_data_map_rand.cc 2011-05-11 20:04:41.000000000 -0500 | ||
119 | @@ -47,17 +47,17 @@ | ||
120 | |||
121 | #ifndef ITERATIONS | ||
122 | # ifdef _GLIBCXX_DEBUG | ||
123 | -# define ITERATIONS 100 | ||
124 | +# define ITERATIONS 2 | ||
125 | # else | ||
126 | -# define ITERATIONS 5000 | ||
127 | +# define ITERATIONS 2 | ||
128 | #endif | ||
129 | #endif | ||
130 | |||
131 | #ifndef KEYS | ||
132 | # ifdef _GLIBCXX_DEBUG | ||
133 | -# define KEYS 200 | ||
134 | +# define KEYS 5 | ||
135 | # else | ||
136 | -# define KEYS 10000 | ||
137 | +# define KEYS 5 | ||
138 | # endif | ||
139 | #endif | ||
140 | |||
141 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_data_map_rand.cc | ||
142 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
143 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_data_map_rand.cc 2011-05-11 20:05:34.000000000 -0500 | ||
144 | @@ -46,17 +46,17 @@ | ||
145 | |||
146 | #ifndef ITERATIONS | ||
147 | # ifdef _GLIBCXX_DEBUG | ||
148 | -# define ITERATIONS 100 | ||
149 | +# define ITERATIONS 2 | ||
150 | # else | ||
151 | -# define ITERATIONS 5000 | ||
152 | +# define ITERATIONS 2 | ||
153 | #endif | ||
154 | #endif | ||
155 | |||
156 | #ifndef KEYS | ||
157 | # ifdef _GLIBCXX_DEBUG | ||
158 | -# define KEYS 200 | ||
159 | +# define KEYS 5 | ||
160 | # else | ||
161 | -# define KEYS 10000 | ||
162 | +# define KEYS 5 | ||
163 | # endif | ||
164 | #endif | ||
165 | |||
166 | diff -u gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_no_data_map_rand.cc gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_no_data_map_rand.cc | ||
167 | --- gcc-4.6.0-orig/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_no_data_map_rand.cc 2011-05-11 20:01:58.000000000 -0500 | ||
168 | +++ gcc-4.6.0/libstdc++-v3/testsuite/ext/pb_ds/regression/trie_no_data_map_rand.cc 2011-05-11 20:05:50.000000000 -0500 | ||
169 | @@ -46,17 +46,17 @@ | ||
170 | |||
171 | #ifndef ITERATIONS | ||
172 | # ifdef _GLIBCXX_DEBUG | ||
173 | -# define ITERATIONS 100 | ||
174 | +# define ITERATIONS 2 | ||
175 | # else | ||
176 | -# define ITERATIONS 5000 | ||
177 | +# define ITERATIONS 2 | ||
178 | #endif | ||
179 | #endif | ||
180 | |||
181 | #ifndef KEYS | ||
182 | # ifdef _GLIBCXX_DEBUG | ||
183 | -# define KEYS 200 | ||
184 | +# define KEYS 5 | ||
185 | # else | ||
186 | -# define KEYS 10000 | ||
187 | +# define KEYS 5 | ||
188 | # endif | ||
189 | #endif | ||
190 | |||
diff --git a/recipes-devtools/gcc/files/gcc.widen_types-46.patch b/recipes-devtools/gcc/files/gcc.widen_types-46.patch new file mode 100644 index 0000000..0590560 --- /dev/null +++ b/recipes-devtools/gcc/files/gcc.widen_types-46.patch | |||
@@ -0,0 +1,1534 @@ | |||
1 | diff -ruN gcc-4.6.0-orig/gcc/common.opt gcc-4.6.0-new/gcc/common.opt | ||
2 | --- gcc-4.6.0-orig/gcc/common.opt 2011-03-05 18:38:13.000000000 -0600 | ||
3 | +++ gcc-4.6.0-new/gcc/common.opt 2011-08-25 13:16:36.408937475 -0500 | ||
4 | @@ -1797,6 +1797,10 @@ | ||
5 | Common Report Var(flag_strict_overflow) | ||
6 | Treat signed overflow as undefined | ||
7 | |||
8 | +fwiden-types | ||
9 | +Common Report Var(flag_widen_types) | ||
10 | +Widen signed integral variables (local, whose address has not been taken, non-volatile and having precision less than that of long) to long (retaining original qualifiers) | ||
11 | + | ||
12 | fsyntax-only | ||
13 | Common Report Var(flag_syntax_only) | ||
14 | Check for syntax errors, then stop | ||
15 | diff -ruN gcc-4.6.0-orig/gcc/Makefile.in gcc-4.6.0-new/gcc/Makefile.in | ||
16 | --- gcc-4.6.0-orig/gcc/Makefile.in 2011-01-25 22:19:58.000000000 -0600 | ||
17 | +++ gcc-4.6.0-new/gcc/Makefile.in 2011-08-25 13:16:36.411937390 -0500 | ||
18 | @@ -1245,6 +1245,7 @@ | ||
19 | gimple-fold.o \ | ||
20 | gimple-low.o \ | ||
21 | gimple-pretty-print.o \ | ||
22 | + widen-types.o \ | ||
23 | gimplify.o \ | ||
24 | godump.o \ | ||
25 | graph.o \ | ||
26 | @@ -2628,6 +2629,12 @@ | ||
27 | $(TREE_INLINE_H) tree-mudflap.h $(GGC_H) graph.h $(CGRAPH_H) \ | ||
28 | $(TREE_PASS_H) $(CFGLOOP_H) $(EXCEPT_H) $(REGSET_H) | ||
29 | |||
30 | +widen-types.o : widen-types.c $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(GIMPLE_H) \ | ||
31 | + $(DIAGNOSTIC_H) $(GIMPLE_H) $(TREE_INLINE_H) langhooks.h \ | ||
32 | + $(LANGHOOKS_DEF_H) $(TREE_FLOW_H) $(CGRAPH_H) $(TIMEVAR_H) $(TM_H) \ | ||
33 | + coretypes.h $(EXCEPT_H) $(FLAGS_H) $(RTL_H) $(FUNCTION_H) $(EXPR_H) output.h \ | ||
34 | + $(GGC_H) gt-gimplify.h $(HASHTAB_H) $(TARGET_H) $(DIAGNOSTIC_CORE_H) $(OPTABS_H) \ | ||
35 | + $(SPLAY_TREE_H) $(VEC_H) tree-iterator.h tree-pass.h tree-pretty-print.h | ||
36 | gimplify.o : gimplify.c $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(GIMPLE_H) \ | ||
37 | $(DIAGNOSTIC_H) $(GIMPLE_H) $(TREE_INLINE_H) langhooks.h \ | ||
38 | $(LANGHOOKS_DEF_H) $(TREE_FLOW_H) $(CGRAPH_H) $(TIMEVAR_H) $(TM_H) \ | ||
39 | @@ -3733,6 +3740,7 @@ | ||
40 | $(srcdir)/tree-cfg.c \ | ||
41 | $(srcdir)/tree-dfa.c \ | ||
42 | $(srcdir)/tree-iterator.c $(srcdir)/gimplify.c \ | ||
43 | + $(srcdir)/widen-types.c \ | ||
44 | $(srcdir)/tree-chrec.h \ | ||
45 | $(srcdir)/tree-scalar-evolution.c \ | ||
46 | $(srcdir)/tree-ssa-operands.h \ | ||
47 | diff -ruN gcc-4.6.0-orig/gcc/passes.c gcc-4.6.0-new/gcc/passes.c | ||
48 | --- gcc-4.6.0-orig/gcc/passes.c 2011-02-17 10:18:24.000000000 -0600 | ||
49 | +++ gcc-4.6.0-new/gcc/passes.c 2011-08-25 13:16:36.413937342 -0500 | ||
50 | @@ -719,6 +719,7 @@ | ||
51 | backend might produce already lowered functions that are not processed | ||
52 | by these passes. */ | ||
53 | p = &all_lowering_passes; | ||
54 | + NEXT_PASS (pass_widen_types_stmts); | ||
55 | NEXT_PASS (pass_warn_unused_result); | ||
56 | NEXT_PASS (pass_diagnose_omp_blocks); | ||
57 | NEXT_PASS (pass_mudflap_1); | ||
58 | @@ -741,6 +742,7 @@ | ||
59 | NEXT_PASS (pass_fixup_cfg); | ||
60 | NEXT_PASS (pass_init_datastructures); | ||
61 | NEXT_PASS (pass_expand_omp); | ||
62 | + NEXT_PASS (pass_widen_types_bbs); | ||
63 | |||
64 | NEXT_PASS (pass_referenced_vars); | ||
65 | NEXT_PASS (pass_build_ssa); | ||
66 | diff -ruN gcc-4.6.0-orig/gcc/tree-pass.h gcc-4.6.0-new/gcc/tree-pass.h | ||
67 | --- gcc-4.6.0-orig/gcc/tree-pass.h 2011-02-01 09:12:26.000000000 -0600 | ||
68 | +++ gcc-4.6.0-new/gcc/tree-pass.h 2011-08-25 13:16:36.406937543 -0500 | ||
69 | @@ -349,6 +349,7 @@ | ||
70 | |||
71 | extern void tree_lowering_passes (tree decl); | ||
72 | |||
73 | +extern struct gimple_opt_pass pass_widen_types_stmts; | ||
74 | extern struct gimple_opt_pass pass_mudflap_1; | ||
75 | extern struct gimple_opt_pass pass_mudflap_2; | ||
76 | extern struct gimple_opt_pass pass_lower_cf; | ||
77 | @@ -409,6 +410,7 @@ | ||
78 | extern struct gimple_opt_pass pass_lower_omp; | ||
79 | extern struct gimple_opt_pass pass_diagnose_omp_blocks; | ||
80 | extern struct gimple_opt_pass pass_expand_omp; | ||
81 | +extern struct gimple_opt_pass pass_widen_types_bbs; | ||
82 | extern struct gimple_opt_pass pass_expand_omp_ssa; | ||
83 | extern struct gimple_opt_pass pass_object_sizes; | ||
84 | extern struct gimple_opt_pass pass_fold_builtins; | ||
85 | diff -ruN gcc-4.6.0-orig/gcc/widen-types.c gcc-4.6.0-new/gcc/widen-types.c | ||
86 | --- gcc-4.6.0-orig/gcc/widen-types.c 1969-12-31 18:00:00.000000000 -0600 | ||
87 | +++ gcc-4.6.0-new/gcc/widen-types.c 2011-08-25 17:27:31.372937392 -0500 | ||
88 | @@ -0,0 +1,1446 @@ | ||
89 | +/* | ||
90 | + Type Widening: | ||
91 | + | ||
92 | + Locals and temporaries having signed integral types, whose address has | ||
93 | + not been taken, are not volatile qualified, and having type precision | ||
94 | + less than that of type long are widened to type long (with any other | ||
95 | + qualifiers retained). | ||
96 | + | ||
97 | + Copyright (C) 2011 | ||
98 | + Free Software Foundation, Inc. | ||
99 | + | ||
100 | +This file is part of GCC. | ||
101 | + | ||
102 | +GCC is free software; you can redistribute it and/or modify it under | ||
103 | +the terms of the GNU General Public License as published by the Free | ||
104 | +Software Foundation; either version 3, or (at your option) any later | ||
105 | +version. | ||
106 | + | ||
107 | +GCC is distributed in the hope that it will be useful, but WITHOUT ANY | ||
108 | +WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
109 | +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
110 | +for more details. | ||
111 | + | ||
112 | +You should have received a copy of the GNU General Public License | ||
113 | +along with GCC; see the file COPYING3. If not see | ||
114 | +<http://www.gnu.org/licenses/>. */ | ||
115 | + | ||
116 | +#include "config.h" | ||
117 | +#include "system.h" | ||
118 | +#include "coretypes.h" | ||
119 | +#include "tm.h" | ||
120 | +#include "tree.h" | ||
121 | +#include "tm_p.h" | ||
122 | +#include "gimple.h" | ||
123 | +#include "basic-block.h" | ||
124 | +#include "tree-iterator.h" | ||
125 | +#include "tree-inline.h" | ||
126 | +#include "langhooks.h" | ||
127 | +#include "tree-pretty-print.h" | ||
128 | +#include "gimple-pretty-print.h" | ||
129 | +#include "langhooks.h" | ||
130 | +#include "tree-flow.h" | ||
131 | +#include "cgraph.h" | ||
132 | +#include "timevar.h" | ||
133 | +#include "hashtab.h" | ||
134 | +#include "flags.h" | ||
135 | +#include "function.h" | ||
136 | +#include "output.h" | ||
137 | +#include "ggc.h" | ||
138 | +#include "tree-dump.h" | ||
139 | +#include "tree-pass.h" | ||
140 | +#include "diagnostic-core.h" | ||
141 | +#include "target.h" | ||
142 | +#include "pointer-set.h" | ||
143 | +#include "splay-tree.h" | ||
144 | +#include "vec.h" | ||
145 | +#include "gimple.h" | ||
146 | +#include "tree-pass.h" | ||
147 | + | ||
148 | +#include "langhooks-def.h" | ||
149 | +#include "expr.h" | ||
150 | + | ||
151 | +#include "except.h" | ||
152 | +#include "value-prof.h" | ||
153 | +#include "pointer-set.h" | ||
154 | + | ||
155 | +/* define TW_FINALIZE_STMTS to 1, if you want to run the widening | ||
156 | + * pass just after gimplification - over the sequence of statements. | ||
157 | + */ | ||
158 | +#define TW_FINALIZE_STMTS 1 | ||
159 | + | ||
160 | +#define TW_DEBUG 0 | ||
161 | +#if TW_DEBUG | ||
162 | + | ||
163 | +#define TWDBG_STMT(stmt) fprintf (stderr, "%s: ", __FUNCTION__); \ | ||
164 | + debug_gimple_stmt (stmt); | ||
165 | + | ||
166 | +#define TWDBG_TREE(tree) \ | ||
167 | +{ \ | ||
168 | + fprintf (stderr, "%s:\n", #tree); \ | ||
169 | + debug_tree (tree); \ | ||
170 | + fprintf (stderr, "\n"); \ | ||
171 | +} | ||
172 | + | ||
173 | +#define TWDBG_MSG(fmt) \ | ||
174 | +fprintf (stderr, "%s: ", __FUNCTION__); \ | ||
175 | +fprintf (stderr, fmt) | ||
176 | + | ||
177 | +#define TWDBG_MSG1(fmt, msg) \ | ||
178 | +fprintf (stderr, "%s: ", __FUNCTION__); \ | ||
179 | +fprintf (stderr, fmt, msg) | ||
180 | + | ||
181 | +#else | ||
182 | +#define TWDBG_STMT(stmt) | ||
183 | +#define TWDBG_TREE(tree) | ||
184 | +#define TWDBG_MSG(fmt) | ||
185 | +#define TWDBG_MSG1(fmt, msg) | ||
186 | +#endif | ||
187 | + | ||
188 | +#if TW_DEBUG | ||
189 | +static void tw_dump_candidate_list (void); | ||
190 | +static bool tw_debug_candidate (const void *t, void **candidacy, void *data); | ||
191 | +#endif | ||
192 | +static void tw_init (void); | ||
193 | +static void tw_reset (void); | ||
194 | +static long tw_candidate (tree node); | ||
195 | +static long tw_candidate_const (tree node); | ||
196 | +static long *tw_log_candidate (tree node); | ||
197 | +static long tw_candidacy_valid (tree node); | ||
198 | +static void tw_candidacy (tree node, long value); | ||
199 | +static long tw_in_candidate_list (tree node); | ||
200 | +static tree tw_widen_constant (tree node); | ||
201 | +static tree tw_widen_variable (tree node); | ||
202 | +#ifdef TW_FINALIZE_STMTS | ||
203 | +static long tw_fn_has_openmp (gimple_seq stmts); | ||
204 | +#endif | ||
205 | +static void tw_log_parms (tree fndecl); | ||
206 | +#ifdef TW_FINALIZE_STMTS | ||
207 | +static void tw_log_vars (gimple_seq stmts); | ||
208 | +#endif | ||
209 | +static void tw_log_local_decls (void); | ||
210 | +#ifdef TW_FINALIZE_STMTS | ||
211 | +static unsigned int tw_finalize_stmts (void); | ||
212 | +#endif | ||
213 | +static unsigned int tw_finalize_bbs (void); | ||
214 | +static long tw_gimple_in_seq (gimple_seq stmts, long widen); | ||
215 | +static long tw_gimple_in_bb (basic_block bb, long widen); | ||
216 | +static long tw_switch (gimple stmt, long widen); | ||
217 | +static long tw_gimple_stmt (gimple stmt, long widen); | ||
218 | +static long tw_gimple_assign (gimple stmt, long widen); | ||
219 | +static long tw_gimple_assign_single (gimple stmt, long widen); | ||
220 | +static long tw_gimple_assign_unary (gimple stmt, long widen); | ||
221 | +static long tw_gimple_assign_binary (gimple stmt, long widen); | ||
222 | +static long tw_gimple_assign_ternary (gimple stmt, long widen); | ||
223 | +static bool is_formatted_IO_fn (tree decl); | ||
224 | +static long tw_gimple_call (gimple stmt, long widen); | ||
225 | +static long tw_gimple_comparison (gimple stmt, long widen); | ||
226 | +static long tw_gimple_switch (gimple stmt, long widen); | ||
227 | +static long tw_gimple_return (gimple stmt, long widen); | ||
228 | +static long tw_gimple_asm (gimple stmt, long widen); | ||
229 | +static long tw_gimple_debug (gimple stmt, long widen); | ||
230 | + | ||
231 | +static struct pointer_map_t *tw_candidate_list; | ||
232 | + | ||
233 | +#if TW_DEBUG | ||
234 | +static void | ||
235 | +tw_dump_candidate_list (void) | ||
236 | +{ | ||
237 | + TWDBG_MSG ("Dumping candidate list:\n"); | ||
238 | + pointer_map_traverse (tw_candidate_list, tw_debug_candidate, NULL); | ||
239 | + TWDBG_MSG ("Done dumping candidate list\n"); | ||
240 | +} | ||
241 | + | ||
242 | +static | ||
243 | +bool tw_debug_candidate (const void *t, void **candidacy, void *data) | ||
244 | +{ | ||
245 | + debug_tree (t); | ||
246 | + fprintf(stderr, "candidacy: %ld\n data (ignore): %p", *((long *) candidacy), data); | ||
247 | + return true; | ||
248 | +} | ||
249 | +#endif | ||
250 | + | ||
251 | +static void | ||
252 | +tw_init (void) | ||
253 | +{ | ||
254 | + gcc_assert (tw_candidate_list == NULL); | ||
255 | + tw_candidate_list = pointer_map_create (); | ||
256 | +} | ||
257 | + | ||
258 | +static void | ||
259 | +tw_reset (void) | ||
260 | +{ | ||
261 | + if (tw_candidate_list) | ||
262 | + { | ||
263 | + pointer_map_destroy (tw_candidate_list); | ||
264 | + tw_candidate_list = NULL; | ||
265 | + } | ||
266 | +} | ||
267 | + | ||
268 | +/* gcc.dg/torture/pr43879_[12].c | ||
269 | + * Initialized statics should not be widened: | ||
270 | + * | ||
271 | + * void bar(int c) | ||
272 | + * { | ||
273 | + * static int x = 1; // if widened, x gets initialized to (2^32) | ||
274 | + * if (c != x) __builtin_abort(); | ||
275 | + * x--; | ||
276 | + * } | ||
277 | + * | ||
278 | + * int main() | ||
279 | + * { | ||
280 | + * int c = 1; | ||
281 | + * bar (1); | ||
282 | + * return 0; | ||
283 | + * } | ||
284 | + * | ||
285 | + * Likely, the initial value is laid out/translated to RTL way before | ||
286 | + * the rest of the code is translated to GIMPLE; so when we widen the | ||
287 | + * type, it's already too late. | ||
288 | + */ | ||
289 | + | ||
290 | +/* tw_candidate() has no way to tell if it was passed a local variable | ||
291 | + * (or not) - so make sure it is passed local variables or parameters only. | ||
292 | + */ | ||
293 | +static long | ||
294 | +tw_candidate (tree node) | ||
295 | +{ | ||
296 | + long rv = 0; | ||
297 | + | ||
298 | + if (!node || TREE_TYPE (node) == error_mark_node) | ||
299 | + return 0; | ||
300 | + | ||
301 | + if (node && TREE_TYPE (node) != error_mark_node && | ||
302 | + ((TREE_CODE (node) == VAR_DECL && | ||
303 | + /* See note: Initialized statics should not be widened. */ | ||
304 | + (!TREE_STATIC (node) || !DECL_INITIAL (node))) || | ||
305 | + TREE_CODE (node) == PARM_DECL || | ||
306 | + TREE_CODE (node) == DEBUG_EXPR_DECL) && | ||
307 | + !TYPE_VOLATILE (TREE_TYPE (node)) && | ||
308 | + !TREE_ADDRESSABLE (node) && | ||
309 | + !POINTER_TYPE_P (TREE_TYPE (node)) && | ||
310 | + INTEGRAL_TYPE_P (TREE_TYPE (node)) && | ||
311 | + !TYPE_UNSIGNED (TREE_TYPE (node)) && | ||
312 | + (TYPE_PRECISION (TREE_TYPE (node)) < TYPE_PRECISION (long_integer_type_node))) | ||
313 | + rv = 1; | ||
314 | + return rv; | ||
315 | +} | ||
316 | + | ||
317 | +static long | ||
318 | +tw_candidate_const (tree node) | ||
319 | +{ | ||
320 | + long rv = 0; | ||
321 | + | ||
322 | + if (node && TREE_TYPE (node) != error_mark_node && | ||
323 | + INTEGRAL_TYPE_P (TREE_TYPE (node)) && | ||
324 | + TREE_CONSTANT (node) && | ||
325 | + (TYPE_PRECISION (TREE_TYPE (node)) < TYPE_PRECISION (long_integer_type_node))) | ||
326 | + rv = 1; | ||
327 | + return rv; | ||
328 | +} | ||
329 | + | ||
330 | +static long * | ||
331 | +tw_log_candidate (tree node) | ||
332 | +{ | ||
333 | + long *pval = NULL; | ||
334 | + | ||
335 | + if (tw_candidate_list && node && TREE_TYPE (node) != error_mark_node) | ||
336 | + { | ||
337 | + pval = (long *) pointer_map_contains (tw_candidate_list, node); | ||
338 | + if (!pval) | ||
339 | + { | ||
340 | + pval = (long *) pointer_map_insert (tw_candidate_list, node); | ||
341 | + *pval = 1; | ||
342 | + TWDBG_MSG ("Logged variable:\n"); | ||
343 | + TWDBG_TREE (node); | ||
344 | + } | ||
345 | + } | ||
346 | + return pval; | ||
347 | +} | ||
348 | + | ||
349 | +static long | ||
350 | +tw_candidacy_valid (tree node) | ||
351 | +{ | ||
352 | + long rval = 0; | ||
353 | + long *pval = NULL; | ||
354 | + | ||
355 | + if (tw_candidate_list && node && TREE_TYPE (node) != error_mark_node) | ||
356 | + pval = (long *) pointer_map_contains (tw_candidate_list, node); | ||
357 | + if (pval) | ||
358 | + rval = *pval ? 1 : 0; | ||
359 | + return rval; | ||
360 | +} | ||
361 | + | ||
362 | +static void | ||
363 | +tw_candidacy (tree node, long value) | ||
364 | +{ | ||
365 | + long *pval; | ||
366 | + | ||
367 | + if (tw_candidate_list && node) | ||
368 | + { | ||
369 | + pval = (long *) pointer_map_contains (tw_candidate_list, node); | ||
370 | + if (pval) | ||
371 | + { | ||
372 | + *pval = value; | ||
373 | +#if TW_DEBUG | ||
374 | + fprintf (stderr, "Setting candidacy of node:\n"); | ||
375 | + TWDBG_TREE (node); | ||
376 | + fprintf (stderr, "to: %ld\n", value); | ||
377 | +#endif | ||
378 | + } | ||
379 | + } | ||
380 | +} | ||
381 | + | ||
382 | +static long | ||
383 | +tw_in_candidate_list (tree node) | ||
384 | +{ | ||
385 | + long *pval; | ||
386 | + long rval = 0; | ||
387 | + | ||
388 | + if (tw_candidate_list && node && TREE_TYPE (node) != error_mark_node) | ||
389 | + { | ||
390 | + pval = (long *) pointer_map_contains (tw_candidate_list, node); | ||
391 | + rval = pval ? 1 : 0; | ||
392 | + } | ||
393 | + return rval; | ||
394 | +} | ||
395 | + | ||
396 | +static tree | ||
397 | +tw_widen_constant (tree node) | ||
398 | +{ | ||
399 | + if (node && tw_candidate_const (node)) | ||
400 | + node = build_int_cst (long_integer_type_node, TREE_INT_CST_LOW (node)); | ||
401 | + | ||
402 | + return node; | ||
403 | +} | ||
404 | + | ||
405 | +static tree | ||
406 | +tw_widen_variable (tree node) | ||
407 | +{ | ||
408 | + if (node && tw_candidacy_valid (node)) | ||
409 | + { | ||
410 | + TWDBG_MSG ("Widening:\n"); | ||
411 | + TWDBG_TREE(node); | ||
412 | + | ||
413 | + TREE_TYPE (node) = build_qualified_type (long_integer_type_node, | ||
414 | + TYPE_QUALS (TREE_TYPE (node))); | ||
415 | + | ||
416 | + if (TREE_CODE (node) != DEBUG_EXPR_DECL) | ||
417 | + relayout_decl (node); | ||
418 | + } | ||
419 | + return node; | ||
420 | +} | ||
421 | + | ||
422 | +#ifdef TW_FINALIZE_STMTS | ||
423 | +static long | ||
424 | +tw_fn_has_openmp (gimple_seq stmts) | ||
425 | +{ | ||
426 | + gimple_stmt_iterator ittr; | ||
427 | + long found_openmp = 0; | ||
428 | + | ||
429 | + for (ittr = gsi_start (stmts); !gsi_end_p (ittr) && !found_openmp; gsi_next (&ittr)) | ||
430 | + { | ||
431 | + gimple stmt = gsi_stmt (ittr); | ||
432 | + | ||
433 | + switch (gimple_code (stmt)) | ||
434 | + { | ||
435 | + case GIMPLE_BIND: | ||
436 | + found_openmp = tw_fn_has_openmp (gimple_bind_body (stmt)); | ||
437 | + break; | ||
438 | + | ||
439 | + case GIMPLE_TRY: | ||
440 | + found_openmp = tw_fn_has_openmp (gimple_try_eval (stmt)); | ||
441 | + found_openmp = tw_fn_has_openmp (gimple_try_cleanup (stmt)); | ||
442 | + break; | ||
443 | + | ||
444 | + case GIMPLE_EH_FILTER: | ||
445 | + found_openmp = tw_fn_has_openmp (gimple_eh_filter_failure (stmt)); | ||
446 | + break; | ||
447 | + | ||
448 | + case GIMPLE_CATCH: | ||
449 | + found_openmp = tw_fn_has_openmp (gimple_catch_handler (stmt)); | ||
450 | + break; | ||
451 | + | ||
452 | + default: | ||
453 | + switch (gimple_code (stmt)) | ||
454 | + { | ||
455 | + CASE_GIMPLE_OMP: | ||
456 | + found_openmp = 1; | ||
457 | + break; | ||
458 | + default: | ||
459 | + break; | ||
460 | + } | ||
461 | + } | ||
462 | + } | ||
463 | + return found_openmp; | ||
464 | +} | ||
465 | +#endif | ||
466 | + | ||
467 | +/* Originally, we implemented type widening over the emitted GIMPLE | ||
468 | + * sequence. Later on, we discovered that we needed to wait till | ||
469 | + * after OpenMP expansion, so we implemented type widening over the | ||
470 | + * CFG-BB form. | ||
471 | + */ | ||
472 | +#ifdef TW_FINALIZE_STMTS | ||
473 | +struct gimple_opt_pass pass_widen_types_stmts = | ||
474 | +{ | ||
475 | + { | ||
476 | + GIMPLE_PASS, | ||
477 | + "tw-stmts", /* name */ | ||
478 | + NULL, /* gate */ | ||
479 | + tw_finalize_stmts, /* execute */ | ||
480 | + NULL, /* sub */ | ||
481 | + NULL, /* next */ | ||
482 | + 0, /* static_pass_number */ | ||
483 | + TV_NONE, /* tv_id */ | ||
484 | + PROP_gimple_any, /* properties_required */ | ||
485 | + 0, /* properties_provided */ | ||
486 | + 0, /* properties_destroyed */ | ||
487 | + 0, /* todo_flags_start */ | ||
488 | + TODO_dump_func /* todo_flags_finish */ | ||
489 | + } | ||
490 | +}; | ||
491 | +#endif | ||
492 | + | ||
493 | +struct gimple_opt_pass pass_widen_types_bbs = | ||
494 | +{ | ||
495 | + { | ||
496 | + GIMPLE_PASS, | ||
497 | + "tw-bbs", /* name */ | ||
498 | + NULL, /* gate */ | ||
499 | + tw_finalize_bbs, /* execute */ | ||
500 | + NULL, /* sub */ | ||
501 | + NULL, /* next */ | ||
502 | + 0, /* static_pass_number */ | ||
503 | + TV_NONE, /* tv_id */ | ||
504 | + PROP_gimple_any, /* properties_required */ | ||
505 | + 0, /* properties_provided */ | ||
506 | + 0, /* properties_destroyed */ | ||
507 | + 0, /* todo_flags_start */ | ||
508 | + TODO_dump_func /* todo_flags_finish */ | ||
509 | + } | ||
510 | +}; | ||
511 | + | ||
512 | +static | ||
513 | +void | ||
514 | +tw_log_parms (tree fndecl) | ||
515 | +{ | ||
516 | + tree parm; | ||
517 | + | ||
518 | + if (!fndecl) | ||
519 | + return; | ||
520 | + for (parm = DECL_ARGUMENTS (fndecl); parm; parm = DECL_CHAIN (parm)) | ||
521 | + if (tw_candidate (parm)) | ||
522 | + tw_log_candidate (parm); | ||
523 | + return; | ||
524 | +} | ||
525 | + | ||
526 | +#ifdef TW_FINALIZE_STMTS | ||
527 | +static | ||
528 | +void | ||
529 | +tw_log_vars (gimple_seq stmts) | ||
530 | +{ | ||
531 | + gimple_stmt_iterator ittr; | ||
532 | + tree vars, vindex; | ||
533 | + | ||
534 | + if (!stmts) | ||
535 | + return; | ||
536 | + | ||
537 | + gcc_assert (tw_candidate_list != NULL); | ||
538 | + | ||
539 | + for (ittr = gsi_start (stmts); !gsi_end_p (ittr); gsi_next (&ittr)) | ||
540 | + { | ||
541 | + gimple stmt = gsi_stmt (ittr); | ||
542 | + | ||
543 | + switch (gimple_code (stmt)) | ||
544 | + { | ||
545 | + case GIMPLE_BIND: | ||
546 | + vars = gimple_bind_vars (stmt); | ||
547 | + for (vindex = vars; vindex; vindex = DECL_CHAIN (vindex)) | ||
548 | + if (tw_candidate (vindex)) | ||
549 | + tw_log_candidate (vindex); | ||
550 | + tw_log_vars (gimple_bind_body (stmt)); | ||
551 | + break; | ||
552 | + | ||
553 | + case GIMPLE_TRY: | ||
554 | + tw_log_vars (gimple_try_eval (stmt)); | ||
555 | + tw_log_vars (gimple_try_cleanup (stmt)); | ||
556 | + break; | ||
557 | + | ||
558 | + case GIMPLE_EH_FILTER: | ||
559 | + tw_log_vars (gimple_eh_filter_failure (stmt)); | ||
560 | + break; | ||
561 | + | ||
562 | + case GIMPLE_CATCH: | ||
563 | + tw_log_vars (gimple_catch_handler (stmt)); | ||
564 | + break; | ||
565 | + | ||
566 | + default: | ||
567 | + break; | ||
568 | + } | ||
569 | + } | ||
570 | + | ||
571 | + return; | ||
572 | +} | ||
573 | +#endif | ||
574 | + | ||
575 | +static | ||
576 | +void | ||
577 | +tw_log_local_decls (void) | ||
578 | +{ | ||
579 | + tree decl; | ||
580 | + unsigned ix; | ||
581 | + | ||
582 | + FOR_EACH_LOCAL_DECL (cfun, ix, decl) | ||
583 | + { | ||
584 | + TWDBG_MSG ("Testing decl:\n"); | ||
585 | + TWDBG_TREE (decl); | ||
586 | + if (tw_candidate (decl)) | ||
587 | + tw_log_candidate (decl); | ||
588 | + } | ||
589 | +} | ||
590 | + | ||
591 | +/* Widen types. tw_finalize_stmts () can be run anytime immediately after | ||
592 | + * gimplification but before the CFG pass (see comment * accompanying | ||
593 | + * gimple_body ()). | ||
594 | + * | ||
595 | + * After gimplification has occurred, the emitted GIMPLE is | ||
596 | + * scanned to check if these variables are only used among | ||
597 | + * themselves (with the exception of being cast to unsigned long); | ||
598 | + * invalidating the candidacy of any variable that is used with | ||
599 | + * another outside this set (and so on recursively). The variables | ||
600 | + * that remain after this process all occur in operations with other | ||
601 | + * such candidate variables, (or with constants) - the type of all | ||
602 | + * such residual candidate variables (and of constants that appear | ||
603 | + * with these in operations) is changed to long (along with the | ||
604 | + * original accompannying qualifiers on the type). | ||
605 | + * | ||
606 | + * void | ||
607 | + * init_optimization_passes (void) | ||
608 | + * | ||
609 | + * p = &all_lowering_passes; | ||
610 | + * NEXT_PASS (pass_widen_types_stmts); | ||
611 | + * NEXT_PASS (pass_warn_unused_result); | ||
612 | + */ | ||
613 | +#ifdef TW_FINALIZE_STMTS | ||
614 | +static | ||
615 | +unsigned int | ||
616 | +tw_finalize_stmts (void) | ||
617 | +{ | ||
618 | + long iv = 0; | ||
619 | + gimple_seq stmts; | ||
620 | + tree fndecl = current_function_decl; | ||
621 | + | ||
622 | + if (strcmp (lang_hooks.name, "GNU C") != 0 || | ||
623 | + seen_error () || | ||
624 | + !flag_strict_overflow || | ||
625 | + !flag_widen_types) | ||
626 | + { | ||
627 | + TWDBG_MSG ("Skipping: Language not C or seen error or -fno-strict-overflow or -fno-widen-types\n"); | ||
628 | + return 0; | ||
629 | + } | ||
630 | + | ||
631 | + /* gcc.dg/pr23518.c execution test */ | ||
632 | + if (flag_wrapv) | ||
633 | + { | ||
634 | + TWDBG_MSG ("Skipping: -fwrapv specified.\n"); | ||
635 | + return 0; | ||
636 | + } | ||
637 | + | ||
638 | + if (debug_info_level == DINFO_LEVEL_NONE) | ||
639 | + { | ||
640 | + /* PS: That we cannot call relayout_decl () on DEBUG_EXPR_DECL is an | ||
641 | + * issue: Debug information is generated after lowering from tree to | ||
642 | + * GIMPLE; unless we widen before debug information is generated, the | ||
643 | + * debug information will record pre-widening information - and that | ||
644 | + * cannot be changed because relayout_decl () cannot be invoked on | ||
645 | + * DEBUG_EXPR_DECL. expand_debug_locations () during cfgexpand will | ||
646 | + * fail gcc_assert ()'s on the DEBUG_INSN's since e.g. the modes will | ||
647 | + * not agree, etc. So if we are compiling -g, we ought to run the | ||
648 | + * pass_widen_types_stmts. | ||
649 | + * | ||
650 | + * In short: pass_widen_types_stmts runs iff we're generating debug | ||
651 | + * information. | ||
652 | + */ | ||
653 | + TWDBG_MSG ("Skipping: Debug level none.\n"); | ||
654 | + return 0; | ||
655 | + } | ||
656 | + gcc_assert (debug_info_level != DINFO_LEVEL_NONE); | ||
657 | + | ||
658 | + if (!fndecl) | ||
659 | + { | ||
660 | + TWDBG_MSG ("Skipping: !fndecl.\n"); | ||
661 | + return 0; | ||
662 | + } | ||
663 | + | ||
664 | + TWDBG_MSG ("Widening function:\n"); | ||
665 | + TWDBG_TREE (fndecl); | ||
666 | + | ||
667 | + stmts = gimple_body (fndecl); | ||
668 | + | ||
669 | + if (!stmts) | ||
670 | + { | ||
671 | + TWDBG_MSG ("Skipping: !stmts.\n"); | ||
672 | + return 0; | ||
673 | + } | ||
674 | + | ||
675 | + if (tw_fn_has_openmp (stmts)) | ||
676 | + { | ||
677 | + TWDBG_MSG ("Skipping: OpenMP stmts found.\n"); | ||
678 | + return 0; | ||
679 | + } | ||
680 | + | ||
681 | + /* Assume for now that we do not need to check for nested functions: | ||
682 | + * (cgraph_get_node (fndecl) && cgraph_get_node (fndecl)->nested != NULL) || | ||
683 | + * TREE_CODE (DECL_CONTEXT (fndecl)) != TRANSLATION_UNIT_DECL || | ||
684 | + * Well, turns out that a nested function is processed only if it is | ||
685 | + * actually invoked from within the function, so we are in good shape. | ||
686 | + */ | ||
687 | + | ||
688 | + tw_init (); | ||
689 | + tw_log_parms (fndecl); | ||
690 | + tw_log_vars (stmts); | ||
691 | +#if TW_DEBUG | ||
692 | + tw_dump_candidate_list (); | ||
693 | +#endif | ||
694 | + | ||
695 | + do | ||
696 | + { | ||
697 | + iv = tw_gimple_in_seq (stmts, 0); | ||
698 | + } while (iv); | ||
699 | + tw_gimple_in_seq (stmts, 1); | ||
700 | + verify_types_in_gimple_seq (stmts); | ||
701 | + | ||
702 | + tw_reset (); | ||
703 | + | ||
704 | + return 0; | ||
705 | +} | ||
706 | +#endif | ||
707 | + | ||
708 | +static | ||
709 | +unsigned int | ||
710 | +tw_finalize_bbs (void) | ||
711 | +{ | ||
712 | + long iv = 0; | ||
713 | + basic_block bb; | ||
714 | + tree fndecl; | ||
715 | + | ||
716 | + if (strcmp (lang_hooks.name, "GNU C") != 0 || | ||
717 | + seen_error () || | ||
718 | + !flag_strict_overflow || | ||
719 | + !flag_widen_types) | ||
720 | + { | ||
721 | + TWDBG_MSG ("Skipping: Language not C or seen error or -fno-strict-overflow or -fno-widen-types\n"); | ||
722 | + return 0; | ||
723 | + } | ||
724 | + | ||
725 | + /* gcc.dg/pr23518.c execution test */ | ||
726 | + if (flag_wrapv) | ||
727 | + { | ||
728 | + TWDBG_MSG ("Skipping: -fwrapv specified.\n"); | ||
729 | + return 0; | ||
730 | + } | ||
731 | + | ||
732 | + if (debug_info_level != DINFO_LEVEL_NONE && flag_openmp) | ||
733 | + { | ||
734 | + /* Cannot run this pass as the debug information has already | ||
735 | + * been recorded; If we type widen now, it'll lead to assert | ||
736 | + * failures during RTL expansion in expandcfg.c since the | ||
737 | + * debug information would all be prewidening and would | ||
738 | + * mismatch with the postwidening information for the variables | ||
739 | + * that got widened (but whoose debug information was already | ||
740 | + * generated). This is all because we cannot call relayout_decl () | ||
741 | + * on DEBUG_EXPR_DECL's - see note elsewhere. | ||
742 | + */ | ||
743 | + TWDBG_MSG ("Skipping: Non-zero debug level and -fopenmp specified.\n"); | ||
744 | + return 0; | ||
745 | + } | ||
746 | + | ||
747 | + if (!cfun || !(fndecl = cfun->decl) || !(cfun->cfg)) | ||
748 | + { | ||
749 | + TWDBG_MSG ("Skipping: !cfun or !fndecl or !(cfun->cfg).\n"); | ||
750 | + return 0; | ||
751 | + } | ||
752 | + | ||
753 | + TWDBG_MSG ("Widening function:\n"); | ||
754 | + TWDBG_TREE (fndecl); | ||
755 | + | ||
756 | + /* Assume for now that we do not need to check for nested functions: | ||
757 | + * (cgraph_get_node (fndecl) && cgraph_get_node (fndecl)->nested != NULL) || | ||
758 | + * TREE_CODE (DECL_CONTEXT (fndecl)) != TRANSLATION_UNIT_DECL || | ||
759 | + * Well, turns out that a nested function is processed only if it is | ||
760 | + * actually invoked from within the function, so we are in good shape. | ||
761 | + */ | ||
762 | + | ||
763 | + tw_init (); | ||
764 | + tw_log_parms (fndecl); | ||
765 | + tw_log_local_decls (); | ||
766 | +#if TW_DEBUG | ||
767 | + tw_dump_candidate_list (); | ||
768 | +#endif | ||
769 | + | ||
770 | + do | ||
771 | + { | ||
772 | + iv = 0; | ||
773 | + FOR_EACH_BB (bb) | ||
774 | + iv += tw_gimple_in_bb (bb, 0); | ||
775 | + } while (iv); | ||
776 | + FOR_EACH_BB (bb) | ||
777 | + tw_gimple_in_bb (bb, 1); | ||
778 | + FOR_EACH_BB (bb) | ||
779 | + verify_types_in_gimple_seq (bb_seq (bb)); | ||
780 | + | ||
781 | + tw_reset (); | ||
782 | + | ||
783 | + return 0; | ||
784 | +} | ||
785 | + | ||
786 | +/* Assumes that we have run verify_gimple_in_seq (stmts) | ||
787 | + * i.e. that we have valid gimple. | ||
788 | + */ | ||
789 | +static long | ||
790 | +tw_gimple_in_seq (gimple_seq stmts, long widen) | ||
791 | +{ | ||
792 | + gimple_stmt_iterator ittr; | ||
793 | + long iv = 0; | ||
794 | + | ||
795 | + for (ittr = gsi_start (stmts); !gsi_end_p (ittr); gsi_next (&ittr)) | ||
796 | + { | ||
797 | + gimple stmt = gsi_stmt (ittr); | ||
798 | + iv += tw_switch (stmt, widen); | ||
799 | + } | ||
800 | + return iv; | ||
801 | +} | ||
802 | + | ||
803 | +static long | ||
804 | +tw_gimple_in_bb (basic_block bb, long widen) | ||
805 | +{ | ||
806 | + gimple_stmt_iterator ittr; | ||
807 | + long iv = 0; | ||
808 | + | ||
809 | +#if TW_DEBUG | ||
810 | + fprintf (stderr, "Dumping basic block (widen = %ld):\n", widen); | ||
811 | + debug_bb (bb); | ||
812 | + fprintf (stderr, "Done dumping basic block (widen = %ld)\n", widen); | ||
813 | +#endif | ||
814 | + for (ittr = gsi_start_bb (bb); !gsi_end_p (ittr); gsi_next (&ittr)) | ||
815 | + { | ||
816 | + gimple stmt = gsi_stmt (ittr); | ||
817 | + iv += tw_switch (stmt, widen); | ||
818 | + } | ||
819 | + return iv; | ||
820 | +} | ||
821 | + | ||
822 | +static long | ||
823 | +tw_switch (gimple stmt, long widen) | ||
824 | +{ | ||
825 | + long iv = 0; | ||
826 | + | ||
827 | + switch (gimple_code (stmt)) | ||
828 | + { | ||
829 | + case GIMPLE_BIND: | ||
830 | + iv += tw_gimple_in_seq (gimple_bind_body (stmt), widen); | ||
831 | + break; | ||
832 | + | ||
833 | + case GIMPLE_TRY: | ||
834 | + iv += tw_gimple_in_seq (gimple_try_eval (stmt), widen); | ||
835 | + iv += tw_gimple_in_seq (gimple_try_cleanup (stmt), widen); | ||
836 | + break; | ||
837 | + | ||
838 | + case GIMPLE_EH_FILTER: | ||
839 | + iv += tw_gimple_in_seq (gimple_eh_filter_failure (stmt), widen); | ||
840 | + break; | ||
841 | + | ||
842 | + case GIMPLE_CATCH: | ||
843 | + iv += tw_gimple_in_seq (gimple_catch_handler (stmt), widen); | ||
844 | + break; | ||
845 | + | ||
846 | + default: | ||
847 | + iv += tw_gimple_stmt (stmt, widen); | ||
848 | + break; | ||
849 | + } | ||
850 | + return iv; | ||
851 | +} | ||
852 | + | ||
853 | +/* tw_gimple_stmt () mimics verify_gimple_stmt () | ||
854 | + */ | ||
855 | +static long | ||
856 | +tw_gimple_stmt (gimple stmt, long widen) | ||
857 | +{ | ||
858 | + long iv = 0; | ||
859 | + | ||
860 | + switch (gimple_code (stmt)) | ||
861 | + { | ||
862 | + case GIMPLE_ASSIGN: | ||
863 | + iv = tw_gimple_assign (stmt, widen); | ||
864 | + break; | ||
865 | + | ||
866 | + case GIMPLE_CALL: | ||
867 | + iv = tw_gimple_call (stmt, widen); | ||
868 | + break; | ||
869 | + | ||
870 | + case GIMPLE_COND: | ||
871 | + iv = tw_gimple_comparison (stmt, widen); | ||
872 | + break; | ||
873 | + | ||
874 | + case GIMPLE_SWITCH: | ||
875 | + iv = tw_gimple_switch (stmt, widen); | ||
876 | + break; | ||
877 | + | ||
878 | + case GIMPLE_RETURN: | ||
879 | + iv = tw_gimple_return (stmt, widen); | ||
880 | + break; | ||
881 | + | ||
882 | + case GIMPLE_LABEL: | ||
883 | + TWDBG_STMT(stmt); | ||
884 | + break; | ||
885 | + | ||
886 | + case GIMPLE_GOTO: | ||
887 | + TWDBG_STMT(stmt); | ||
888 | + break; | ||
889 | + | ||
890 | + case GIMPLE_ASM: | ||
891 | + iv = tw_gimple_asm (stmt, widen); | ||
892 | + break; | ||
893 | + | ||
894 | + /* Tuples that do not have tree operands. */ | ||
895 | + case GIMPLE_NOP: | ||
896 | + case GIMPLE_PREDICT: | ||
897 | + case GIMPLE_RESX: | ||
898 | + case GIMPLE_EH_DISPATCH: | ||
899 | + case GIMPLE_EH_MUST_NOT_THROW: | ||
900 | + TWDBG_STMT(stmt); | ||
901 | + break; | ||
902 | + | ||
903 | + CASE_GIMPLE_OMP: | ||
904 | + TWDBG_STMT(stmt); | ||
905 | + break; | ||
906 | + | ||
907 | + case GIMPLE_DEBUG: | ||
908 | + iv = tw_gimple_debug (stmt, widen); | ||
909 | + break; | ||
910 | + | ||
911 | + default: | ||
912 | + gcc_unreachable (); | ||
913 | + } | ||
914 | + return iv; | ||
915 | +} | ||
916 | + | ||
917 | +static long | ||
918 | +tw_gimple_assign (gimple stmt, long widen) | ||
919 | +{ | ||
920 | + long iv = 0; | ||
921 | + | ||
922 | + switch (gimple_assign_rhs_class (stmt)) | ||
923 | + { | ||
924 | + case GIMPLE_SINGLE_RHS: | ||
925 | + iv = tw_gimple_assign_single (stmt, widen); | ||
926 | + break; | ||
927 | + | ||
928 | + case GIMPLE_UNARY_RHS: | ||
929 | + iv = tw_gimple_assign_unary (stmt, widen); | ||
930 | + break; | ||
931 | + | ||
932 | + case GIMPLE_BINARY_RHS: | ||
933 | + iv = tw_gimple_assign_binary (stmt, widen); | ||
934 | + break; | ||
935 | + | ||
936 | + case GIMPLE_TERNARY_RHS: | ||
937 | + iv = tw_gimple_assign_ternary (stmt, widen); | ||
938 | + break; | ||
939 | + | ||
940 | + default: | ||
941 | + gcc_unreachable (); | ||
942 | + } | ||
943 | + return iv; | ||
944 | +} | ||
945 | + | ||
946 | +static long | ||
947 | +tw_gimple_assign_single (gimple stmt, long widen) | ||
948 | +{ | ||
949 | + tree lhs = gimple_assign_lhs (stmt); | ||
950 | + tree rhs1 = gimple_assign_rhs1 (stmt); | ||
951 | + tree value; | ||
952 | + long iv = 0; | ||
953 | + unsigned int idx; | ||
954 | + | ||
955 | + TWDBG_STMT(stmt); | ||
956 | + TWDBG_TREE(lhs); | ||
957 | + TWDBG_TREE(rhs1); | ||
958 | + | ||
959 | + if (widen) | ||
960 | + { | ||
961 | + TWDBG_MSG ("Widening run.\n"); | ||
962 | + if (TREE_CODE (rhs1) == ARRAY_REF && | ||
963 | + tw_candidacy_valid (TREE_OPERAND (rhs1, 1))) | ||
964 | + { | ||
965 | + /* Note that we are widening the array index, hence no | ||
966 | + * gimple_assign_set_rhs1 () */ | ||
967 | + tw_widen_variable (TREE_OPERAND (rhs1, 1)); | ||
968 | + } | ||
969 | + else if (TREE_CODE (lhs) == ARRAY_REF && | ||
970 | + tw_candidacy_valid (TREE_OPERAND (lhs, 1))) | ||
971 | + { | ||
972 | + /* Note that we are widening the array index, hence no | ||
973 | + * gimple_assign_set_lhs () */ | ||
974 | + tw_widen_variable (TREE_OPERAND (lhs, 1)); | ||
975 | + } | ||
976 | + else if (tw_candidacy_valid (lhs) && tw_candidate_const (rhs1)) | ||
977 | + { | ||
978 | + gimple_assign_set_lhs (stmt, tw_widen_variable (lhs)); | ||
979 | + gimple_assign_set_rhs1 (stmt, tw_widen_constant (rhs1)); | ||
980 | + } | ||
981 | + else if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs1)) | ||
982 | + { | ||
983 | + gimple_assign_set_lhs (stmt, tw_widen_variable (lhs)); | ||
984 | + gimple_assign_set_rhs1 (stmt, tw_widen_variable (rhs1)); | ||
985 | + } | ||
986 | + } | ||
987 | + else | ||
988 | + { | ||
989 | + TWDBG_MSG ("Validating run.\n"); | ||
990 | + if (tw_candidacy_valid (lhs) && tw_candidate_const (rhs1)) | ||
991 | + return iv; | ||
992 | + if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs1)) | ||
993 | + return iv; | ||
994 | + if (TREE_CODE (lhs) == VAR_DECL && TREE_CODE (TREE_TYPE (lhs)) == VECTOR_TYPE && | ||
995 | + TREE_CODE (rhs1) == CONSTRUCTOR && TREE_CODE (TREE_TYPE (rhs1)) == VECTOR_TYPE) | ||
996 | + { | ||
997 | + FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (rhs1), idx, value) | ||
998 | + { | ||
999 | + if (tw_candidacy_valid (value)) | ||
1000 | + { | ||
1001 | + TWDBG_MSG ("Invalidating candidacy of constructor element:\n"); | ||
1002 | + TWDBG_TREE (value); | ||
1003 | + tw_candidacy (value, 0); | ||
1004 | + iv++; | ||
1005 | + } | ||
1006 | + } | ||
1007 | + } | ||
1008 | + if (tw_candidacy_valid (lhs)) | ||
1009 | + { | ||
1010 | + tw_candidacy (lhs, 0); | ||
1011 | + iv++; | ||
1012 | + } | ||
1013 | + if (tw_candidacy_valid (rhs1)) | ||
1014 | + { | ||
1015 | + tw_candidacy (rhs1, 0); | ||
1016 | + iv++; | ||
1017 | + } | ||
1018 | + } | ||
1019 | + return iv; | ||
1020 | +} | ||
1021 | + | ||
1022 | +static long | ||
1023 | +tw_gimple_assign_unary (gimple stmt, long widen) | ||
1024 | +{ | ||
1025 | + tree lhs = gimple_assign_lhs (stmt); | ||
1026 | + tree rhs1 = gimple_assign_rhs1 (stmt); | ||
1027 | + long iv = 0; | ||
1028 | + | ||
1029 | + TWDBG_STMT(stmt); | ||
1030 | + TWDBG_TREE(lhs); | ||
1031 | + TWDBG_TREE(rhs1); | ||
1032 | + | ||
1033 | + if (widen) | ||
1034 | + { | ||
1035 | + TWDBG_MSG ("Widening run.\n"); | ||
1036 | + if (gimple_assign_rhs_code (stmt) == NOP_EXPR && | ||
1037 | + tw_candidacy_valid (rhs1) && | ||
1038 | + (TREE_TYPE (lhs) == long_unsigned_type_node || | ||
1039 | + TREE_TYPE (lhs) == long_integer_type_node)) | ||
1040 | + gimple_assign_set_rhs1 (stmt, tw_widen_variable (rhs1)); | ||
1041 | + } | ||
1042 | + else | ||
1043 | + { | ||
1044 | + TWDBG_MSG ("Validating run.\n"); | ||
1045 | + if (gimple_assign_rhs_code (stmt) == NOP_EXPR && | ||
1046 | + tw_candidacy_valid (rhs1) && | ||
1047 | + (TREE_TYPE (lhs) == long_unsigned_type_node || | ||
1048 | + TREE_TYPE (lhs) == long_integer_type_node)) | ||
1049 | + return iv; | ||
1050 | + if (tw_candidacy_valid (lhs)) | ||
1051 | + { | ||
1052 | + tw_candidacy (lhs, 0); | ||
1053 | + iv++; | ||
1054 | + } | ||
1055 | + if (tw_candidacy_valid (rhs1)) | ||
1056 | + { | ||
1057 | + tw_candidacy (rhs1, 0); | ||
1058 | + iv++; | ||
1059 | + } | ||
1060 | + } | ||
1061 | + return iv; | ||
1062 | +} | ||
1063 | + | ||
1064 | +static long | ||
1065 | +tw_gimple_assign_binary (gimple stmt, long widen) | ||
1066 | +{ | ||
1067 | + tree lhs = gimple_assign_lhs (stmt); | ||
1068 | + tree rhs1 = gimple_assign_rhs1 (stmt); | ||
1069 | + tree rhs2 = gimple_assign_rhs2 (stmt); | ||
1070 | + long iv = 0; | ||
1071 | + | ||
1072 | + TWDBG_STMT(stmt); | ||
1073 | + TWDBG_TREE(lhs); | ||
1074 | + TWDBG_TREE(rhs1); | ||
1075 | + TWDBG_TREE(rhs2); | ||
1076 | + | ||
1077 | + if (widen) | ||
1078 | + { | ||
1079 | + TWDBG_MSG ("Widening run.\n"); | ||
1080 | + if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs1) && tw_candidate_const (rhs2)) | ||
1081 | + { | ||
1082 | + gimple_assign_set_lhs (stmt, tw_widen_variable (lhs)); | ||
1083 | + gimple_assign_set_rhs1 (stmt, tw_widen_variable (rhs1)); | ||
1084 | + gimple_assign_set_rhs2 (stmt, tw_widen_constant (rhs2)); | ||
1085 | + } | ||
1086 | + else if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs1) && tw_candidacy_valid (rhs2)) | ||
1087 | + { | ||
1088 | + gimple_assign_set_lhs (stmt, tw_widen_variable (lhs)); | ||
1089 | + gimple_assign_set_rhs1 (stmt, tw_widen_variable (rhs1)); | ||
1090 | + gimple_assign_set_rhs2 (stmt, tw_widen_variable (rhs2)); | ||
1091 | + } | ||
1092 | + } | ||
1093 | + else | ||
1094 | + { | ||
1095 | + TWDBG_MSG ("Validating run.\n"); | ||
1096 | + if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs1) && tw_candidate_const (rhs2)) | ||
1097 | + return iv; | ||
1098 | + if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs1) && tw_candidacy_valid (rhs2)) | ||
1099 | + return iv; | ||
1100 | + if (tw_candidacy_valid (lhs)) | ||
1101 | + { | ||
1102 | + tw_candidacy (lhs, 0); | ||
1103 | + iv++; | ||
1104 | + } | ||
1105 | + if (tw_candidacy_valid (rhs1)) | ||
1106 | + { | ||
1107 | + tw_candidacy (rhs1, 0); | ||
1108 | + iv++; | ||
1109 | + } | ||
1110 | + if (tw_candidacy_valid (rhs2)) | ||
1111 | + { | ||
1112 | + tw_candidacy (rhs2, 0); | ||
1113 | + iv++; | ||
1114 | + } | ||
1115 | + } | ||
1116 | + return iv; | ||
1117 | +} | ||
1118 | + | ||
1119 | +static long | ||
1120 | +tw_gimple_assign_ternary (gimple stmt, long widen) | ||
1121 | +{ | ||
1122 | + tree lhs = gimple_assign_lhs (stmt); | ||
1123 | + tree rhs1 = gimple_assign_rhs1 (stmt); | ||
1124 | + tree rhs2 = gimple_assign_rhs2 (stmt); | ||
1125 | + tree rhs3 = gimple_assign_rhs3 (stmt); | ||
1126 | + long iv = 0; | ||
1127 | + | ||
1128 | + TWDBG_STMT(stmt); | ||
1129 | + TWDBG_TREE(lhs); | ||
1130 | + TWDBG_TREE(rhs1); | ||
1131 | + TWDBG_TREE(rhs2); | ||
1132 | + TWDBG_TREE(rhs3); | ||
1133 | + | ||
1134 | + if (widen) | ||
1135 | + { | ||
1136 | + TWDBG_MSG ("Widening run.\n"); | ||
1137 | + return iv; | ||
1138 | + } | ||
1139 | + | ||
1140 | + TWDBG_MSG ("Validating run.\n"); | ||
1141 | + if (tw_candidacy_valid (lhs)) | ||
1142 | + { | ||
1143 | + tw_candidacy (lhs, 0); | ||
1144 | + iv++; | ||
1145 | + } | ||
1146 | + if (tw_candidacy_valid (rhs1)) | ||
1147 | + { | ||
1148 | + tw_candidacy (rhs1, 0); | ||
1149 | + iv++; | ||
1150 | + } | ||
1151 | + if (tw_candidacy_valid (rhs2)) | ||
1152 | + { | ||
1153 | + tw_candidacy (rhs2, 0); | ||
1154 | + iv++; | ||
1155 | + } | ||
1156 | + if (tw_candidacy_valid (rhs3)) | ||
1157 | + { | ||
1158 | + tw_candidacy (rhs3, 0); | ||
1159 | + iv++; | ||
1160 | + } | ||
1161 | + return iv; | ||
1162 | +} | ||
1163 | + | ||
1164 | +/* Ref. WG14/N1256 Committee Draft - September 7, 2007 ISO/IEC 9899:TC3 | ||
1165 | + * 7.19.6 Formatted input/output functions | ||
1166 | + * Sec. 17.19.6.[1 ... 14] | ||
1167 | + */ | ||
1168 | +#define IO_FN_COUNT 14 | ||
1169 | +static const char *IO_fn_names[IO_FN_COUNT] = | ||
1170 | +{ | ||
1171 | + "fprintf", "fscanf", | ||
1172 | + "printf", "scanf", | ||
1173 | + "snprintf", | ||
1174 | + "sprintf", "sscanf", | ||
1175 | + "vfprintf", "vfscanf", | ||
1176 | + "vprintf", "vscanf", | ||
1177 | + "vsnprintf", | ||
1178 | + "vsprintf", "vsscanf", | ||
1179 | +}; | ||
1180 | + | ||
1181 | +static bool | ||
1182 | +is_formatted_IO_fn (tree decl) | ||
1183 | +{ | ||
1184 | + const char *fn_name; | ||
1185 | + long i; | ||
1186 | + | ||
1187 | + if (decl && TREE_CODE (decl) == FUNCTION_DECL && | ||
1188 | + DECL_NAME (decl) /* TREE_CODE (decl) == IDENTIFIER_NODE */ && | ||
1189 | + (fn_name = IDENTIFIER_POINTER (DECL_NAME (decl)))) | ||
1190 | + { | ||
1191 | + for (i = 0; i < IO_FN_COUNT; i++) | ||
1192 | + if (strcmp (IO_fn_names[i], fn_name) == 0) | ||
1193 | + return true; | ||
1194 | + } | ||
1195 | + return false; | ||
1196 | +} | ||
1197 | + | ||
1198 | +/* TODO: If you have: | ||
1199 | + * | ||
1200 | + * int i, n, f(); | ||
1201 | + * | ||
1202 | + * n = f(); | ||
1203 | + * | ||
1204 | + * for (i = 0; i < n; i++) | ||
1205 | + * // stuff | ||
1206 | + * | ||
1207 | + * then (after the candidate set stabilizes) do: | ||
1208 | + * | ||
1209 | + * int n, f(); | ||
1210 | + * long twl.n; | ||
1211 | + * | ||
1212 | + * n = f(); | ||
1213 | + * twl.n = (long) n; | ||
1214 | + * | ||
1215 | + * for (i = 0; i < twl.n; i++) | ||
1216 | + * // stuff | ||
1217 | + * | ||
1218 | + * only if adding twl.n does not decrease the size of the stabilized | ||
1219 | + * candidate set or "cause any other damage". | ||
1220 | + * | ||
1221 | + * This should help in benchmarks where parameters are set via function | ||
1222 | + * calls to prevent them from being optimized away. | ||
1223 | + * | ||
1224 | + */ | ||
1225 | +static long | ||
1226 | +tw_gimple_call (gimple stmt, long widen) | ||
1227 | +{ | ||
1228 | +#if TW_DEBUG | ||
1229 | + tree fn = gimple_call_fn (stmt); | ||
1230 | +#endif | ||
1231 | + long iv = 0; | ||
1232 | + unsigned i; | ||
1233 | + tree arg; | ||
1234 | + | ||
1235 | + TWDBG_STMT(stmt); | ||
1236 | + TWDBG_TREE(fn); | ||
1237 | + TWDBG_TREE(gimple_call_fndecl (stmt)); | ||
1238 | + | ||
1239 | + if (widen) | ||
1240 | + { | ||
1241 | + TWDBG_MSG ("Widening run.\n"); | ||
1242 | + for (i = 0; i < gimple_call_num_args (stmt); i++) | ||
1243 | + { | ||
1244 | + arg = gimple_call_arg (stmt, i); | ||
1245 | + if (arg && tw_candidacy_valid (arg)) | ||
1246 | + gimple_call_set_arg (stmt, i, tw_widen_variable (arg)); | ||
1247 | + } | ||
1248 | + return iv; | ||
1249 | + } | ||
1250 | + | ||
1251 | + TWDBG_MSG ("Validating run.\n"); | ||
1252 | + if (gimple_call_lhs (stmt) && tw_candidacy_valid (gimple_call_lhs (stmt))) | ||
1253 | + { | ||
1254 | + tw_candidacy (gimple_call_lhs (stmt), 0); | ||
1255 | + iv++; | ||
1256 | + } | ||
1257 | + if (gimple_call_fndecl (stmt) && | ||
1258 | + (is_builtin_fn (gimple_call_fndecl (stmt)) || | ||
1259 | + is_formatted_IO_fn (gimple_call_fndecl (stmt)))) | ||
1260 | + { | ||
1261 | + /* Certain types of function (printf-scanf family, | ||
1262 | + * formatted IO functions, builtin functions) ought | ||
1263 | + * not to have their args widened. | ||
1264 | + * | ||
1265 | + * e.g. A call to printf () such as: | ||
1266 | + * int x; | ||
1267 | + * printf ("%d", x); | ||
1268 | + * because, we cannot change the %d to a %ld. | ||
1269 | + * | ||
1270 | + * or e.g. in: | ||
1271 | + * | ||
1272 | + * int D.2852; | ||
1273 | + * int si; | ||
1274 | + * | ||
1275 | + * si = 2; | ||
1276 | + * __builtin_altivec_dst (&vi, si, 0); | ||
1277 | + * D.2852 = 0; | ||
1278 | + * | ||
1279 | + * si should not be widened. | ||
1280 | + * | ||
1281 | + * PS: We could generate code for casts to their original types in the | ||
1282 | + * call, but that would slow-down performance and we do not expect | ||
1283 | + * a loop index to be used in a call to a formatted IO function. | ||
1284 | + */ | ||
1285 | + for (i = 0; i < gimple_call_num_args (stmt); i++) | ||
1286 | + { | ||
1287 | + arg = gimple_call_arg (stmt, i); | ||
1288 | + if (arg && tw_candidacy_valid (arg)) | ||
1289 | + { | ||
1290 | + tw_candidacy (arg, 0); | ||
1291 | + iv++; | ||
1292 | + } | ||
1293 | + } | ||
1294 | + } | ||
1295 | + return iv; | ||
1296 | +} | ||
1297 | + | ||
1298 | +static long | ||
1299 | +tw_gimple_comparison (gimple stmt, long widen) | ||
1300 | +{ | ||
1301 | + tree lhs = gimple_cond_lhs (stmt); | ||
1302 | + tree rhs = gimple_cond_rhs (stmt); | ||
1303 | + long iv = 0; | ||
1304 | + | ||
1305 | + TWDBG_STMT(stmt); | ||
1306 | + TWDBG_TREE(lhs); | ||
1307 | + TWDBG_TREE(rhs); | ||
1308 | + | ||
1309 | + if (widen) | ||
1310 | + { | ||
1311 | + TWDBG_MSG ("Widening run.\n"); | ||
1312 | + if (tw_candidacy_valid (lhs) && tw_candidate_const (rhs)) | ||
1313 | + { | ||
1314 | + gimple_cond_set_lhs (stmt, tw_widen_variable (lhs)); | ||
1315 | + gimple_cond_set_rhs (stmt, tw_widen_constant (rhs)); | ||
1316 | + } | ||
1317 | + else if (tw_candidate_const (lhs) && tw_candidacy_valid (rhs)) | ||
1318 | + { | ||
1319 | + gimple_cond_set_lhs (stmt, tw_widen_constant (lhs)); | ||
1320 | + gimple_cond_set_rhs (stmt, tw_widen_variable (rhs)); | ||
1321 | + } | ||
1322 | + else if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs)) | ||
1323 | + { | ||
1324 | + gimple_cond_set_lhs (stmt, tw_widen_variable (lhs)); | ||
1325 | + gimple_cond_set_rhs (stmt, tw_widen_variable (rhs)); | ||
1326 | + } | ||
1327 | + } | ||
1328 | + else | ||
1329 | + { | ||
1330 | + TWDBG_MSG ("Validating run.\n"); | ||
1331 | + if (tw_candidacy_valid (lhs) && tw_candidate_const (rhs)) | ||
1332 | + return iv; | ||
1333 | + if (tw_candidate_const (lhs) && tw_candidacy_valid (rhs)) | ||
1334 | + return iv; | ||
1335 | + if (tw_candidacy_valid (lhs) && tw_candidacy_valid (rhs)) | ||
1336 | + return iv; | ||
1337 | + if (tw_candidacy_valid (lhs)) | ||
1338 | + { | ||
1339 | + tw_candidacy (lhs, 0); | ||
1340 | + iv++; | ||
1341 | + } | ||
1342 | + if (tw_candidacy_valid (rhs)) | ||
1343 | + { | ||
1344 | + tw_candidacy (rhs, 0); | ||
1345 | + iv++; | ||
1346 | + } | ||
1347 | + } | ||
1348 | + return iv; | ||
1349 | +} | ||
1350 | + | ||
1351 | +static long | ||
1352 | +tw_gimple_switch (gimple stmt, long widen) | ||
1353 | +{ | ||
1354 | + tree index = gimple_switch_index (stmt); | ||
1355 | + long iv = 0; | ||
1356 | + | ||
1357 | + TWDBG_STMT(stmt); | ||
1358 | + TWDBG_TREE(index); | ||
1359 | + | ||
1360 | + if (widen && tw_candidacy_valid (index)) | ||
1361 | + { | ||
1362 | + TWDBG_MSG ("Widening run.\n"); | ||
1363 | + gimple_switch_set_index (stmt, tw_widen_variable (index)); | ||
1364 | + return iv; | ||
1365 | + } | ||
1366 | + | ||
1367 | + TWDBG_MSG ("Validating run.\n"); | ||
1368 | + return iv; | ||
1369 | +} | ||
1370 | + | ||
1371 | +static long | ||
1372 | +tw_gimple_return (gimple stmt, long widen) | ||
1373 | +{ | ||
1374 | + tree op = gimple_return_retval (stmt); | ||
1375 | + long iv = 0; | ||
1376 | + | ||
1377 | + TWDBG_STMT(stmt); | ||
1378 | + TWDBG_TREE(op); | ||
1379 | + | ||
1380 | + if (widen) | ||
1381 | + { | ||
1382 | + TWDBG_MSG ("Widening run.\n"); | ||
1383 | + return iv; | ||
1384 | + } | ||
1385 | + | ||
1386 | + TWDBG_MSG ("Validating run.\n"); | ||
1387 | + if (tw_candidacy_valid (op)) | ||
1388 | + { | ||
1389 | + tw_candidacy (op, 0); | ||
1390 | + iv++; | ||
1391 | + } | ||
1392 | + return iv; | ||
1393 | +} | ||
1394 | + | ||
1395 | +static long | ||
1396 | +tw_gimple_asm (gimple stmt, long widen) | ||
1397 | +{ | ||
1398 | + long iv = 0; | ||
1399 | + unsigned int ninputs = gimple_asm_ninputs (stmt); | ||
1400 | + unsigned int noutputs = gimple_asm_noutputs (stmt); | ||
1401 | + unsigned int nclobbers = gimple_asm_nclobbers (stmt); | ||
1402 | + unsigned int i; | ||
1403 | + | ||
1404 | + TWDBG_STMT(stmt); | ||
1405 | + TWDBG_MSG("Inputs:\n"); | ||
1406 | + for (i = 0; i < ninputs; i++) | ||
1407 | + { | ||
1408 | + TWDBG_MSG1 ("input %d\n", i); | ||
1409 | + TWDBG_TREE (gimple_asm_input_op (stmt, i)); | ||
1410 | + } | ||
1411 | + TWDBG_MSG("Outputs:\n"); | ||
1412 | + for (i = 0; i < noutputs; i++) | ||
1413 | + { | ||
1414 | + TWDBG_MSG1 ("output %d\n", i); | ||
1415 | + TWDBG_TREE (gimple_asm_output_op (stmt, i)); | ||
1416 | + } | ||
1417 | + TWDBG_MSG("Clobbers:\n"); | ||
1418 | + for (i = 0; i < nclobbers; i++) | ||
1419 | + { | ||
1420 | + TWDBG_MSG1 ("clobber %d\n", i); | ||
1421 | + TWDBG_TREE (gimple_asm_clobber_op (stmt, i)); | ||
1422 | + } | ||
1423 | + if (widen) | ||
1424 | + { | ||
1425 | + TWDBG_MSG ("Widening run.\n"); | ||
1426 | + return iv; | ||
1427 | + } | ||
1428 | + TWDBG_MSG ("Validating run.\n"); | ||
1429 | + for (i = 0; i < ninputs; i++) | ||
1430 | + { | ||
1431 | + if (tw_candidacy_valid (gimple_asm_input_op (stmt, i))) | ||
1432 | + { | ||
1433 | + tw_candidacy (gimple_asm_input_op (stmt, i), 0); | ||
1434 | + iv++; | ||
1435 | + } | ||
1436 | + } | ||
1437 | + for (i = 0; i < noutputs; i++) | ||
1438 | + { | ||
1439 | + if (tw_candidacy_valid (gimple_asm_output_op (stmt, i))) | ||
1440 | + { | ||
1441 | + tw_candidacy (gimple_asm_output_op (stmt, i), 0); | ||
1442 | + iv++; | ||
1443 | + } | ||
1444 | + } | ||
1445 | + for (i = 0; i < nclobbers; i++) | ||
1446 | + { | ||
1447 | + if (tw_candidacy_valid (gimple_asm_clobber_op (stmt, i))) | ||
1448 | + { | ||
1449 | + tw_candidacy (gimple_asm_clobber_op (stmt, i), 0); | ||
1450 | + iv++; | ||
1451 | + } | ||
1452 | + } | ||
1453 | + return iv; | ||
1454 | +} | ||
1455 | + | ||
1456 | +static long | ||
1457 | +tw_gimple_debug (gimple stmt, long widen) | ||
1458 | +{ | ||
1459 | + long iv = 0; | ||
1460 | + tree var, value; | ||
1461 | + | ||
1462 | + var = gimple_debug_bind_get_var (stmt); | ||
1463 | + value = gimple_debug_bind_get_value (stmt); | ||
1464 | + | ||
1465 | + TWDBG_STMT(stmt); | ||
1466 | + TWDBG_TREE(var); | ||
1467 | + TWDBG_TREE(value); | ||
1468 | + | ||
1469 | + /* TODO: What if the value is a constant? */ | ||
1470 | + | ||
1471 | + if (widen) | ||
1472 | + { | ||
1473 | + TWDBG_MSG ("Widening run.\n"); | ||
1474 | + if (tw_candidacy_valid (var) && tw_candidacy_valid (value)) | ||
1475 | + { | ||
1476 | + gimple_debug_bind_set_var (stmt, tw_widen_variable (var)); | ||
1477 | + gimple_debug_bind_set_value (stmt, tw_widen_variable (value)); | ||
1478 | + } | ||
1479 | + else if (tw_candidacy_valid (var) && tw_candidate_const (value)) | ||
1480 | + { | ||
1481 | + gimple_debug_bind_set_var (stmt, tw_widen_variable (var)); | ||
1482 | + gimple_debug_bind_set_value (stmt, tw_widen_constant (value)); | ||
1483 | + } | ||
1484 | + } | ||
1485 | + else | ||
1486 | + { | ||
1487 | + TWDBG_MSG ("Validating run.\n"); | ||
1488 | + | ||
1489 | + if (var && !tw_in_candidate_list (var) && tw_candidate (var)) | ||
1490 | + tw_log_candidate (var); | ||
1491 | + if (value && !tw_in_candidate_list (value) && tw_candidate (value)) | ||
1492 | + tw_log_candidate (value); | ||
1493 | + if (tw_candidacy_valid (var) && tw_candidacy_valid (value)) | ||
1494 | + return iv; | ||
1495 | + if (tw_candidacy_valid (var)) | ||
1496 | + { | ||
1497 | + tw_candidacy (var, 0); | ||
1498 | + iv++; | ||
1499 | + } | ||
1500 | + if (tw_candidacy_valid (value)) | ||
1501 | + { | ||
1502 | + tw_candidacy (value, 0); | ||
1503 | + iv++; | ||
1504 | + } | ||
1505 | + } | ||
1506 | + | ||
1507 | + return iv; | ||
1508 | +} | ||
1509 | + | ||
1510 | +/* Notes: | ||
1511 | + * ------ | ||
1512 | + * | ||
1513 | + * Limitations to be documented: | ||
1514 | + * 0. -g -fopenmp not supported. | ||
1515 | + * | ||
1516 | + * Known DejaGNU failures: | ||
1517 | + * 0. FAIL: gcc.dg/pr38245-2.c scan-tree-dump-not optimized "link_error" | ||
1518 | + * This failure is because the optimization is dependent on the type of the variable; | ||
1519 | + * once the type of the variable has changed from int to long, the inequalities in | ||
1520 | + * this test case no longer hold and the code cannot be optimized anymore, consequently, | ||
1521 | + * the test fails. | ||
1522 | + * | ||
1523 | + * DejaGNU failures that are not due to type-widening: | ||
1524 | + * 0. gcc.dg/vect/vect-120.c scan-tree-dump-times vect "vectorized 1 loops" 1 | ||
1525 | + * 1.gcc.dg/vect/vect-120.c -flto scan-tree-dump-times vect "vectorized 1 loops" 1 | ||
1526 | + * | ||
1527 | + * DejaGNU PASS'es with -fwiden-types (but FAIL's in the baseline - the baseline needs | ||
1528 | + * to be fixed - it just so happens that the debug information happens to be better in | ||
1529 | + * the type-converted case. We have verified that the generated assembly is the same in | ||
1530 | + * either case (or has extsw eliminated)): | ||
1531 | + * gcc.dg/guality/pr45882.c | ||
1532 | + * gcc.dg/guality/pr43177.c | ||
1533 | + * | ||
1534 | + */ | ||
diff --git a/recipes-devtools/gcc/files/optional_libstdc.patch b/recipes-devtools/gcc/files/optional_libstdc.patch new file mode 100644 index 0000000..fe157a8 --- /dev/null +++ b/recipes-devtools/gcc/files/optional_libstdc.patch | |||
@@ -0,0 +1,86 @@ | |||
1 | Upstream-Status: Inappropriate [embedded specific] | ||
2 | |||
3 | gcc-runtime builds libstdc++ separately from gcc-cross-*. Its configure tests using g++ | ||
4 | will not run correctly since by default the linker will try to link against libstdc++ | ||
5 | which shouldn't exist yet. We need an option to disable -lstdc++ | ||
6 | option whilst leaving -lc, -lgcc and other automatic library dependencies added by gcc | ||
7 | driver. This patch adds such an option which only disables the -lstdc++. | ||
8 | |||
9 | A "standard" gcc build uses xgcc and hence avoids this. We should ask upstream how to | ||
10 | do this officially, the likely answer is don't build libstdc++ separately. | ||
11 | |||
12 | RP 29/6/10 | ||
13 | |||
14 | Index: gcc-4.6.0/gcc/cp/g++spec.c | ||
15 | =================================================================== | ||
16 | --- gcc-4.6.0.orig/gcc/cp/g++spec.c | ||
17 | +++ gcc-4.6.0/gcc/cp/g++spec.c | ||
18 | @@ -127,6 +127,7 @@ lang_specific_driver (struct cl_decoded_ | ||
19 | switch (decoded_options[i].opt_index) | ||
20 | { | ||
21 | case OPT_nostdlib: | ||
22 | + case OPT_nostdlib__: | ||
23 | case OPT_nodefaultlibs: | ||
24 | library = -1; | ||
25 | break; | ||
26 | Index: gcc-4.6.0/gcc/doc/invoke.texi | ||
27 | =================================================================== | ||
28 | --- gcc-4.6.0.orig/gcc/doc/invoke.texi | ||
29 | +++ gcc-4.6.0/gcc/doc/invoke.texi | ||
30 | @@ -193,7 +193,7 @@ in the following sections. | ||
31 | -fno-pretty-templates @gol | ||
32 | -frepo -fno-rtti -fstats -ftemplate-depth=@var{n} @gol | ||
33 | -fno-threadsafe-statics -fuse-cxa-atexit -fno-weak -nostdinc++ @gol | ||
34 | --fno-default-inline -fvisibility-inlines-hidden @gol | ||
35 | +-nostdlib++ -fno-default-inline -fvisibility-inlines-hidden @gol | ||
36 | -fvisibility-ms-compat @gol | ||
37 | -Wabi -Wconversion-null -Wctor-dtor-privacy @gol | ||
38 | -Wnoexcept -Wnon-virtual-dtor -Wreorder @gol | ||
39 | @@ -431,7 +431,7 @@ Objective-C and Objective-C++ Dialects}. | ||
40 | @gccoptlist{@var{object-file-name} -l@var{library} @gol | ||
41 | -nostartfiles -nodefaultlibs -nostdlib -pie -rdynamic @gol | ||
42 | -s -static -static-libgcc -static-libstdc++ -shared @gol | ||
43 | --shared-libgcc -symbolic @gol | ||
44 | +-shared-libgcc -symbolic -nostdlib++ @gol | ||
45 | -T @var{script} -Wl,@var{option} -Xlinker @var{option} @gol | ||
46 | -u @var{symbol}} | ||
47 | |||
48 | @@ -9069,6 +9069,11 @@ These entries are usually resolved by en | ||
49 | libc. These entry points should be supplied through some other | ||
50 | mechanism when this option is specified. | ||
51 | |||
52 | +@item -nostdlib++ | ||
53 | +@opindex nostdlib++ | ||
54 | +Do not use the standard system C++ runtime libraries when linking. | ||
55 | +Only the libraries you specify will be passed to the linker. | ||
56 | + | ||
57 | @cindex @option{-lgcc}, use with @option{-nostdlib} | ||
58 | @cindex @option{-nostdlib} and unresolved references | ||
59 | @cindex unresolved references and @option{-nostdlib} | ||
60 | Index: gcc-4.6.0/gcc/c-family/c.opt | ||
61 | =================================================================== | ||
62 | --- gcc-4.6.0.orig/gcc/c-family/c.opt | ||
63 | +++ gcc-4.6.0/gcc/c-family/c.opt | ||
64 | @@ -1111,6 +1111,10 @@ nostdinc++ | ||
65 | C++ ObjC++ | ||
66 | Do not search standard system include directories for C++ | ||
67 | |||
68 | +nostdlib++ | ||
69 | +Driver | ||
70 | +Do not link standard C++ runtime library | ||
71 | + | ||
72 | o | ||
73 | C ObjC C++ ObjC++ Joined Separate | ||
74 | ; Documented in common.opt | ||
75 | Index: gcc-4.6.0/gcc/gcc.c | ||
76 | =================================================================== | ||
77 | --- gcc-4.6.0.orig/gcc/gcc.c | ||
78 | +++ gcc-4.6.0/gcc/gcc.c | ||
79 | @@ -666,6 +666,7 @@ proper position among the other output f | ||
80 | %(mflib) " STACK_SPLIT_SPEC "\ | ||
81 | %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\ | ||
82 | %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}}\ | ||
83 | + %{!nostdlib++:}\ | ||
84 | %{!nostdlib:%{!nostartfiles:%E}} %{T*} }}}}}}" | ||
85 | #endif | ||
86 | |||
diff --git a/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend b/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend b/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend b/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/gcc-cross_4.6.bbappend b/recipes-devtools/gcc/gcc-cross_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc-cross_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend b/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend b/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend new file mode 100644 index 0000000..ed27db0 --- /dev/null +++ b/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend | |||
@@ -0,0 +1,22 @@ | |||
1 | require gcc-fsl.inc | ||
2 | |||
3 | do_install () { | ||
4 | oe_runmake 'DESTDIR=${D}' install | ||
5 | install -d ${D}${target_base_libdir}/ | ||
6 | cp -rf ${D}${exec_prefix}/${TARGET_SYS}/${baselib}/ ${D}${target_base_libdir}/ | ||
7 | |||
8 | # We don't really need this (here shares/ contains man/, info/, locale/). | ||
9 | rm -rf ${D}${datadir}/ | ||
10 | |||
11 | # We use libiberty from binutils | ||
12 | find ${D}${exec_prefix}/lib -name libiberty.a | xargs rm -f | ||
13 | find ${D}${exec_prefix}/lib -name libiberty.h | xargs rm -f | ||
14 | |||
15 | # Insert symlinks into libexec so when tools without a prefix are searched for, the correct ones are | ||
16 | # found. These need to be relative paths so they work in different locations. | ||
17 | dest=${D}${libexecdir}/gcc/${TARGET_SYS}/${BINV}/ | ||
18 | install -d $dest | ||
19 | for t in ar as ld nm objcopy objdump ranlib strip g77 gcc cpp gfortran; do | ||
20 | ln -sf ${BINRELPATH}/${TARGET_PREFIX}$t $dest$t | ||
21 | done | ||
22 | } | ||
diff --git a/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend b/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/gcc-fsl.inc b/recipes-devtools/gcc/gcc-fsl.inc new file mode 100644 index 0000000..83d519c --- /dev/null +++ b/recipes-devtools/gcc/gcc-fsl.inc | |||
@@ -0,0 +1,44 @@ | |||
1 | #LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \ | ||
2 | # file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \ | ||
3 | # file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \ | ||
4 | # file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \ | ||
5 | # file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8" | ||
6 | |||
7 | BINV = "4.6.2" | ||
8 | |||
9 | SRCREV = "180516" | ||
10 | # ignore linaro backports since we are changing the SRCREV | ||
11 | GCC-4_6-BRANCH-LINARO-BACKPORTS = "" | ||
12 | |||
13 | SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \ | ||
14 | file://gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \ | ||
15 | file://gcc.fix_longversionstring.patch \ | ||
16 | file://gcc.rm_slow_tests.patch \ | ||
17 | file://gcc.fix_mingw32.patch \ | ||
18 | file://gcc.fix_cloogstatic2.patch \ | ||
19 | file://gcc.fix_build-with-cxx.patch \ | ||
20 | file://gcc.e6500-FSF46.patch \ | ||
21 | file://gcc.ld_unaligned-460.patch \ | ||
22 | file://gcc.local_unaligned_altivec.patch \ | ||
23 | file://gcc.soft_float-460.patch \ | ||
24 | file://gcc.case_values.patch \ | ||
25 | file://gcc.builtin_isel.patch \ | ||
26 | file://gcc.experimental_move.patch \ | ||
27 | file://gcc.widen_types-46.patch \ | ||
28 | file://gcc.extelim-v3.patch \ | ||
29 | file://gcc.e5500_mfocr.patch \ | ||
30 | file://gcc.opt-array-offset.patch \ | ||
31 | file://gcc.load_on_store_bypass-462.patch \ | ||
32 | file://gcc.fix_constvector.patch \ | ||
33 | file://gcc.fix_MTWX51204-dwarf-vector-reg.patch \ | ||
34 | file://gcc.fix_ira-loop-pressure.patch \ | ||
35 | file://optional_libstdc.patch \ | ||
36 | file://gcc.remove_CCUNSmode_reference.patch \ | ||
37 | file://gcc.check_path_validity.patch \ | ||
38 | file://gcc.fix_header_issue.patch \ | ||
39 | file://gcc.fix_SSIZE_MAX_undefine_issue.patch \ | ||
40 | " | ||
41 | |||
42 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:" | ||
43 | |||
44 | PR .= "+${DISTRO}.0" | ||
diff --git a/recipes-devtools/gcc/gcc-runtime_4.6.bbappend b/recipes-devtools/gcc/gcc-runtime_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc-runtime_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/gcc_4.6.bbappend b/recipes-devtools/gcc/gcc_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/gcc_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||
diff --git a/recipes-devtools/gcc/libgcc_4.6.bbappend b/recipes-devtools/gcc/libgcc_4.6.bbappend new file mode 100644 index 0000000..1c725f2 --- /dev/null +++ b/recipes-devtools/gcc/libgcc_4.6.bbappend | |||
@@ -0,0 +1 @@ | |||
require gcc-fsl.inc | |||