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Diffstat (limited to 'recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch')
-rw-r--r--recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch162
1 files changed, 0 insertions, 162 deletions
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch
deleted file mode 100644
index 8da6d97..0000000
--- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch
+++ /dev/null
@@ -1,162 +0,0 @@
1From 2e5adad8385127605c3ad3e3a006d65deeccde38 Mon Sep 17 00:00:00 2001
2From: Marek Vasut <marek.vasut@gmail.com>
3Date: Tue, 1 May 2012 11:09:51 +0000
4Subject: [PATCH 53/56] i.MX28: Add battery boot components to SPL
5
6Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
7Cc: Detlev Zundel <dzu@denx.de>
8Cc: Fabio Estevam <fabio.estevam@freescale.com>
9Cc: Stefano Babic <sbabic@denx.de>
10Cc: Wolfgang Denk <wd@denx.de>
11---
12 arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 100 +++++++++++++++++++++++---
13 1 file changed, 92 insertions(+), 8 deletions(-)
14
15diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
16index ac942b4..4b09b0c 100644
17--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
18+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
19@@ -45,11 +45,11 @@ void mx28_power_clock2pll(void)
20 struct mx28_clkctrl_regs *clkctrl_regs =
21 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
22
23- writel(CLKCTRL_PLL0CTRL0_POWER,
24- &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
25+ setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
26+ CLKCTRL_PLL0CTRL0_POWER);
27 early_delay(100);
28- writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
29- &clkctrl_regs->hw_clkctrl_clkseq_clr);
30+ setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
31+ CLKCTRL_CLKSEQ_BYPASS_CPU);
32 }
33
34 void mx28_power_clear_auto_restart(void)
35@@ -455,9 +455,14 @@ void mx28_power_enable_4p2(void)
36 mx28_power_init_4p2_regulator();
37
38 /* Shutdown battery (none present) */
39- clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
40- writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
41- writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
42+ if (!mx28_is_batt_ready()) {
43+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
44+ POWER_DCDC4P2_BO_MASK);
45+ writel(POWER_CTRL_DCDC4P2_BO_IRQ,
46+ &power_regs->hw_power_ctrl_clr);
47+ writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
48+ &power_regs->hw_power_ctrl_clr);
49+ }
50
51 mx28_power_init_dcdc_4p2_source();
52
53@@ -515,6 +520,50 @@ void mx28_powerdown(void)
54 &power_regs->hw_power_reset);
55 }
56
57+void mx28_batt_boot(void)
58+{
59+ struct mx28_power_regs *power_regs =
60+ (struct mx28_power_regs *)MXS_POWER_BASE;
61+
62+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
63+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
64+
65+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
66+ POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
67+ writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
68+
69+ /* 5V to battery handoff. */
70+ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
71+ early_delay(30);
72+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
73+
74+ writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
75+
76+ clrsetbits_le32(&power_regs->hw_power_minpwr,
77+ POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
78+
79+ mx28_power_set_linreg();
80+
81+ clrbits_le32(&power_regs->hw_power_vdddctrl,
82+ POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
83+
84+ clrbits_le32(&power_regs->hw_power_vddactrl,
85+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
86+
87+ clrbits_le32(&power_regs->hw_power_vddioctrl,
88+ POWER_VDDIOCTRL_DISABLE_FET);
89+
90+ setbits_le32(&power_regs->hw_power_5vctrl,
91+ POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
92+
93+ setbits_le32(&power_regs->hw_power_5vctrl,
94+ POWER_5VCTRL_ENABLE_DCDC);
95+
96+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
97+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
98+ 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
99+}
100+
101 void mx28_handle_5v_conflict(void)
102 {
103 struct mx28_power_regs *power_regs =
104@@ -539,6 +588,11 @@ void mx28_handle_5v_conflict(void)
105 mx28_powerdown();
106 break;
107 }
108+
109+ if (tmp & POWER_STS_PSWITCH_MASK) {
110+ mx28_batt_boot();
111+ break;
112+ }
113 }
114 }
115
116@@ -595,12 +649,42 @@ void mx28_switch_vddd_to_dcdc_source(void)
117
118 void mx28_power_configure_power_source(void)
119 {
120+ int batt_ready, batt_good;
121+ struct mx28_power_regs *power_regs =
122+ (struct mx28_power_regs *)MXS_POWER_BASE;
123+ struct mx28_lradc_regs *lradc_regs =
124+ (struct mx28_lradc_regs *)MXS_LRADC_BASE;
125+
126 mx28_src_power_init();
127
128- mx28_5v_boot();
129+ batt_ready = mx28_is_batt_ready();
130+
131+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
132+ batt_good = mx28_is_batt_good();
133+ if (batt_ready) {
134+ /* 5V source detected, good battery detected. */
135+ mx28_batt_boot();
136+ } else {
137+ if (batt_good) {
138+ /* 5V source detected, low battery detceted. */
139+ } else {
140+ /* 5V source detected, bad battery detected. */
141+ writel(LRADC_CONVERSION_AUTOMATIC,
142+ &lradc_regs->hw_lradc_conversion_clr);
143+ clrbits_le32(&power_regs->hw_power_battmonitor,
144+ POWER_BATTMONITOR_BATT_VAL_MASK);
145+ }
146+ mx28_5v_boot();
147+ }
148+ } else {
149+ /* 5V not detected, booting from battery. */
150+ mx28_batt_boot();
151+ }
152+
153 mx28_power_clock2pll();
154
155 mx28_init_batt_bo();
156+
157 mx28_switch_vddd_to_dcdc_source();
158 }
159
160--
1611.7.10
162