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-rw-r--r--recipes-bsp/u-boot/u-boot-v2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch437
1 files changed, 0 insertions, 437 deletions
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch
deleted file mode 100644
index 0717e16..0000000
--- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch
+++ /dev/null
@@ -1,437 +0,0 @@
1From dfc17c49a75e682b9ef56985bdb5793863019f6b Mon Sep 17 00:00:00 2001
2From: Marek Vasut <marek.vasut@gmail.com>
3Date: Tue, 1 May 2012 11:09:48 +0000
4Subject: [PATCH 50/56] i.MX28: Add LRADC register definitions
5
6Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
7Cc: Detlev Zundel <dzu@denx.de>
8Cc: Fabio Estevam <fabio.estevam@freescale.com>
9Cc: Stefano Babic <sbabic@denx.de>
10Cc: Wolfgang Denk <wd@denx.de>
11---
12 arch/arm/include/asm/arch-mx28/imx-regs.h | 1 +
13 arch/arm/include/asm/arch-mx28/regs-lradc.h | 400 +++++++++++++++++++++++++++
14 2 files changed, 401 insertions(+)
15 create mode 100644 arch/arm/include/asm/arch-mx28/regs-lradc.h
16
17diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h
18index 581bf0a..37d0a93 100644
19--- a/arch/arm/include/asm/arch-mx28/imx-regs.h
20+++ b/arch/arm/include/asm/arch-mx28/imx-regs.h
21@@ -31,6 +31,7 @@
22 #include <asm/arch/regs-gpmi.h>
23 #include <asm/arch/regs-i2c.h>
24 #include <asm/arch/regs-lcdif.h>
25+#include <asm/arch/regs-lradc.h>
26 #include <asm/arch/regs-ocotp.h>
27 #include <asm/arch/regs-pinctrl.h>
28 #include <asm/arch/regs-power.h>
29diff --git a/arch/arm/include/asm/arch-mx28/regs-lradc.h b/arch/arm/include/asm/arch-mx28/regs-lradc.h
30new file mode 100644
31index 0000000..16e2bbf
32--- /dev/null
33+++ b/arch/arm/include/asm/arch-mx28/regs-lradc.h
34@@ -0,0 +1,400 @@
35+/*
36+ * Freescale i.MX28 LRADC Register Definitions
37+ *
38+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
39+ * on behalf of DENX Software Engineering GmbH
40+ *
41+ * Based on code from LTIB:
42+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
43+ *
44+ * This program is free software; you can redistribute it and/or modify
45+ * it under the terms of the GNU General Public License as published by
46+ * the Free Software Foundation; either version 2 of the License, or
47+ * (at your option) any later version.
48+ *
49+ * This program is distributed in the hope that it will be useful,
50+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
51+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
52+ * GNU General Public License for more details.
53+ *
54+ * You should have received a copy of the GNU General Public License
55+ * along with this program; if not, write to the Free Software
56+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
57+ *
58+ */
59+
60+#ifndef __MX28_REGS_LRADC_H__
61+#define __MX28_REGS_LRADC_H__
62+
63+#include <asm/arch/regs-common.h>
64+
65+#ifndef __ASSEMBLY__
66+struct mx28_lradc_regs {
67+ mx28_reg_32(hw_lradc_ctrl0);
68+ mx28_reg_32(hw_lradc_ctrl1);
69+ mx28_reg_32(hw_lradc_ctrl2);
70+ mx28_reg_32(hw_lradc_ctrl3);
71+ mx28_reg_32(hw_lradc_status);
72+ mx28_reg_32(hw_lradc_ch0);
73+ mx28_reg_32(hw_lradc_ch1);
74+ mx28_reg_32(hw_lradc_ch2);
75+ mx28_reg_32(hw_lradc_ch3);
76+ mx28_reg_32(hw_lradc_ch4);
77+ mx28_reg_32(hw_lradc_ch5);
78+ mx28_reg_32(hw_lradc_ch6);
79+ mx28_reg_32(hw_lradc_ch7);
80+ mx28_reg_32(hw_lradc_delay0);
81+ mx28_reg_32(hw_lradc_delay1);
82+ mx28_reg_32(hw_lradc_delay2);
83+ mx28_reg_32(hw_lradc_delay3);
84+ mx28_reg_32(hw_lradc_debug0);
85+ mx28_reg_32(hw_lradc_debug1);
86+ mx28_reg_32(hw_lradc_conversion);
87+ mx28_reg_32(hw_lradc_ctrl4);
88+ mx28_reg_32(hw_lradc_treshold0);
89+ mx28_reg_32(hw_lradc_treshold1);
90+ mx28_reg_32(hw_lradc_version);
91+};
92+#endif
93+
94+#define LRADC_CTRL0_SFTRST (1 << 31)
95+#define LRADC_CTRL0_CLKGATE (1 << 30)
96+#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26)
97+#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25)
98+#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24)
99+#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
100+#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
101+#define LRADC_CTRL0_YNLRSW (1 << 21)
102+#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19)
103+#define LRADC_CTRL0_YPLLSW_OFFSET 19
104+#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17)
105+#define LRADC_CTRL0_XNURSW_OFFSET 17
106+#define LRADC_CTRL0_XPULSW (1 << 16)
107+#define LRADC_CTRL0_SCHEDULE_MASK 0xff
108+#define LRADC_CTRL0_SCHEDULE_OFFSET 0
109+
110+#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28)
111+#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27)
112+#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26)
113+#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25)
114+#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24)
115+#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23)
116+#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22)
117+#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21)
118+#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20)
119+#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19)
120+#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18)
121+#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17)
122+#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16)
123+#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12)
124+#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11)
125+#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10)
126+#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9)
127+#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
128+#define LRADC_CTRL1_LRADC7_IRQ (1 << 7)
129+#define LRADC_CTRL1_LRADC6_IRQ (1 << 6)
130+#define LRADC_CTRL1_LRADC5_IRQ (1 << 5)
131+#define LRADC_CTRL1_LRADC4_IRQ (1 << 4)
132+#define LRADC_CTRL1_LRADC3_IRQ (1 << 3)
133+#define LRADC_CTRL1_LRADC2_IRQ (1 << 2)
134+#define LRADC_CTRL1_LRADC1_IRQ (1 << 1)
135+#define LRADC_CTRL1_LRADC0_IRQ (1 << 0)
136+
137+#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24)
138+#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
139+#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
140+#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13)
141+#define LRADC_CTRL2_VTHSENSE_OFFSET 13
142+#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12)
143+#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9)
144+#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8)
145+#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4)
146+#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4
147+#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4)
148+#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4)
149+#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4)
150+#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4)
151+#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4)
152+#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4)
153+#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4)
154+#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4)
155+#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4)
156+#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4)
157+#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4)
158+#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4)
159+#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4)
160+#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4)
161+#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4)
162+#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4)
163+#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0)
164+#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0
165+#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0)
166+#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0)
167+#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0)
168+#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0)
169+#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0)
170+#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0)
171+#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0)
172+#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0)
173+#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0)
174+#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0)
175+#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0)
176+#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0)
177+#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0)
178+#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0)
179+#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0)
180+#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0)
181+
182+#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24)
183+#define LRADC_CTRL3_DISCARD_OFFSET 24
184+#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24)
185+#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24)
186+#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24)
187+#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23)
188+#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22)
189+#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8)
190+#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8
191+#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8)
192+#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8)
193+#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8)
194+#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8)
195+#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4)
196+#define LRADC_CTRL3_HIGH_TIME_OFFSET 4
197+#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4)
198+#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4)
199+#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4)
200+#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4)
201+#define LRADC_CTRL3_DELAY_CLOCK (1 << 1)
202+#define LRADC_CTRL3_INVERT_CLOCK (1 << 0)
203+
204+#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28)
205+#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27)
206+#define LRADC_STATUS_TEMP1_PRESENT (1 << 26)
207+#define LRADC_STATUS_TEMP0_PRESENT (1 << 25)
208+#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24)
209+#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23)
210+#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22)
211+#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21)
212+#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20)
213+#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19)
214+#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18)
215+#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17)
216+#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16)
217+#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2)
218+#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1)
219+#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0)
220+
221+#define LRADC_CH_TOGGLE (1 << 31)
222+#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30)
223+#define LRADC_CH_ACCUMULATE (1 << 29)
224+#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
225+#define LRADC_CH_NUM_SAMPLES_OFFSET 24
226+#define LRADC_CH_VALUE_MASK 0x3ffff
227+#define LRADC_CH_VALUE_OFFSET 0
228+
229+#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
230+#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
231+#define LRADC_DELAY_KICK (1 << 20)
232+#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
233+#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
234+#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
235+#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
236+#define LRADC_DELAY_DELAY_MASK 0x7ff
237+#define LRADC_DELAY_DELAY_OFFSET 0
238+
239+#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16)
240+#define LRADC_DEBUG0_READONLY_OFFSET 16
241+#define LRADC_DEBUG0_STATE_MASK (0xfff << 0)
242+#define LRADC_DEBUG0_STATE_OFFSET 0
243+
244+#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16)
245+#define LRADC_DEBUG1_REQUEST_OFFSET 16
246+#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8)
247+#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8
248+#define LRADC_DEBUG1_TESTMODE6 (1 << 2)
249+#define LRADC_DEBUG1_TESTMODE5 (1 << 1)
250+#define LRADC_DEBUG1_TESTMODE (1 << 0)
251+
252+#define LRADC_CONVERSION_AUTOMATIC (1 << 20)
253+#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16)
254+#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16
255+#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16)
256+#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16)
257+#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16)
258+#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16)
259+#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff
260+#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0
261+
262+#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28)
263+#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28
264+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28)
265+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28)
266+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28)
267+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28)
268+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28)
269+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28)
270+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28)
271+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28)
272+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28)
273+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28)
274+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28)
275+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28)
276+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28)
277+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28)
278+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28)
279+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28)
280+#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24)
281+#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24
282+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24)
283+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24)
284+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24)
285+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24)
286+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24)
287+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24)
288+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24)
289+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24)
290+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24)
291+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24)
292+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24)
293+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24)
294+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24)
295+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24)
296+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24)
297+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24)
298+#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20)
299+#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20
300+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20)
301+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20)
302+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20)
303+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20)
304+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20)
305+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20)
306+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20)
307+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20)
308+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20)
309+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20)
310+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20)
311+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20)
312+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20)
313+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20)
314+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20)
315+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20)
316+#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16)
317+#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16
318+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16)
319+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16)
320+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16)
321+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16)
322+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16)
323+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16)
324+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16)
325+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16)
326+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16)
327+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16)
328+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16)
329+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16)
330+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16)
331+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16)
332+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16)
333+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16)
334+#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12)
335+#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12
336+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12)
337+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12)
338+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12)
339+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12)
340+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12)
341+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12)
342+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12)
343+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12)
344+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12)
345+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12)
346+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12)
347+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12)
348+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12)
349+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12)
350+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12)
351+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12)
352+#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8)
353+#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8
354+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8)
355+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8)
356+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8)
357+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8)
358+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8)
359+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8)
360+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8)
361+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8)
362+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8)
363+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8)
364+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8)
365+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8)
366+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8)
367+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8)
368+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8)
369+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8)
370+#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4)
371+#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4
372+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4)
373+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4)
374+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4)
375+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4)
376+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4)
377+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4)
378+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4)
379+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4)
380+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4)
381+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4)
382+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4)
383+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4)
384+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4)
385+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4)
386+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4)
387+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4)
388+#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf
389+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0)
390+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0)
391+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0)
392+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0)
393+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0)
394+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0)
395+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0)
396+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0)
397+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0)
398+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0)
399+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0)
400+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0)
401+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0)
402+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0)
403+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0)
404+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0)
405+
406+#define LRADC_THRESHOLD_ENABLE (1 << 24)
407+#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23)
408+#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20)
409+#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20
410+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20)
411+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20)
412+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20)
413+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20)
414+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20)
415+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20)
416+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20)
417+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20)
418+#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18)
419+#define LRADC_THRESHOLD_SETTING_OFFSET 18
420+#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18)
421+#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18)
422+#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18)
423+#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18)
424+#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff
425+#define LRADC_THRESHOLD_VALUE_OFFSET 0
426+
427+#define LRADC_VERSION_MAJOR_MASK (0xff << 24)
428+#define LRADC_VERSION_MAJOR_OFFSET 24
429+#define LRADC_VERSION_MINOR_MASK (0xff << 16)
430+#define LRADC_VERSION_MINOR_OFFSET 16
431+#define LRADC_VERSION_STEP_MASK 0xffff
432+#define LRADC_VERSION_STEP_OFFSET 0
433+
434+#endif /* __MX28_REGS_LRADC_H__ */
435--
4361.7.10
437
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-10-06 16:40:54 +0000