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authorOtavio Salvador <otavio@ossystems.com.br>2014-09-11 15:51:09 -0300
committerOtavio Salvador <otavio@ossystems.com.br>2014-09-15 11:16:53 -0300
commitb4c85efb85d80b387ed4497fbfd0fdb557f0785d (patch)
treeb6c62277c2c7f9e438afe64ef0cc6ca74722c2e0
parente9bf647e10ff1e31f911d3236dbb22a1ad7ace9f (diff)
downloadmeta-fsl-arm-b4c85efb85d80b387ed4497fbfd0fdb557f0785d.tar.gz
linux-imx (3.10.17): Forward port 3.10.17-1.0.0 fixes
Freescale when doing 3.10.17-1.0.1 has ignored the fixes done, by themselves, in the 3.10.17-1.0.0 kernel. This includes following patches, rebased on top 3.10.17-1.0.1: ENGR00318392 ARM:imx6x: Save/restore SCU and some CP15 registers across suspend/resume ENGR00301078-2: ARM: dts: imx6sl-evk: add support for pfuze200 on imx6sl-evk ENGR00301078-1: ARM: dts: imx6dl-sabresd: add support for pfuze200 on mx6dl-sabresd pfuze100-regulator: Fix of_node_get() parameter regulator: pfuze100: Use of_get_child_by_name regulator: pfuze100: Add PFUZE200 support to Kconfig and module description regulator: pfuze100: Add terminate entry for [i2c|of]_device_id tables regulator: pfuze100: add pfuze200 support regulator: pfuze100: Fix address of FABID ENGR00309838 ARM: imx6sl: gpc: add chip revision check for dispmix Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0001-ENGR00309838-ARM-imx6sl-gpc-add-chip-revision-check-.patch52
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0002-regulator-pfuze100-Fix-address-of-FABID.patch36
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0003-regulator-pfuze100-add-pfuze200-support.patch506
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0004-regulator-pfuze100-Add-terminate-entry-for-i2c-of-_d.patch61
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0005-regulator-pfuze100-Add-PFUZE200-support-to-Kconfig-a.patch56
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0006-regulator-pfuze100-Use-of_get_child_by_name.patch34
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0007-pfuze100-regulator-Fix-of_node_get-parameter.patch44
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0008-ENGR00301078-1-ARM-dts-imx6dl-sabresd-add-support-fo.patch752
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0009-ENGR00301078-2-ARM-dts-imx6sl-evk-add-support-for-pf.patch1202
-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0010-ENGR00318392-ARM-imx6x-Save-restore-SCU-and-some-CP1.patch133
-rw-r--r--recipes-kernel/linux/linux-imx_3.10.17.bb11
11 files changed, 2887 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0001-ENGR00309838-ARM-imx6sl-gpc-add-chip-revision-check-.patch b/recipes-kernel/linux/linux-imx-3.10.17/0001-ENGR00309838-ARM-imx6sl-gpc-add-chip-revision-check-.patch
new file mode 100644
index 0000000..962a804
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0001-ENGR00309838-ARM-imx6sl-gpc-add-chip-revision-check-.patch
@@ -0,0 +1,52 @@
1From 5dad39098c3c8686f23db638505bf00ae2cc092f Mon Sep 17 00:00:00 2001
2From: Robby Cai <r63905@freescale.com>
3Date: Fri, 23 May 2014 16:02:13 +0800
4Subject: [PATCH 01/10] ENGR00309838 ARM: imx6sl: gpc: add chip revision check
5 for dispmix
6Organization: O.S. Systems Software LTDA.
7
8The dispmix feature works without problem since TO1.2.
9This patch adds the back-compatibility for older chip.
10
11Signed-off-by: Robby Cai <r63905@freescale.com>
12(cherry picked from commit a187b916d55052fed10de1797009250095b598fb)
13
14Upstream-Status: Pending
15---
16 arch/arm/mach-imx/gpc.c | 8 +++++---
17 1 file changed, 5 insertions(+), 3 deletions(-)
18
19diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
20index 9734327..25e987c 100644
21--- a/arch/arm/mach-imx/gpc.c
22+++ b/arch/arm/mach-imx/gpc.c
23@@ -1,5 +1,5 @@
24 /*
25- * Copyright 2011-2013 Freescale Semiconductor, Inc.
26+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
27 * Copyright 2011 Linaro Ltd.
28 *
29 * The code contained herein is licensed under the GNU General Public
30@@ -90,7 +90,8 @@ static void imx_disp_clk(bool enable)
31
32 static void imx_gpc_dispmix_on(void)
33 {
34- if (cpu_is_imx6sl()) {
35+ if (cpu_is_imx6sl() &&
36+ imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) {
37 imx_disp_clk(true);
38
39 writel_relaxed(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
40@@ -105,7 +106,8 @@ static void imx_gpc_dispmix_on(void)
41
42 static void imx_gpc_dispmix_off(void)
43 {
44- if (cpu_is_imx6sl()) {
45+ if (cpu_is_imx6sl() &&
46+ imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) {
47 imx_disp_clk(true);
48
49 writel_relaxed(0xFFFFFFFF,
50--
512.1.0
52
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0002-regulator-pfuze100-Fix-address-of-FABID.patch b/recipes-kernel/linux/linux-imx-3.10.17/0002-regulator-pfuze100-Fix-address-of-FABID.patch
new file mode 100644
index 0000000..ff36488
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0002-regulator-pfuze100-Fix-address-of-FABID.patch
@@ -0,0 +1,36 @@
1From a38734076be8b4fbb1a9db757e1a69dddef61f63 Mon Sep 17 00:00:00 2001
2From: Axel Lin <axel.lin@ingics.com>
3Date: Mon, 9 Dec 2013 15:24:19 +0800
4Subject: [PATCH 02/10] regulator: pfuze100: Fix address of FABID
5Organization: O.S. Systems Software LTDA.
6
7According to the datasheet, the address of FABID is 0x4. Fix it.
8
9Signed-off-by: Axel Lin <axel.lin@ingics.com>
10Acked-by: Robin Gong <b38343@freescale.com>
11Signed-off-by: Mark Brown <broonie@linaro.org>
12Cc: stable@vger.kernel.org
13(cherry picked from commit c07a24939f36fb6de522a9726369ea64eee5d98d)
14(cherry picked from commit cfec286ff9f375c2c289072d63cedbb0c7917a48)
15
16Upstream-Status: Pending
17---
18 drivers/regulator/pfuze100-regulator.c | 2 +-
19 1 file changed, 1 insertion(+), 1 deletion(-)
20
21diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
22index ba67b2c..565a631 100644
23--- a/drivers/regulator/pfuze100-regulator.c
24+++ b/drivers/regulator/pfuze100-regulator.c
25@@ -38,7 +38,7 @@
26
27 #define PFUZE100_DEVICEID 0x0
28 #define PFUZE100_REVID 0x3
29-#define PFUZE100_FABID 0x3
30+#define PFUZE100_FABID 0x4
31
32 #define PFUZE100_SW1ABVOL 0x20
33 #define PFUZE100_SW1CVOL 0x2e
34--
352.1.0
36
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0003-regulator-pfuze100-add-pfuze200-support.patch b/recipes-kernel/linux/linux-imx-3.10.17/0003-regulator-pfuze100-add-pfuze200-support.patch
new file mode 100644
index 0000000..923da0a
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0003-regulator-pfuze100-add-pfuze200-support.patch
@@ -0,0 +1,506 @@
1From 08284f19c7cfdf84332c8098204f6e7fad368308 Mon Sep 17 00:00:00 2001
2From: Robin Gong <b38343@freescale.com>
3Date: Tue, 4 Mar 2014 17:40:36 +0800
4Subject: [PATCH 03/10] regulator: pfuze100: add pfuze200 support
5Organization: O.S. Systems Software LTDA.
6
7support pfuze200 chip which remove SW1C and SW4 based on pfuze100.
8
9Signed-off-by: Robin Gong <b38343@freescale.com>
10Signed-off-by: Mark Brown <broonie@linaro.org>
11(cherry picked from commit f2518480c7b744296a5587990a54e3a284d932b8)
12
13Conflicts:
14
15 drivers/regulator/pfuze100-regulator.c
16(cherry picked from commit f9e62732cfb59ff68fed303bbbb3913d2f1002bf)
17
18Upstream-Status: Pending
19---
20 .../devicetree/bindings/regulator/pfuze100.txt | 96 ++++++++++-
21 drivers/regulator/pfuze100-regulator.c | 181 ++++++++++++++++-----
22 include/linux/regulator/pfuze100.h | 14 ++
23 3 files changed, 245 insertions(+), 46 deletions(-)
24
25diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt
26index fc989b2..34ef5d1 100644
27--- a/Documentation/devicetree/bindings/regulator/pfuze100.txt
28+++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt
29@@ -1,7 +1,7 @@
30 PFUZE100 family of regulators
31
32 Required properties:
33-- compatible: "fsl,pfuze100"
34+- compatible: "fsl,pfuze100" or "fsl,pfuze200"
35 - reg: I2C slave address
36
37 Required child node:
38@@ -10,11 +10,14 @@ Required child node:
39 Documentation/devicetree/bindings/regulator/regulator.txt.
40
41 The valid names for regulators are:
42+ --PFUZE100
43 sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6
44+ --PFUZE200
45+ sw1ab,sw2,sw3a,sw3b,swbst,vsnvs,vrefddr,vgen1~vgen6
46
47 Each regulator is defined using the standard binding for regulators.
48
49-Example:
50+Example 1: PFUZE100
51
52 pmic: pfuze100@08 {
53 compatible = "fsl,pfuze100";
54@@ -113,3 +116,92 @@ Example:
55 };
56 };
57 };
58+
59+
60+Example 2: PFUZE200
61+
62+ pmic: pfuze200@08 {
63+ compatible = "fsl,pfuze200";
64+ reg = <0x08>;
65+
66+ regulators {
67+ sw1a_reg: sw1ab {
68+ regulator-min-microvolt = <300000>;
69+ regulator-max-microvolt = <1875000>;
70+ regulator-boot-on;
71+ regulator-always-on;
72+ regulator-ramp-delay = <6250>;
73+ };
74+
75+ sw2_reg: sw2 {
76+ regulator-min-microvolt = <800000>;
77+ regulator-max-microvolt = <3300000>;
78+ regulator-boot-on;
79+ regulator-always-on;
80+ };
81+
82+ sw3a_reg: sw3a {
83+ regulator-min-microvolt = <400000>;
84+ regulator-max-microvolt = <1975000>;
85+ regulator-boot-on;
86+ regulator-always-on;
87+ };
88+
89+ sw3b_reg: sw3b {
90+ regulator-min-microvolt = <400000>;
91+ regulator-max-microvolt = <1975000>;
92+ regulator-boot-on;
93+ regulator-always-on;
94+ };
95+
96+ swbst_reg: swbst {
97+ regulator-min-microvolt = <5000000>;
98+ regulator-max-microvolt = <5150000>;
99+ };
100+
101+ snvs_reg: vsnvs {
102+ regulator-min-microvolt = <1000000>;
103+ regulator-max-microvolt = <3000000>;
104+ regulator-boot-on;
105+ regulator-always-on;
106+ };
107+
108+ vref_reg: vrefddr {
109+ regulator-boot-on;
110+ regulator-always-on;
111+ };
112+
113+ vgen1_reg: vgen1 {
114+ regulator-min-microvolt = <800000>;
115+ regulator-max-microvolt = <1550000>;
116+ };
117+
118+ vgen2_reg: vgen2 {
119+ regulator-min-microvolt = <800000>;
120+ regulator-max-microvolt = <1550000>;
121+ };
122+
123+ vgen3_reg: vgen3 {
124+ regulator-min-microvolt = <1800000>;
125+ regulator-max-microvolt = <3300000>;
126+ };
127+
128+ vgen4_reg: vgen4 {
129+ regulator-min-microvolt = <1800000>;
130+ regulator-max-microvolt = <3300000>;
131+ regulator-always-on;
132+ };
133+
134+ vgen5_reg: vgen5 {
135+ regulator-min-microvolt = <1800000>;
136+ regulator-max-microvolt = <3300000>;
137+ regulator-always-on;
138+ };
139+
140+ vgen6_reg: vgen6 {
141+ regulator-min-microvolt = <1800000>;
142+ regulator-max-microvolt = <3300000>;
143+ regulator-always-on;
144+ };
145+ };
146+ };
147diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
148index 565a631..35b1de1 100644
149--- a/drivers/regulator/pfuze100-regulator.c
150+++ b/drivers/regulator/pfuze100-regulator.c
151@@ -56,6 +56,8 @@
152 #define PFUZE100_VGEN5VOL 0x70
153 #define PFUZE100_VGEN6VOL 0x71
154
155+enum chips {PFUZE100, PFUZE200, PFUZE_NUM};
156+
157 struct pfuze_regulator {
158 struct regulator_desc desc;
159 unsigned char stby_reg;
160@@ -63,6 +65,7 @@ struct pfuze_regulator {
161 };
162
163 struct pfuze_chip {
164+ int chip_id;
165 struct regmap *regmap;
166 struct device *dev;
167 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
168@@ -77,15 +80,15 @@ static const int pfuze100_vsnvs[] = {
169 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
170 };
171
172-static const struct i2c_device_id pfuze_device_id[] = {
173- {.name = "pfuze100"},
174- {},
175+static const struct i2c_device_id pfuze_device_id[PFUZE_NUM] = {
176+ {.name = "pfuze100", .driver_data = PFUZE100},
177+ {.name = "pfuze200", .driver_data = PFUZE200},
178 };
179 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
180
181-static const struct of_device_id pfuze_dt_ids[] = {
182- { .compatible = "fsl,pfuze100" },
183- {},
184+static const struct of_device_id pfuze_dt_ids[PFUZE_NUM] = {
185+ { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
186+ { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
187 };
188 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
189
190@@ -139,14 +142,14 @@ static struct regulator_ops pfuze100_swb_regulator_ops = {
191
192 };
193
194-#define PFUZE100_FIXED_REG(_name, base, voltage) \
195- [PFUZE100_ ## _name] = { \
196+#define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
197+ [_chip ## _ ## _name] = { \
198 .desc = { \
199 .name = #_name, \
200 .n_voltages = 1, \
201 .ops = &pfuze100_fixed_regulator_ops, \
202 .type = REGULATOR_VOLTAGE, \
203- .id = PFUZE100_ ## _name, \
204+ .id = _chip ## _ ## _name, \
205 .owner = THIS_MODULE, \
206 .min_uV = (voltage), \
207 .enable_reg = (base), \
208@@ -154,14 +157,14 @@ static struct regulator_ops pfuze100_swb_regulator_ops = {
209 }, \
210 }
211
212-#define PFUZE100_SW_REG(_name, base, min, max, step) \
213- [PFUZE100_ ## _name] = { \
214+#define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
215+ [_chip ## _ ## _name] = { \
216 .desc = { \
217 .name = #_name,\
218 .n_voltages = ((max) - (min)) / (step) + 1, \
219 .ops = &pfuze100_sw_regulator_ops, \
220 .type = REGULATOR_VOLTAGE, \
221- .id = PFUZE100_ ## _name, \
222+ .id = _chip ## _ ## _name, \
223 .owner = THIS_MODULE, \
224 .min_uV = (min), \
225 .uV_step = (step), \
226@@ -172,14 +175,14 @@ static struct regulator_ops pfuze100_swb_regulator_ops = {
227 .stby_mask = 0x3f, \
228 }
229
230-#define PFUZE100_SWB_REG(_name, base, mask, voltages) \
231- [PFUZE100_ ## _name] = { \
232+#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
233+ [_chip ## _ ## _name] = { \
234 .desc = { \
235 .name = #_name, \
236 .n_voltages = ARRAY_SIZE(voltages), \
237 .ops = &pfuze100_swb_regulator_ops, \
238 .type = REGULATOR_VOLTAGE, \
239- .id = PFUZE100_ ## _name, \
240+ .id = _chip ## _ ## _name, \
241 .owner = THIS_MODULE, \
242 .volt_table = voltages, \
243 .vsel_reg = (base), \
244@@ -187,14 +190,14 @@ static struct regulator_ops pfuze100_swb_regulator_ops = {
245 }, \
246 }
247
248-#define PFUZE100_VGEN_REG(_name, base, min, max, step) \
249- [PFUZE100_ ## _name] = { \
250+#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
251+ [_chip ## _ ## _name] = { \
252 .desc = { \
253 .name = #_name, \
254 .n_voltages = ((max) - (min)) / (step) + 1, \
255 .ops = &pfuze100_ldo_regulator_ops, \
256 .type = REGULATOR_VOLTAGE, \
257- .id = PFUZE100_ ## _name, \
258+ .id = _chip ## _ ## _name, \
259 .owner = THIS_MODULE, \
260 .min_uV = (min), \
261 .uV_step = (step), \
262@@ -207,25 +210,45 @@ static struct regulator_ops pfuze100_swb_regulator_ops = {
263 .stby_mask = 0x20, \
264 }
265
266+/* PFUZE100 */
267 static struct pfuze_regulator pfuze100_regulators[] = {
268- PFUZE100_SW_REG(SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
269- PFUZE100_SW_REG(SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
270- PFUZE100_SW_REG(SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
271- PFUZE100_SW_REG(SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
272- PFUZE100_SW_REG(SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
273- PFUZE100_SW_REG(SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
274- PFUZE100_SWB_REG(SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
275- PFUZE100_SWB_REG(VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
276- PFUZE100_FIXED_REG(VREFDDR, PFUZE100_VREFDDRCON, 750000),
277- PFUZE100_VGEN_REG(VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
278- PFUZE100_VGEN_REG(VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
279- PFUZE100_VGEN_REG(VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
280- PFUZE100_VGEN_REG(VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
281- PFUZE100_VGEN_REG(VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
282- PFUZE100_VGEN_REG(VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
283+ PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
284+ PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
285+ PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
286+ PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
287+ PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
288+ PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
289+ PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
290+ PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
291+ PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
292+ PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
293+ PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
294+ PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
295+ PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
296+ PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
297+ PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
298+};
299+
300+static struct pfuze_regulator pfuze200_regulators[] = {
301+ PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
302+ PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
303+ PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
304+ PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
305+ PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
306+ PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
307+ PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
308+ PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
309+ PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
310+ PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
311+ PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
312+ PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
313+ PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
314 };
315
316+static struct pfuze_regulator *pfuze_regulators;
317+
318 #ifdef CONFIG_OF
319+/* PFUZE100 */
320 static struct of_regulator_match pfuze100_matches[] = {
321 { .name = "sw1ab", },
322 { .name = "sw1c", },
323@@ -244,6 +267,26 @@ static struct of_regulator_match pfuze100_matches[] = {
324 { .name = "vgen6", },
325 };
326
327+/* PFUZE200 */
328+static struct of_regulator_match pfuze200_matches[] = {
329+
330+ { .name = "sw1ab", },
331+ { .name = "sw2", },
332+ { .name = "sw3a", },
333+ { .name = "sw3b", },
334+ { .name = "swbst", },
335+ { .name = "vsnvs", },
336+ { .name = "vrefddr", },
337+ { .name = "vgen1", },
338+ { .name = "vgen2", },
339+ { .name = "vgen3", },
340+ { .name = "vgen4", },
341+ { .name = "vgen5", },
342+ { .name = "vgen6", },
343+};
344+
345+static struct of_regulator_match *pfuze_matches;
346+
347 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
348 {
349 struct device *dev = chip->dev;
350@@ -260,8 +303,20 @@ static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
351 return -EINVAL;
352 }
353
354- ret = of_regulator_match(dev, parent, pfuze100_matches,
355- ARRAY_SIZE(pfuze100_matches));
356+ switch (chip->chip_id) {
357+ case PFUZE200:
358+ pfuze_matches = pfuze200_matches;
359+ ret = of_regulator_match(dev, parent, pfuze200_matches,
360+ ARRAY_SIZE(pfuze200_matches));
361+ break;
362+
363+ case PFUZE100:
364+ default:
365+ pfuze_matches = pfuze100_matches;
366+ ret = of_regulator_match(dev, parent, pfuze100_matches,
367+ ARRAY_SIZE(pfuze100_matches));
368+ break;
369+ }
370
371 of_node_put(parent);
372 if (ret < 0) {
373@@ -275,12 +330,12 @@ static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
374
375 static inline struct regulator_init_data *match_init_data(int index)
376 {
377- return pfuze100_matches[index].init_data;
378+ return pfuze_matches[index].init_data;
379 }
380
381 static inline struct device_node *match_of_node(int index)
382 {
383- return pfuze100_matches[index].of_node;
384+ return pfuze_matches[index].of_node;
385 }
386 #else
387 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
388@@ -308,7 +363,8 @@ static int pfuze_identify(struct pfuze_chip *pfuze_chip)
389 if (ret)
390 return ret;
391
392- if (value & 0x0f) {
393+ if ((value & 0x0f) != pfuze_chip->chip_id) {
394+ /* device id NOT match with your setting */
395 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
396 return -ENODEV;
397 }
398@@ -344,17 +400,31 @@ static int pfuze100_regulator_probe(struct i2c_client *client,
399 dev_get_platdata(&client->dev);
400 struct regulator_config config = { };
401 int i, ret;
402+ const struct of_device_id *match;
403+ u32 regulator_num;
404+ u32 sw_check_start, sw_check_end;
405
406 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
407 GFP_KERNEL);
408 if (!pfuze_chip)
409 return -ENOMEM;
410
411- i2c_set_clientdata(client, pfuze_chip);
412-
413- memcpy(pfuze_chip->regulator_descs, pfuze100_regulators,
414- sizeof(pfuze_chip->regulator_descs));
415+ if (client->dev.of_node) {
416+ match = of_match_device(of_match_ptr(pfuze_dt_ids),
417+ &client->dev);
418+ if (!match) {
419+ dev_err(&client->dev, "Error: No device match found\n");
420+ return -ENODEV;
421+ }
422+ pfuze_chip->chip_id = (int)(long)match->data;
423+ } else if (id) {
424+ pfuze_chip->chip_id = id->driver_data;
425+ } else {
426+ dev_err(&client->dev, "No dts match or id table match found\n");
427+ return -ENODEV;
428+ }
429
430+ i2c_set_clientdata(client, pfuze_chip);
431 pfuze_chip->dev = &client->dev;
432
433 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
434@@ -371,11 +441,34 @@ static int pfuze100_regulator_probe(struct i2c_client *client,
435 return ret;
436 }
437
438+ /* use the right regulators after identify the right device */
439+ switch (pfuze_chip->chip_id) {
440+ case PFUZE200:
441+ pfuze_regulators = pfuze200_regulators;
442+ regulator_num = ARRAY_SIZE(pfuze200_regulators);
443+ sw_check_start = PFUZE200_SW2;
444+ sw_check_end = PFUZE200_SW3B;
445+ break;
446+
447+ case PFUZE100:
448+ default:
449+ pfuze_regulators = pfuze100_regulators;
450+ regulator_num = ARRAY_SIZE(pfuze100_regulators);
451+ sw_check_start = PFUZE100_SW2;
452+ sw_check_end = PFUZE100_SW4;
453+ break;
454+ }
455+ dev_info(&client->dev, "pfuze%s found.\n",
456+ (pfuze_chip->chip_id == PFUZE100) ? "100" : "200");
457+
458+ memcpy(pfuze_chip->regulator_descs, pfuze_regulators,
459+ sizeof(pfuze_chip->regulator_descs));
460+
461 ret = pfuze_parse_regulators_dt(pfuze_chip);
462 if (ret)
463 return ret;
464
465- for (i = 0; i < PFUZE100_MAX_REGULATOR; i++) {
466+ for (i = 0; i < regulator_num; i++) {
467 struct regulator_init_data *init_data;
468 struct regulator_desc *desc;
469 int val;
470@@ -388,7 +481,7 @@ static int pfuze100_regulator_probe(struct i2c_client *client,
471 init_data = match_init_data(i);
472
473 /* SW2~SW4 high bit check and modify the voltage value table */
474- if (i > PFUZE100_SW1C && i < PFUZE100_SWBST) {
475+ if (i >= sw_check_start && i <= sw_check_end) {
476 regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
477 if (val & 0x40) {
478 desc->min_uV = 800000;
479diff --git a/include/linux/regulator/pfuze100.h b/include/linux/regulator/pfuze100.h
480index 65d550b..364f7a7 100644
481--- a/include/linux/regulator/pfuze100.h
482+++ b/include/linux/regulator/pfuze100.h
483@@ -35,6 +35,20 @@
484 #define PFUZE100_VGEN6 14
485 #define PFUZE100_MAX_REGULATOR 15
486
487+#define PFUZE200_SW1AB 0
488+#define PFUZE200_SW2 1
489+#define PFUZE200_SW3A 2
490+#define PFUZE200_SW3B 3
491+#define PFUZE200_SWBST 4
492+#define PFUZE200_VSNVS 5
493+#define PFUZE200_VREFDDR 6
494+#define PFUZE200_VGEN1 7
495+#define PFUZE200_VGEN2 8
496+#define PFUZE200_VGEN3 9
497+#define PFUZE200_VGEN4 10
498+#define PFUZE200_VGEN5 11
499+#define PFUZE200_VGEN6 12
500+
501 struct regulator_init_data;
502
503 struct pfuze_regulator_platform_data {
504--
5052.1.0
506
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0004-regulator-pfuze100-Add-terminate-entry-for-i2c-of-_d.patch b/recipes-kernel/linux/linux-imx-3.10.17/0004-regulator-pfuze100-Add-terminate-entry-for-i2c-of-_d.patch
new file mode 100644
index 0000000..c7381e3
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0004-regulator-pfuze100-Add-terminate-entry-for-i2c-of-_d.patch
@@ -0,0 +1,61 @@
1From fdbdb66994db6b896a5a6464b9c1efd7abfbfdb9 Mon Sep 17 00:00:00 2001
2From: Axel Lin <axel.lin@ingics.com>
3Date: Tue, 4 Mar 2014 18:20:14 +0800
4Subject: [PATCH 04/10] regulator: pfuze100: Add terminate entry for
5 [i2c|of]_device_id tables
6Organization: O.S. Systems Software LTDA.
7
8Also remove PFUZE_NUM to avoid below build warnings:
9
10 CC [M] drivers/regulator/pfuze100-regulator.o
11drivers/regulator/pfuze100-regulator.c:86:2: warning: excess elements in array initializer [enabled by default]
12drivers/regulator/pfuze100-regulator.c:86:2: warning: (near initialization for 'pfuze_device_id') [enabled by default]
13drivers/regulator/pfuze100-regulator.c:93:2: warning: excess elements in array initializer [enabled by default]
14drivers/regulator/pfuze100-regulator.c:93:2: warning: (near initialization for 'pfuze_dt_ids') [enabled by default]
15
16Signed-off-by: Axel Lin <axel.lin@ingics.com>
17Signed-off-by: Mark Brown <broonie@linaro.org>
18(cherry picked from commit e6c4c3378d82c5eeb136ed06b1a23651bcdaf739)
19(cherry picked from commit 12c7dd7c396378fd6dc907903a4ae540a75b31f5)
20
21Upstream-Status: Pending
22---
23 drivers/regulator/pfuze100-regulator.c | 8 +++++---
24 1 file changed, 5 insertions(+), 3 deletions(-)
25
26diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
27index 35b1de1..0f4924e0 100644
28--- a/drivers/regulator/pfuze100-regulator.c
29+++ b/drivers/regulator/pfuze100-regulator.c
30@@ -56,7 +56,7 @@
31 #define PFUZE100_VGEN5VOL 0x70
32 #define PFUZE100_VGEN6VOL 0x71
33
34-enum chips {PFUZE100, PFUZE200, PFUZE_NUM};
35+enum chips { PFUZE100, PFUZE200 };
36
37 struct pfuze_regulator {
38 struct regulator_desc desc;
39@@ -80,15 +80,17 @@ static const int pfuze100_vsnvs[] = {
40 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
41 };
42
43-static const struct i2c_device_id pfuze_device_id[PFUZE_NUM] = {
44+static const struct i2c_device_id pfuze_device_id[] = {
45 {.name = "pfuze100", .driver_data = PFUZE100},
46 {.name = "pfuze200", .driver_data = PFUZE200},
47+ { }
48 };
49 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
50
51-static const struct of_device_id pfuze_dt_ids[PFUZE_NUM] = {
52+static const struct of_device_id pfuze_dt_ids[] = {
53 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
54 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
55+ { }
56 };
57 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
58
59--
602.1.0
61
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0005-regulator-pfuze100-Add-PFUZE200-support-to-Kconfig-a.patch b/recipes-kernel/linux/linux-imx-3.10.17/0005-regulator-pfuze100-Add-PFUZE200-support-to-Kconfig-a.patch
new file mode 100644
index 0000000..7fcc79d
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0005-regulator-pfuze100-Add-PFUZE200-support-to-Kconfig-a.patch
@@ -0,0 +1,56 @@
1From 2610dd3d4f0f167b77c4ce24e1756f7434a17cde Mon Sep 17 00:00:00 2001
2From: Axel Lin <axel.lin@ingics.com>
3Date: Wed, 5 Mar 2014 18:02:43 +0800
4Subject: [PATCH 05/10] regulator: pfuze100: Add PFUZE200 support to Kconfig
5 and module description
6Organization: O.S. Systems Software LTDA.
7
8Signed-off-by: Axel Lin <axel.lin@ingics.com>
9Acked-by: Robin Gong <b38343@freescale.com>
10Signed-off-by: Mark Brown <broonie@linaro.org>
11(cherry picked from commit 2cee2121db44cfeee206d0854bedd52344eea444)
12
13Signed-off-by: Robin Gong <b38343@freescale.com>
14(cherry picked from commit 88236aaba4ed9b89a7873b30fc1ca9cdcb6b407d)
15
16Upstream-Status: Pending
17---
18 drivers/regulator/Kconfig | 6 +++---
19 drivers/regulator/pfuze100-regulator.c | 2 +-
20 2 files changed, 4 insertions(+), 4 deletions(-)
21
22diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
23index 1339404..5b64f2c 100644
24--- a/drivers/regulator/Kconfig
25+++ b/drivers/regulator/Kconfig
26@@ -305,12 +305,12 @@ config REGULATOR_PCF50633
27 on PCF50633
28
29 config REGULATOR_PFUZE100
30- tristate "Support regulators on Freescale PFUZE100 PMIC"
31+ tristate "Freescale PFUZE100/PFUZE200 regulator driver"
32 depends on I2C
33 select REGMAP_I2C
34 help
35- Say y here to support the regulators found on the Freescale PFUZE100
36- PMIC.
37+ Say y here to support the regulators found on the Freescale
38+ PFUZE100/PFUZE200 PMIC.
39
40 config REGULATOR_RC5T583
41 tristate "RICOH RC5T583 Power regulators"
42diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
43index 0f4924e0..21114f7 100644
44--- a/drivers/regulator/pfuze100-regulator.c
45+++ b/drivers/regulator/pfuze100-regulator.c
46@@ -535,6 +535,6 @@ static struct i2c_driver pfuze_driver = {
47 module_i2c_driver(pfuze_driver);
48
49 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
50-MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
51+MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/PFUZE200 PMIC");
52 MODULE_LICENSE("GPL v2");
53 MODULE_ALIAS("i2c:pfuze100-regulator");
54--
552.1.0
56
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0006-regulator-pfuze100-Use-of_get_child_by_name.patch b/recipes-kernel/linux/linux-imx-3.10.17/0006-regulator-pfuze100-Use-of_get_child_by_name.patch
new file mode 100644
index 0000000..21b2e0c
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0006-regulator-pfuze100-Use-of_get_child_by_name.patch
@@ -0,0 +1,34 @@
1From cef8d38fc22ed27e26c8b3d8594c152b6c542253 Mon Sep 17 00:00:00 2001
2From: Sachin Kamat <sachin.kamat@linaro.org>
3Date: Fri, 14 Feb 2014 17:20:00 +0530
4Subject: [PATCH 06/10] regulator: pfuze100: Use of_get_child_by_name
5Organization: O.S. Systems Software LTDA.
6
7of_find_node_by_name walks the allnodes list, and can thus walk
8outside of the parent node. Use of_get_child_by_name instead.
9
10Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
11Signed-off-by: Mark Brown <broonie@linaro.org>
12(cherry picked from commit 4d286178d55cc5811d50750a44eb729252adef11)
13
14Upstream-Status: Pending
15---
16 drivers/regulator/pfuze100-regulator.c | 2 +-
17 1 file changed, 1 insertion(+), 1 deletion(-)
18
19diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
20index 21114f7..15059c74 100644
21--- a/drivers/regulator/pfuze100-regulator.c
22+++ b/drivers/regulator/pfuze100-regulator.c
23@@ -299,7 +299,7 @@ static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
24 if (!np)
25 return 0;
26
27- parent = of_find_node_by_name(np, "regulators");
28+ parent = of_get_child_by_name(np, "regulators");
29 if (!parent) {
30 dev_err(dev, "regulators node not found\n");
31 return -EINVAL;
32--
332.1.0
34
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0007-pfuze100-regulator-Fix-of_node_get-parameter.patch b/recipes-kernel/linux/linux-imx-3.10.17/0007-pfuze100-regulator-Fix-of_node_get-parameter.patch
new file mode 100644
index 0000000..d077858
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0007-pfuze100-regulator-Fix-of_node_get-parameter.patch
@@ -0,0 +1,44 @@
1From cc1f086131aa802abc38428a5a690eb5f35c8225 Mon Sep 17 00:00:00 2001
2From: Fabio Estevam <fabio.estevam@freescale.com>
3Date: Tue, 18 Feb 2014 23:46:14 -0300
4Subject: [PATCH 07/10] pfuze100-regulator: Fix of_node_get() parameter
5Organization: O.S. Systems Software LTDA.
6
7Since commit d7857c42 (regulator: pfuze100: Use of_get_child_by_name) we get
8the following probe failure:
9
10pfuze100-regulator 1-0008: Full layer: 1, Metal layer: 0
11pfuze100-regulator 1-0008: FAB: 0, FIN: 0
12pfuze100-regulator 1-0008: regulators node not found
13pfuze100-regulator: probe of 1-0008 failed with error -22
14
15Now that of_get_child_by_name() is used we should adjust the device_node pointer
16'np' to not get the parent node anymore.
17
18Suggested-by: Shawn Guo <shawn.guo@linaro.org>
19Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
20Acked-by: Sachin Kamat <sachin.kamat@linaro.org>
21Signed-off-by: Mark Brown <broonie@linaro.org>
22(cherry picked from commit 0780208ff201feb45e12ebecb39ecac4740b1244)
23
24Upstream-Status: Pending
25---
26 drivers/regulator/pfuze100-regulator.c | 2 +-
27 1 file changed, 1 insertion(+), 1 deletion(-)
28
29diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
30index 15059c74..b9c1b9a 100644
31--- a/drivers/regulator/pfuze100-regulator.c
32+++ b/drivers/regulator/pfuze100-regulator.c
33@@ -295,7 +295,7 @@ static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
34 struct device_node *np, *parent;
35 int ret;
36
37- np = of_node_get(dev->parent->of_node);
38+ np = of_node_get(dev->of_node);
39 if (!np)
40 return 0;
41
42--
432.1.0
44
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0008-ENGR00301078-1-ARM-dts-imx6dl-sabresd-add-support-fo.patch b/recipes-kernel/linux/linux-imx-3.10.17/0008-ENGR00301078-1-ARM-dts-imx6dl-sabresd-add-support-fo.patch
new file mode 100644
index 0000000..f1e88d4
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0008-ENGR00301078-1-ARM-dts-imx6dl-sabresd-add-support-fo.patch
@@ -0,0 +1,752 @@
1From 37e501e8c4e1f1511e017aa0a7def38895a47fa6 Mon Sep 17 00:00:00 2001
2From: Robin Gong <b38343@freescale.com>
3Date: Thu, 6 Mar 2014 18:59:30 +0800
4Subject: [PATCH 08/10] ENGR00301078-1: ARM: dts: imx6dl-sabresd: add support
5 for pfuze200 on mx6dl-sabresd
6Organization: O.S. Systems Software LTDA.
7
8move pmic device node from imx6qdl-sabresd.dtsi to up-level, and add
9another layer on imx6dl-sabresd to diff pfuze100 or pfuze200. Meanwhile
10only work in ldo-enable mode if using pfuze200,since 'SW1C' switch
11regulator is cut for cost-down which means VDDARM_IN and VDDSOC_IN have
12to share the same switch regulator
13
14Signed-off-by: Robin Gong <b38343@freescale.com>
15(cherry picked from commit 32e4e161b087bfdcea74bd80f0b24c341092c96b)
16
17Upstream-Status: Pending
18---
19 arch/arm/boot/dts/Makefile | 1 +
20 arch/arm/boot/dts/imx6dl-sabresd-common.dtsi | 130 ++++++++++++++++++++
21 arch/arm/boot/dts/imx6dl-sabresd-pf200.dts | 126 +++++++++++++++++++
22 arch/arm/boot/dts/imx6dl-sabresd.dts | 175 ++++++++++++---------------
23 arch/arm/boot/dts/imx6q-sabresd.dts | 101 ++++++++++++++++
24 arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 99 ---------------
25 6 files changed, 435 insertions(+), 197 deletions(-)
26 create mode 100644 arch/arm/boot/dts/imx6dl-sabresd-common.dtsi
27 create mode 100644 arch/arm/boot/dts/imx6dl-sabresd-pf200.dts
28
29diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
30index f43b68b..c744cda 100644
31--- a/arch/arm/boot/dts/Makefile
32+++ b/arch/arm/boot/dts/Makefile
33@@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
34 imx6dl-sabresd.dtb \
35 imx6dl-sabresd-hdcp.dtb \
36 imx6dl-sabresd-ldo.dtb \
37+ imx6dl-sabresd-pf200.dtb \
38 imx6dl-wandboard.dtb \
39 imx6q-arm2.dtb \
40 imx6q-sabreauto.dtb \
41diff --git a/arch/arm/boot/dts/imx6dl-sabresd-common.dtsi b/arch/arm/boot/dts/imx6dl-sabresd-common.dtsi
42new file mode 100644
43index 0000000..2a07534
44--- /dev/null
45+++ b/arch/arm/boot/dts/imx6dl-sabresd-common.dtsi
46@@ -0,0 +1,130 @@
47+/*
48+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
49+ *
50+ * This program is free software; you can redistribute it and/or modify
51+ * it under the terms of the GNU General Public License version 2 as
52+ * published by the Free Software Foundation.
53+ */
54+
55+&battery {
56+ offset-charger = <1485>;
57+ offset-discharger = <1464>;
58+ offset-usb-charger = <1285>;
59+};
60+
61+&i2c3 {
62+ max17135@48 {
63+ compatible = "maxim,max17135";
64+ reg = <0x48>;
65+ vneg_pwrup = <1>;
66+ gvee_pwrup = <1>;
67+ vpos_pwrup = <2>;
68+ gvdd_pwrup = <1>;
69+ gvdd_pwrdn = <1>;
70+ vpos_pwrdn = <2>;
71+ gvee_pwrdn = <1>;
72+ vneg_pwrdn = <1>;
73+ SENSOR-supply = <&reg_sensor>;
74+ gpio_pmic_pwrgood = <&gpio2 21 0>;
75+ gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
76+ gpio_pmic_wakeup = <&gpio3 20 0>;
77+ gpio_pmic_v3p3 = <&gpio2 20 0>;
78+ gpio_pmic_intr = <&gpio2 25 0>;
79+
80+ regulators {
81+ DISPLAY_reg: DISPLAY {
82+ regulator-name = "DISPLAY";
83+ };
84+
85+ GVDD_reg: GVDD {
86+ /* 20v */
87+ regulator-name = "GVDD";
88+ };
89+
90+ GVEE_reg: GVEE {
91+ /* -22v */
92+ regulator-name = "GVEE";
93+ };
94+
95+ HVINN_reg: HVINN {
96+ /* -22v */
97+ regulator-name = "HVINN";
98+ };
99+
100+ HVINP_reg: HVINP {
101+ /* 20v */
102+ regulator-name = "HVINP";
103+ };
104+
105+ VCOM_reg: VCOM {
106+ regulator-name = "VCOM";
107+ /* 2's-compliment, -4325000 */
108+ regulator-min-microvolt = <0xffbe0178>;
109+ /* 2's-compliment, -500000 */
110+ regulator-max-microvolt = <0xfff85ee0>;
111+ };
112+
113+ VNEG_reg: VNEG {
114+ /* -15v */
115+ regulator-name = "VNEG";
116+ };
117+
118+ VPOS_reg: VPOS {
119+ /* 15v */
120+ regulator-name = "VPOS";
121+ };
122+
123+ V3P3_reg: V3P3 {
124+ regulator-name = "V3P3";
125+ };
126+ };
127+ };
128+};
129+
130+&iomuxc {
131+ pinctrl-names = "default";
132+ pinctrl-0 = <&pinctrl_hog_1>, <&pinctrl_hog_2>;
133+
134+ hog {
135+ pinctrl_hog_2: hoggrp-2 {
136+ fsl,pins = <
137+ /* MAX17135 */
138+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
139+ MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x80000000
140+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
141+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
142+ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
143+ /* elan touch */
144+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
145+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
146+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x170b0
147+ >;
148+ };
149+ };
150+};
151+
152+&epdc {
153+ pinctrl-names = "default";
154+ pinctrl-0 = <&pinctrl_epdc_0>;
155+ V3P3-supply = <&V3P3_reg>;
156+ VCOM-supply = <&VCOM_reg>;
157+ DISPLAY-supply = <&DISPLAY_reg>;
158+ status = "okay";
159+};
160+
161+&ldb {
162+ ipu_id = <0>;
163+ sec_ipu_id = <0>;
164+};
165+
166+&mxcfb1 {
167+ status = "okay";
168+};
169+
170+&mxcfb2 {
171+ status = "okay";
172+};
173+
174+&pxp {
175+ status = "okay";
176+};
177diff --git a/arch/arm/boot/dts/imx6dl-sabresd-pf200.dts b/arch/arm/boot/dts/imx6dl-sabresd-pf200.dts
178new file mode 100644
179index 0000000..499f7d3
180--- /dev/null
181+++ b/arch/arm/boot/dts/imx6dl-sabresd-pf200.dts
182@@ -0,0 +1,126 @@
183+/*
184+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
185+ *
186+ * This program is free software; you can redistribute it and/or modify
187+ * it under the terms of the GNU General Public License version 2 as
188+ * published by the Free Software Foundation.
189+ */
190+
191+/dts-v1/;
192+
193+#include "imx6dl.dtsi"
194+#include "imx6qdl-sabresd.dtsi"
195+#include "imx6dl-sabresd-common.dtsi"
196+
197+/ {
198+ model = "Freescale i.MX6 DualLite SABRE Smart Device Board(PFUZE200)";
199+ compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
200+};
201+
202+&cpu0 {
203+ arm-supply = <&reg_arm>;
204+ soc-supply = <&reg_soc>;
205+ pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */
206+};
207+
208+&gpc {
209+ fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */
210+ fsl,wdog-reset = <1>; /* watchdog select of reset source */
211+ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
212+};
213+
214+&gpu {
215+ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
216+};
217+
218+&vpu {
219+ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
220+};
221+
222+&i2c2 {
223+ pmic: pfuze200@08 {
224+ compatible = "fsl,pfuze200";
225+ reg = <0x08>;
226+
227+ regulators {
228+ sw1a_reg: sw1ab {
229+ regulator-min-microvolt = <300000>;
230+ regulator-max-microvolt = <1875000>;
231+ regulator-boot-on;
232+ regulator-always-on;
233+ regulator-ramp-delay = <6250>;
234+ };
235+
236+ sw2_reg: sw2 {
237+ regulator-min-microvolt = <800000>;
238+ regulator-max-microvolt = <3300000>;
239+ regulator-boot-on;
240+ regulator-always-on;
241+ };
242+
243+ sw3a_reg: sw3a {
244+ regulator-min-microvolt = <400000>;
245+ regulator-max-microvolt = <1975000>;
246+ regulator-boot-on;
247+ regulator-always-on;
248+ };
249+
250+ sw3b_reg: sw3b {
251+ regulator-min-microvolt = <400000>;
252+ regulator-max-microvolt = <1975000>;
253+ regulator-boot-on;
254+ regulator-always-on;
255+ };
256+
257+ swbst_reg: swbst {
258+ regulator-min-microvolt = <5000000>;
259+ regulator-max-microvolt = <5150000>;
260+ };
261+
262+ snvs_reg: vsnvs {
263+ regulator-min-microvolt = <1000000>;
264+ regulator-max-microvolt = <3000000>;
265+ regulator-boot-on;
266+ regulator-always-on;
267+ };
268+
269+ vref_reg: vrefddr {
270+ regulator-boot-on;
271+ regulator-always-on;
272+ };
273+
274+ vgen1_reg: vgen1 {
275+ regulator-min-microvolt = <800000>;
276+ regulator-max-microvolt = <1550000>;
277+ };
278+
279+ vgen2_reg: vgen2 {
280+ regulator-min-microvolt = <800000>;
281+ regulator-max-microvolt = <1550000>;
282+ };
283+
284+ vgen3_reg: vgen3 {
285+ regulator-min-microvolt = <1800000>;
286+ regulator-max-microvolt = <3300000>;
287+ };
288+
289+ vgen4_reg: vgen4 {
290+ regulator-min-microvolt = <1800000>;
291+ regulator-max-microvolt = <3300000>;
292+ regulator-always-on;
293+ };
294+
295+ vgen5_reg: vgen5 {
296+ regulator-min-microvolt = <1800000>;
297+ regulator-max-microvolt = <3300000>;
298+ regulator-always-on;
299+ };
300+
301+ vgen6_reg: vgen6 {
302+ regulator-min-microvolt = <1800000>;
303+ regulator-max-microvolt = <3300000>;
304+ regulator-always-on;
305+ };
306+ };
307+ };
308+};
309diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
310index 5713c71..b4c738d 100644
311--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
312+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
313@@ -1,5 +1,5 @@
314 /*
315- * Copyright (C) 2013 Freescale Semiconductor, Inc.
316+ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
317 *
318 * This program is free software; you can redistribute it and/or modify
319 * it under the terms of the GNU General Public License version 2 as
320@@ -10,131 +10,110 @@
321
322 #include "imx6dl.dtsi"
323 #include "imx6qdl-sabresd.dtsi"
324+#include "imx6dl-sabresd-common.dtsi"
325
326 / {
327- model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
328+ model = "Freescale i.MX6 DualLite SABRE Smart Device Board(PFUZE100)";
329 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
330 };
331
332-&battery {
333- offset-charger = <1485>;
334- offset-discharger = <1464>;
335- offset-usb-charger = <1285>;
336-};
337-
338-&i2c3 {
339- max17135@48 {
340- compatible = "maxim,max17135";
341- reg = <0x48>;
342- vneg_pwrup = <1>;
343- gvee_pwrup = <1>;
344- vpos_pwrup = <2>;
345- gvdd_pwrup = <1>;
346- gvdd_pwrdn = <1>;
347- vpos_pwrdn = <2>;
348- gvee_pwrdn = <1>;
349- vneg_pwrdn = <1>;
350- SENSOR-supply = <&reg_sensor>;
351- gpio_pmic_pwrgood = <&gpio2 21 0>;
352- gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
353- gpio_pmic_wakeup = <&gpio3 20 0>;
354- gpio_pmic_v3p3 = <&gpio2 20 0>;
355- gpio_pmic_intr = <&gpio2 25 0>;
356+&i2c2 {
357+ pmic: pfuze100@08 {
358+ compatible = "fsl,pfuze100";
359+ reg = <0x08>;
360
361 regulators {
362- DISPLAY_reg: DISPLAY {
363- regulator-name = "DISPLAY";
364+ sw1a_reg: sw1ab {
365+ regulator-min-microvolt = <300000>;
366+ regulator-max-microvolt = <1875000>;
367+ regulator-boot-on;
368+ regulator-always-on;
369+ regulator-ramp-delay = <6250>;
370 };
371
372- GVDD_reg: GVDD {
373- /* 20v */
374- regulator-name = "GVDD";
375+ sw1c_reg: sw1c {
376+ regulator-min-microvolt = <300000>;
377+ regulator-max-microvolt = <1875000>;
378+ regulator-boot-on;
379+ regulator-always-on;
380+ regulator-ramp-delay = <6250>;
381 };
382
383- GVEE_reg: GVEE {
384- /* -22v */
385- regulator-name = "GVEE";
386+ sw2_reg: sw2 {
387+ regulator-min-microvolt = <800000>;
388+ regulator-max-microvolt = <3300000>;
389+ regulator-boot-on;
390+ regulator-always-on;
391 };
392
393- HVINN_reg: HVINN {
394- /* -22v */
395- regulator-name = "HVINN";
396+ sw3a_reg: sw3a {
397+ regulator-min-microvolt = <400000>;
398+ regulator-max-microvolt = <1975000>;
399+ regulator-boot-on;
400+ regulator-always-on;
401 };
402
403- HVINP_reg: HVINP {
404- /* 20v */
405- regulator-name = "HVINP";
406+ sw3b_reg: sw3b {
407+ regulator-min-microvolt = <400000>;
408+ regulator-max-microvolt = <1975000>;
409+ regulator-boot-on;
410+ regulator-always-on;
411 };
412
413- VCOM_reg: VCOM {
414- regulator-name = "VCOM";
415- /* 2's-compliment, -4325000 */
416- regulator-min-microvolt = <0xffbe0178>;
417- /* 2's-compliment, -500000 */
418- regulator-max-microvolt = <0xfff85ee0>;
419+ sw4_reg: sw4 {
420+ regulator-min-microvolt = <800000>;
421+ regulator-max-microvolt = <3300000>;
422 };
423
424- VNEG_reg: VNEG {
425- /* -15v */
426- regulator-name = "VNEG";
427+ swbst_reg: swbst {
428+ regulator-min-microvolt = <5000000>;
429+ regulator-max-microvolt = <5150000>;
430 };
431
432- VPOS_reg: VPOS {
433- /* 15v */
434- regulator-name = "VPOS";
435+ snvs_reg: vsnvs {
436+ regulator-min-microvolt = <1000000>;
437+ regulator-max-microvolt = <3000000>;
438+ regulator-boot-on;
439+ regulator-always-on;
440 };
441
442- V3P3_reg: V3P3 {
443- regulator-name = "V3P3";
444+ vref_reg: vrefddr {
445+ regulator-boot-on;
446+ regulator-always-on;
447 };
448- };
449- };
450-};
451
452-&iomuxc {
453- pinctrl-names = "default";
454- pinctrl-0 = <&pinctrl_hog_1>, <&pinctrl_hog_2>;
455-
456- hog {
457- pinctrl_hog_2: hoggrp-2 {
458- fsl,pins = <
459- /* MAX17135 */
460- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
461- MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x80000000
462- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
463- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
464- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
465- /* elan touch */
466- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
467- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
468- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x170b0
469- >;
470- };
471- };
472-};
473+ vgen1_reg: vgen1 {
474+ regulator-min-microvolt = <800000>;
475+ regulator-max-microvolt = <1550000>;
476+ };
477
478-&epdc {
479- pinctrl-names = "default";
480- pinctrl-0 = <&pinctrl_epdc_0>;
481- V3P3-supply = <&V3P3_reg>;
482- VCOM-supply = <&VCOM_reg>;
483- DISPLAY-supply = <&DISPLAY_reg>;
484- status = "okay";
485-};
486+ vgen2_reg: vgen2 {
487+ regulator-min-microvolt = <800000>;
488+ regulator-max-microvolt = <1550000>;
489+ };
490
491-&ldb {
492- ipu_id = <0>;
493- sec_ipu_id = <0>;
494-};
495+ vgen3_reg: vgen3 {
496+ regulator-min-microvolt = <1800000>;
497+ regulator-max-microvolt = <3300000>;
498+ };
499
500-&mxcfb1 {
501- status = "okay";
502-};
503+ vgen4_reg: vgen4 {
504+ regulator-min-microvolt = <1800000>;
505+ regulator-max-microvolt = <3300000>;
506+ regulator-always-on;
507+ };
508
509-&mxcfb2 {
510- status = "okay";
511-};
512+ vgen5_reg: vgen5 {
513+ regulator-min-microvolt = <1800000>;
514+ regulator-max-microvolt = <3300000>;
515+ regulator-always-on;
516+ };
517
518-&pxp {
519- status = "okay";
520+ vgen6_reg: vgen6 {
521+ regulator-min-microvolt = <1800000>;
522+ regulator-max-microvolt = <3300000>;
523+ regulator-always-on;
524+ };
525+ };
526+ };
527 };
528diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
529index 072e7d3..5e5ff56 100644
530--- a/arch/arm/boot/dts/imx6q-sabresd.dts
531+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
532@@ -26,6 +26,107 @@
533 offset-usb-charger = <1685>;
534 };
535
536+&i2c2 {
537+ pmic: pfuze100@08 {
538+ compatible = "fsl,pfuze100";
539+ reg = <0x08>;
540+
541+ regulators {
542+ sw1a_reg: sw1ab {
543+ regulator-min-microvolt = <300000>;
544+ regulator-max-microvolt = <1875000>;
545+ regulator-boot-on;
546+ regulator-always-on;
547+ regulator-ramp-delay = <6250>;
548+ };
549+
550+ sw1c_reg: sw1c {
551+ regulator-min-microvolt = <300000>;
552+ regulator-max-microvolt = <1875000>;
553+ regulator-boot-on;
554+ regulator-always-on;
555+ regulator-ramp-delay = <6250>;
556+ };
557+
558+ sw2_reg: sw2 {
559+ regulator-min-microvolt = <800000>;
560+ regulator-max-microvolt = <3300000>;
561+ regulator-boot-on;
562+ regulator-always-on;
563+ };
564+
565+ sw3a_reg: sw3a {
566+ regulator-min-microvolt = <400000>;
567+ regulator-max-microvolt = <1975000>;
568+ regulator-boot-on;
569+ regulator-always-on;
570+ };
571+
572+ sw3b_reg: sw3b {
573+ regulator-min-microvolt = <400000>;
574+ regulator-max-microvolt = <1975000>;
575+ regulator-boot-on;
576+ regulator-always-on;
577+ };
578+
579+ sw4_reg: sw4 {
580+ regulator-min-microvolt = <800000>;
581+ regulator-max-microvolt = <3300000>;
582+ };
583+
584+ swbst_reg: swbst {
585+ regulator-min-microvolt = <5000000>;
586+ regulator-max-microvolt = <5150000>;
587+ };
588+
589+ snvs_reg: vsnvs {
590+ regulator-min-microvolt = <1000000>;
591+ regulator-max-microvolt = <3000000>;
592+ regulator-boot-on;
593+ regulator-always-on;
594+ };
595+
596+ vref_reg: vrefddr {
597+ regulator-boot-on;
598+ regulator-always-on;
599+ };
600+
601+ vgen1_reg: vgen1 {
602+ regulator-min-microvolt = <800000>;
603+ regulator-max-microvolt = <1550000>;
604+ };
605+
606+ vgen2_reg: vgen2 {
607+ regulator-min-microvolt = <800000>;
608+ regulator-max-microvolt = <1550000>;
609+ };
610+
611+ vgen3_reg: vgen3 {
612+ regulator-min-microvolt = <1800000>;
613+ regulator-max-microvolt = <3300000>;
614+ };
615+
616+ vgen4_reg: vgen4 {
617+ regulator-min-microvolt = <1800000>;
618+ regulator-max-microvolt = <3300000>;
619+ regulator-always-on;
620+ };
621+
622+ vgen5_reg: vgen5 {
623+ regulator-min-microvolt = <1800000>;
624+ regulator-max-microvolt = <3300000>;
625+ regulator-always-on;
626+ };
627+
628+ vgen6_reg: vgen6 {
629+ regulator-min-microvolt = <1800000>;
630+ regulator-max-microvolt = <3300000>;
631+ regulator-always-on;
632+ };
633+ };
634+ };
635+};
636+
637 &mxcfb1 {
638 status = "okay";
639 };
640diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
641index 66b6145..5d774e5 100644
642--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
643+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
644@@ -405,105 +405,6 @@
645 mclk_source = <0>;
646 };
647
648- pmic: pfuze100@08 {
649- compatible = "fsl,pfuze100";
650- reg = <0x08>;
651-
652- regulators {
653- sw1a_reg: sw1ab {
654- regulator-min-microvolt = <300000>;
655- regulator-max-microvolt = <1875000>;
656- regulator-boot-on;
657- regulator-always-on;
658- regulator-ramp-delay = <6250>;
659- };
660-
661- sw1c_reg: sw1c {
662- regulator-min-microvolt = <300000>;
663- regulator-max-microvolt = <1875000>;
664- regulator-boot-on;
665- regulator-always-on;
666- regulator-ramp-delay = <6250>;
667- };
668-
669- sw2_reg: sw2 {
670- regulator-min-microvolt = <800000>;
671- regulator-max-microvolt = <3300000>;
672- regulator-boot-on;
673- regulator-always-on;
674- };
675-
676- sw3a_reg: sw3a {
677- regulator-min-microvolt = <400000>;
678- regulator-max-microvolt = <1975000>;
679- regulator-boot-on;
680- regulator-always-on;
681- };
682-
683- sw3b_reg: sw3b {
684- regulator-min-microvolt = <400000>;
685- regulator-max-microvolt = <1975000>;
686- regulator-boot-on;
687- regulator-always-on;
688- };
689-
690- sw4_reg: sw4 {
691- regulator-min-microvolt = <800000>;
692- regulator-max-microvolt = <3300000>;
693- };
694-
695- swbst_reg: swbst {
696- regulator-min-microvolt = <5000000>;
697- regulator-max-microvolt = <5150000>;
698- };
699-
700- snvs_reg: vsnvs {
701- regulator-min-microvolt = <1000000>;
702- regulator-max-microvolt = <3000000>;
703- regulator-boot-on;
704- regulator-always-on;
705- };
706-
707- vref_reg: vrefddr {
708- regulator-boot-on;
709- regulator-always-on;
710- };
711-
712- vgen1_reg: vgen1 {
713- regulator-min-microvolt = <800000>;
714- regulator-max-microvolt = <1550000>;
715- };
716-
717- vgen2_reg: vgen2 {
718- regulator-min-microvolt = <800000>;
719- regulator-max-microvolt = <1550000>;
720- };
721-
722- vgen3_reg: vgen3 {
723- regulator-min-microvolt = <1800000>;
724- regulator-max-microvolt = <3300000>;
725- };
726-
727- vgen4_reg: vgen4 {
728- regulator-min-microvolt = <1800000>;
729- regulator-max-microvolt = <3300000>;
730- regulator-always-on;
731- };
732-
733- vgen5_reg: vgen5 {
734- regulator-min-microvolt = <1800000>;
735- regulator-max-microvolt = <3300000>;
736- regulator-always-on;
737- };
738-
739- vgen6_reg: vgen6 {
740- regulator-min-microvolt = <1800000>;
741- regulator-max-microvolt = <3300000>;
742- regulator-always-on;
743- };
744- };
745- };
746-
747 egalax_ts@04 {
748 compatible = "eeti,egalax_ts";
749 reg = <0x04>;
750--
7512.1.0
752
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0009-ENGR00301078-2-ARM-dts-imx6sl-evk-add-support-for-pf.patch b/recipes-kernel/linux/linux-imx-3.10.17/0009-ENGR00301078-2-ARM-dts-imx6sl-evk-add-support-for-pf.patch
new file mode 100644
index 0000000..326e0a7
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0009-ENGR00301078-2-ARM-dts-imx6sl-evk-add-support-for-pf.patch
@@ -0,0 +1,1202 @@
1From 3082ee40d024412e8c275f1945e4a06a638e81bb Mon Sep 17 00:00:00 2001
2From: Robin Gong <b38343@freescale.com>
3Date: Thu, 6 Mar 2014 19:36:02 +0800
4Subject: [PATCH 09/10] ENGR00301078-2: ARM: dts: imx6sl-evk: add support for
5 pfuze200 on imx6sl-evk
6Organization: O.S. Systems Software LTDA.
7
8move pmic device node from imx6sl-evk.dtsi to upper-level, and add
9another layer on imx6sl-evk to diff pfuze100 or pfuze200. Meanwhile
10only works in ldo-enable mode if using pfuze200, since 'SW1C' switch
11regulator is cut for cost-down which means VDDARM_IN and VDDSOC_IN have
12to share the same switch regulator
13
14Signed-off-by: Robin Gong <b38343@freescale.com>
15
16Upstream-Status: Pending
17---
18 arch/arm/boot/dts/Makefile | 1 +
19 arch/arm/boot/dts/imx6sl-evk-common.dtsi | 504 +++++++++++++++++++++++++++++++
20 arch/arm/boot/dts/imx6sl-evk-pf200.dts | 122 ++++++++
21 arch/arm/boot/dts/imx6sl-evk.dts | 497 +-----------------------------
22 4 files changed, 630 insertions(+), 494 deletions(-)
23 create mode 100644 arch/arm/boot/dts/imx6sl-evk-common.dtsi
24 create mode 100644 arch/arm/boot/dts/imx6sl-evk-pf200.dts
25
26diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
27index c744cda..c5f9a19 100644
28--- a/arch/arm/boot/dts/Makefile
29+++ b/arch/arm/boot/dts/Makefile
30@@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
31 imx6sl-evk.dtb \
32 imx6sl-evk-csi.dtb \
33 imx6sl-evk-ldo.dtb \
34+ imx6sl-evk-pf200.dtb \
35 vf610-twr.dtb
36 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
37 imx23-olinuxino.dtb \
38diff --git a/arch/arm/boot/dts/imx6sl-evk-common.dtsi b/arch/arm/boot/dts/imx6sl-evk-common.dtsi
39new file mode 100644
40index 0000000..a1a3969
41--- /dev/null
42+++ b/arch/arm/boot/dts/imx6sl-evk-common.dtsi
43@@ -0,0 +1,504 @@
44+/*
45+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
46+ *
47+ * This program is free software; you can redistribute it and/or modify
48+ * it under the terms of the GNU General Public License version 2 as
49+ * published by the Free Software Foundation.
50+ */
51+
52+/ {
53+ memory {
54+ reg = <0x80000000 0x40000000>;
55+ };
56+
57+ battery: max8903@0 {
58+ compatible = "fsl,max8903-charger";
59+ pinctrl-names = "default";
60+ dok_input = <&gpio4 13 1>;
61+ uok_input = <&gpio4 13 1>;
62+ chg_input = <&gpio4 15 1>;
63+ flt_input = <&gpio4 14 1>;
64+ fsl,dcm_always_high;
65+ fsl,dc_valid;
66+ fsl,adc_disable;
67+ status = "okay";
68+ };
69+
70+ regulators {
71+ compatible = "simple-bus";
72+
73+ reg_lcd_3v3: lcd-3v3 {
74+ compatible = "regulator-fixed";
75+ regulator-name = "lcd-3v3";
76+ gpio = <&gpio4 3 0>;
77+ enable-active-high;
78+ };
79+
80+ reg_aud3v: wm8962_supply_3v15 {
81+ compatible = "regulator-fixed";
82+ regulator-name = "wm8962-supply-3v15";
83+ regulator-min-microvolt = <3150000>;
84+ regulator-max-microvolt = <3150000>;
85+ regulator-boot-on;
86+ };
87+
88+ reg_aud4v: wm8962_supply_4v2 {
89+ compatible = "regulator-fixed";
90+ regulator-name = "wm8962-supply-4v2";
91+ regulator-min-microvolt = <4325000>;
92+ regulator-max-microvolt = <4325000>;
93+ regulator-boot-on;
94+ };
95+
96+ reg_usb_otg1_vbus: usb_otg1_vbus {
97+ compatible = "regulator-fixed";
98+ regulator-name = "usb_otg1_vbus";
99+ regulator-min-microvolt = <5000000>;
100+ regulator-max-microvolt = <5000000>;
101+ gpio = <&gpio4 0 0>;
102+ enable-active-high;
103+ };
104+
105+ reg_usb_otg2_vbus: usb_otg2_vbus {
106+ compatible = "regulator-fixed";
107+ regulator-name = "usb_otg2_vbus";
108+ regulator-min-microvolt = <5000000>;
109+ regulator-max-microvolt = <5000000>;
110+ gpio = <&gpio4 2 0>;
111+ enable-active-high;
112+ };
113+ };
114+
115+ backlight {
116+ compatible = "pwm-backlight";
117+ pwms = <&pwm1 0 5000000>;
118+ brightness-levels = <0 4 8 16 32 64 128 255>;
119+ default-brightness-level = <6>;
120+ };
121+
122+ csi_v4l2_cap {
123+ compatible = "fsl,imx6sl-csi-v4l2";
124+ status = "disabled";
125+ };
126+
127+ pxp_v4l2_out {
128+ compatible = "fsl,imx6sl-pxp-v4l2";
129+ status = "okay";
130+ };
131+
132+ sound {
133+ compatible = "fsl,imx6q-sabresd-wm8962",
134+ "fsl,imx-audio-wm8962";
135+ model = "wm8962-audio";
136+ ssi-controller = <&ssi2>;
137+ audio-codec = <&codec>;
138+ audio-routing =
139+ "Headphone Jack", "HPOUTL",
140+ "Headphone Jack", "HPOUTR",
141+ "Ext Spk", "SPKOUTL",
142+ "Ext Spk", "SPKOUTR",
143+ "AMIC", "MICBIAS",
144+ "IN3R", "AMIC";
145+ amic-mono;
146+ mux-int-port = <2>;
147+ mux-ext-port = <3>;
148+ hp-det-gpios = <&gpio4 19 1>;
149+ };
150+
151+ sound-spdif {
152+ compatible = "fsl,imx-audio-spdif",
153+ "fsl,imx6sl-evk-spdif";
154+ model = "imx-spdif";
155+ spdif-controller = <&spdif>;
156+ spdif-out;
157+ };
158+
159+ sii902x_reset: sii902x-reset {
160+ compatible = "gpio-reset";
161+ reset-gpios = <&gpio2 19 1>;
162+ reset-delay-us = <100000>;
163+ #reset-cells = <0>;
164+ };
165+};
166+
167+&audmux {
168+ pinctrl-names = "default";
169+ pinctrl-0 = <&pinctrl_audmux_1>;
170+ status = "okay";
171+};
172+
173+&csi {
174+ status = "disabled";
175+};
176+
177+&ecspi1 {
178+ fsl,spi-num-chipselects = <1>;
179+ cs-gpios = <&gpio4 11 0>;
180+ pinctrl-names = "default";
181+ pinctrl-0 = <&pinctrl_ecspi1_1>;
182+ status = "okay";
183+
184+ flash: m25p80@0 {
185+ #address-cells = <1>;
186+ #size-cells = <1>;
187+ compatible = "st,m25p32";
188+ spi-max-frequency = <20000000>;
189+ reg = <0>;
190+ };
191+};
192+
193+&epdc {
194+ pinctrl-names = "default";
195+ pinctrl-0 = <&pinctrl_epdc_0>;
196+ V3P3-supply = <&V3P3_reg>;
197+ VCOM-supply = <&VCOM_reg>;
198+ DISPLAY-supply = <&DISPLAY_reg>;
199+ status = "okay";
200+};
201+
202+&cpu0 {
203+ arm-supply = <&sw1a_reg>;
204+ soc-supply = <&sw1c_reg>;
205+ pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
206+};
207+
208+&fec {
209+ pinctrl-names = "default", "sleep";
210+ pinctrl-0 = <&pinctrl_fec_1>;
211+ pinctrl-1 = <&pinctrl_fec_1_sleep>;
212+ phy-mode = "rmii";
213+ phy-reset-gpios = <&gpio4 21 0>; /* GPIO4_21 */
214+ phy-reset-duration = <1>;
215+ status = "okay";
216+};
217+
218+&gpc {
219+ fsl,cpu_pupscr_sw2iso = <0xf>;
220+ fsl,cpu_pupscr_sw = <0xf>;
221+ fsl,cpu_pdnscr_iso2sw = <0x1>;
222+ fsl,cpu_pdnscr_iso = <0x1>;
223+ fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
224+ fsl,wdog-reset = <1>; /* watchdog select of reset source */
225+ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
226+};
227+
228+&gpu {
229+ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
230+};
231+
232+&i2c1 {
233+ clock-frequency = <100000>;
234+ pinctrl-names = "default";
235+ pinctrl-0 = <&pinctrl_i2c1_1>;
236+ status = "okay";
237+
238+ elan@10 {
239+ compatible = "elan,elan-touch";
240+ reg = <0x10>;
241+ interrupt-parent = <&gpio2>;
242+ interrupts = <10 2>;
243+ gpio_elan_cs = <&gpio2 9 0>;
244+ gpio_elan_rst = <&gpio4 4 0>;
245+ gpio_intr = <&gpio2 10 0>;
246+ status = "okay";
247+ };
248+
249+ max17135@48 {
250+ compatible = "maxim,max17135";
251+ reg = <0x48>;
252+ vneg_pwrup = <1>;
253+ gvee_pwrup = <2>;
254+ vpos_pwrup = <10>;
255+ gvdd_pwrup = <12>;
256+ gvdd_pwrdn = <1>;
257+ vpos_pwrdn = <2>;
258+ gvee_pwrdn = <8>;
259+ vneg_pwrdn = <10>;
260+ gpio_pmic_pwrgood = <&gpio2 13 0>;
261+ gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
262+ gpio_pmic_wakeup = <&gpio2 14 0>;
263+ gpio_pmic_v3p3 = <&gpio2 7 0>;
264+ gpio_pmic_intr = <&gpio2 12 0>;
265+
266+ regulators {
267+ DISPLAY_reg: DISPLAY {
268+ regulator-name = "DISPLAY";
269+ };
270+
271+ GVDD_reg: GVDD {
272+ /* 20v */
273+ regulator-name = "GVDD";
274+ };
275+
276+ GVEE_reg: GVEE {
277+ /* -22v */
278+ regulator-name = "GVEE";
279+ };
280+
281+ HVINN_reg: HVINN {
282+ /* -22v */
283+ regulator-name = "HVINN";
284+ };
285+
286+ HVINP_reg: HVINP {
287+ /* 20v */
288+ regulator-name = "HVINP";
289+ };
290+
291+ VCOM_reg: VCOM {
292+ regulator-name = "VCOM";
293+ /* 2's-compliment, -4325000 */
294+ regulator-min-microvolt = <0xffbe0178>;
295+ /* 2's-compliment, -500000 */
296+ regulator-max-microvolt = <0xfff85ee0>;
297+ };
298+
299+ VNEG_reg: VNEG {
300+ /* -15v */
301+ regulator-name = "VNEG";
302+ };
303+
304+ VPOS_reg: VPOS {
305+ /* 15v */
306+ regulator-name = "VPOS";
307+ };
308+
309+ V3P3_reg: V3P3 {
310+ regulator-name = "V3P3";
311+ };
312+ };
313+ };
314+
315+ mma8450@1c {
316+ compatible = "fsl,mma8450";
317+ reg = <0x1c>;
318+ };
319+};
320+
321+&i2c2 {
322+ clock-frequency = <100000>;
323+ pinctrl-names = "default";
324+ pinctrl-0 = <&pinctrl_i2c2_1>;
325+ status = "okay";
326+
327+ codec: wm8962@1a {
328+ compatible = "wlf,wm8962";
329+ reg = <0x1a>;
330+ clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
331+ DCVDD-supply = <&vgen3_reg>;
332+ DBVDD-supply = <&reg_aud3v>;
333+ AVDD-supply = <&vgen3_reg>;
334+ CPVDD-supply = <&vgen3_reg>;
335+ MICVDD-supply = <&reg_aud3v>;
336+ PLLVDD-supply = <&vgen3_reg>;
337+ SPKVDD1-supply = <&reg_aud4v>;
338+ SPKVDD2-supply = <&reg_aud4v>;
339+ amic-mono;
340+ };
341+
342+ sii902x@39 {
343+ compatible = "SiI,sii902x";
344+ interrupt-parent = <&gpio2>;
345+ interrupts = <10 2>;
346+ mode_str ="1280x720M@60";
347+ bits-per-pixel = <32>;
348+ resets = <&sii902x_reset>;
349+ reg = <0x39>;
350+ };
351+};
352+
353+&i2c3 {
354+ clock-frequency = <100000>;
355+ pinctrl-names = "default";
356+ pinctrl-0 = <&pinctrl_i2c3_1>;
357+ status = "disabled";
358+
359+ ov564x: ov564x@3c {
360+ compatible = "ovti,ov564x";
361+ reg = <0x3c>;
362+ pinctrl-names = "default";
363+ pinctrl-0 = <&pinctrl_csi_0>;
364+ clocks = <&clks IMX6SL_CLK_CSI>;
365+ clock-names = "csi_mclk";
366+ AVDD-supply = <&vgen6_reg>; /* 2.8v */
367+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
368+ pwn-gpios = <&gpio1 25 1>;
369+ rst-gpios = <&gpio1 26 0>;
370+ csi_id = <0>;
371+ mclk = <24000000>;
372+ mclk_source = <0>;
373+ };
374+};
375+
376+&iomuxc {
377+ pinctrl-names = "default", "sleep";
378+ pinctrl-0 = <&pinctrl_hog>;
379+ pinctrl-1 = <&pinctrl_hog_sleep>;
380+
381+ hog {
382+ pinctrl_hog: hoggrp {
383+ fsl,pins = <
384+ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
385+ MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
386+ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
387+ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
388+ MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
389+ MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x80000000
390+ MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x110b0
391+ MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000
392+ MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x80000000
393+ MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x80000000
394+ MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x80000000
395+ MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x80000000
396+ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x170b0
397+ MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
398+ MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
399+ MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
400+ MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
401+ MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
402+ MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
403+ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0
404+ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
405+ MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
406+ >;
407+ };
408+
409+ pinctrl_hog_sleep: hoggrp_sleep {
410+ fsl,pins = <
411+ MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x3080
412+ MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x3080
413+ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x3080
414+ >;
415+ };
416+ };
417+};
418+
419+&kpp {
420+ pinctrl-names = "default", "sleep";
421+ pinctrl-0 = <&pinctrl_kpp_1>;
422+ pinctrl-1 = <&pinctrl_kpp_1_sleep>;
423+ linux,keymap = <
424+ 0x00000067 /* KEY_UP */
425+ 0x0001006c /* KEY_DOWN */
426+ 0x0002001c /* KEY_ENTER */
427+ 0x01000066 /* KEY_HOME */
428+ 0x0101006a /* KEY_RIGHT */
429+ 0x01020069 /* KEY_LEFT */
430+ 0x02000072 /* KEY_VOLUMEDOWN */
431+ 0x02010073 /* KEY_VOLUMEUP */
432+ >;
433+ status = "okay";
434+};
435+
436+&lcdif {
437+ pinctrl-names = "default";
438+ pinctrl-0 = <&pinctrl_lcdif_dat_0
439+ &pinctrl_lcdif_ctrl_0>;
440+ lcd-supply = <&reg_lcd_3v3>;
441+ display = <&display>;
442+ status = "okay";
443+
444+ display: display {
445+ bits-per-pixel = <16>;
446+ bus-width = <24>;
447+
448+ display-timings {
449+ native-mode = <&timing0>;
450+ timing0: timing0 {
451+ clock-frequency = <33500000>;
452+ hactive = <800>;
453+ vactive = <480>;
454+ hback-porch = <89>;
455+ hfront-porch = <164>;
456+ vback-porch = <23>;
457+ vfront-porch = <10>;
458+ hsync-len = <10>;
459+ vsync-len = <10>;
460+ hsync-active = <0>;
461+ vsync-active = <0>;
462+ de-active = <1>;
463+ pixelclk-active = <0>;
464+ };
465+ };
466+ };
467+};
468+
469+&pwm1 {
470+ pinctrl-names = "default", "sleep";
471+ pinctrl-0 = <&pinctrl_pwm1_0>;
472+ pinctrl-1 = <&pinctrl_pwm1_0_sleep>;
473+ status = "okay";
474+};
475+
476+&pxp {
477+ status = "okay";
478+};
479+
480+&spdif {
481+ pinctrl-names = "default";
482+ pinctrl-0 = <&pinctrl_spdif_1>;
483+ status = "okay";
484+};
485+
486+&ssi2 {
487+ fsl,mode = "i2s-slave";
488+ status = "okay";
489+};
490+
491+&uart1 {
492+ pinctrl-names = "default";
493+ pinctrl-0 = <&pinctrl_uart1_1>;
494+ status = "okay";
495+};
496+
497+&usbotg1 {
498+ vbus-supply = <&reg_usb_otg1_vbus>;
499+ pinctrl-names = "default";
500+ pinctrl-0 = <&pinctrl_usbotg1_1>;
501+ disable-over-current;
502+ imx6-usb-charger-detection;
503+ status = "okay";
504+};
505+
506+&usbotg2 {
507+ vbus-supply = <&reg_usb_otg2_vbus>;
508+ dr_mode = "host";
509+ disable-over-current;
510+ status = "okay";
511+};
512+
513+&usdhc1 {
514+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
515+ pinctrl-0 = <&pinctrl_usdhc1_1>;
516+ pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
517+ pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
518+ bus-width = <8>;
519+ cd-gpios = <&gpio4 7 0>;
520+ wp-gpios = <&gpio4 6 0>;
521+ keep-power-in-suspend;
522+ enable-sdio-wakeup;
523+ status = "okay";
524+};
525+
526+&usdhc2 {
527+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
528+ pinctrl-0 = <&pinctrl_usdhc2_1>;
529+ pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
530+ pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
531+ cd-gpios = <&gpio5 0 0>;
532+ wp-gpios = <&gpio4 29 0>;
533+ keep-power-in-suspend;
534+ enable-sdio-wakeup;
535+ status = "okay";
536+};
537+
538+&usdhc3 {
539+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
540+ pinctrl-0 = <&pinctrl_usdhc3_1>;
541+ pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
542+ pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
543+ cd-gpios = <&gpio3 22 0>;
544+ keep-power-in-suspend;
545+ enable-sdio-wakeup;
546+ status = "okay";
547+};
548diff --git a/arch/arm/boot/dts/imx6sl-evk-pf200.dts b/arch/arm/boot/dts/imx6sl-evk-pf200.dts
549new file mode 100644
550index 0000000..55d3081
551--- /dev/null
552+++ b/arch/arm/boot/dts/imx6sl-evk-pf200.dts
553@@ -0,0 +1,122 @@
554+/*
555+ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
556+ *
557+ * This program is free software; you can redistribute it and/or modify
558+ * it under the terms of the GNU General Public License version 2 as
559+ * published by the Free Software Foundation.
560+ */
561+
562+/dts-v1/;
563+
564+#include "imx6sl.dtsi"
565+#include "imx6sl-evk-common.dtsi"
566+
567+/ {
568+ model = "Freescale i.MX6 SoloLite EVK Board(PFUZE200)";
569+ compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
570+};
571+
572+&cpu0 {
573+ arm-supply = <&reg_arm>;
574+ soc-supply = <&reg_soc>;
575+ pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */
576+};
577+
578+&gpc {
579+ fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */
580+ fsl,wdog-reset = <1>; /* watchdog select of reset source */
581+ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
582+};
583+
584+&gpu {
585+ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
586+};
587+
588+&i2c1 {
589+ pmic: pfuze200@08 {
590+ compatible = "fsl,pfuze200";
591+ reg = <0x08>;
592+
593+ regulators {
594+ sw1a_reg: sw1ab {
595+ regulator-min-microvolt = <300000>;
596+ regulator-max-microvolt = <1875000>;
597+ regulator-boot-on;
598+ regulator-always-on;
599+ regulator-ramp-delay = <6250>;
600+ };
601+
602+ sw2_reg: sw2 {
603+ regulator-min-microvolt = <800000>;
604+ regulator-max-microvolt = <3300000>;
605+ regulator-boot-on;
606+ regulator-always-on;
607+ };
608+
609+ sw3a_reg: sw3a {
610+ regulator-min-microvolt = <400000>;
611+ regulator-max-microvolt = <1975000>;
612+ regulator-boot-on;
613+ regulator-always-on;
614+ };
615+
616+ sw3b_reg: sw3b {
617+ regulator-min-microvolt = <400000>;
618+ regulator-max-microvolt = <1975000>;
619+ regulator-boot-on;
620+ regulator-always-on;
621+ };
622+
623+ swbst_reg: swbst {
624+ regulator-min-microvolt = <5000000>;
625+ regulator-max-microvolt = <5150000>;
626+ };
627+
628+ snvs_reg: vsnvs {
629+ regulator-min-microvolt = <1000000>;
630+ regulator-max-microvolt = <3000000>;
631+ regulator-boot-on;
632+ regulator-always-on;
633+ };
634+
635+ vref_reg: vrefddr {
636+ regulator-boot-on;
637+ regulator-always-on;
638+ };
639+
640+ vgen1_reg: vgen1 {
641+ regulator-min-microvolt = <800000>;
642+ regulator-max-microvolt = <1550000>;
643+ };
644+
645+ vgen2_reg: vgen2 {
646+ regulator-min-microvolt = <800000>;
647+ regulator-max-microvolt = <1550000>;
648+ };
649+
650+ vgen3_reg: vgen3 {
651+ regulator-min-microvolt = <1800000>;
652+ regulator-max-microvolt = <3300000>;
653+ regulator-always-on;
654+ };
655+
656+ vgen4_reg: vgen4 {
657+ regulator-min-microvolt = <1800000>;
658+ regulator-max-microvolt = <3300000>;
659+ regulator-always-on;
660+ };
661+
662+ vgen5_reg: vgen5 {
663+ regulator-min-microvolt = <1800000>;
664+ regulator-max-microvolt = <3300000>;
665+ regulator-always-on;
666+ };
667+
668+ vgen6_reg: vgen6 {
669+ regulator-min-microvolt = <1800000>;
670+ regulator-max-microvolt = <3300000>;
671+ regulator-always-on;
672+ };
673+ };
674+ };
675+};
676diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
677index 4966f38..ed0ce89 100644
678--- a/arch/arm/boot/dts/imx6sl-evk.dts
679+++ b/arch/arm/boot/dts/imx6sl-evk.dts
680@@ -1,5 +1,5 @@
681 /*
682- * Copyright (C) 2013 Freescale Semiconductor, Inc.
683+ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
684 *
685 * This program is free software; you can redistribute it and/or modify
686 * it under the terms of the GNU General Public License version 2 as
687@@ -9,195 +9,14 @@
688 /dts-v1/;
689
690 #include "imx6sl.dtsi"
691+#include "imx6sl-evk-common.dtsi"
692
693 / {
694- model = "Freescale i.MX6 SoloLite EVK Board";
695+ model = "Freescale i.MX6 SoloLite EVK Board(PFUZE100)";
696 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
697-
698- memory {
699- reg = <0x80000000 0x40000000>;
700- };
701-
702- battery: max8903@0 {
703- compatible = "fsl,max8903-charger";
704- pinctrl-names = "default";
705- dok_input = <&gpio4 13 1>;
706- uok_input = <&gpio4 13 1>;
707- chg_input = <&gpio4 15 1>;
708- flt_input = <&gpio4 14 1>;
709- fsl,dcm_always_high;
710- fsl,dc_valid;
711- fsl,adc_disable;
712- status = "okay";
713- };
714- regulators {
715- compatible = "simple-bus";
716-
717- reg_lcd_3v3: lcd-3v3 {
718- compatible = "regulator-fixed";
719- regulator-name = "lcd-3v3";
720- gpio = <&gpio4 3 0>;
721- enable-active-high;
722- };
723-
724- reg_aud3v: wm8962_supply_3v15 {
725- compatible = "regulator-fixed";
726- regulator-name = "wm8962-supply-3v15";
727- regulator-min-microvolt = <3150000>;
728- regulator-max-microvolt = <3150000>;
729- regulator-boot-on;
730- };
731-
732- reg_aud4v: wm8962_supply_4v2 {
733- compatible = "regulator-fixed";
734- regulator-name = "wm8962-supply-4v2";
735- regulator-min-microvolt = <4325000>;
736- regulator-max-microvolt = <4325000>;
737- regulator-boot-on;
738- };
739-
740- reg_usb_otg1_vbus: usb_otg1_vbus {
741- compatible = "regulator-fixed";
742- regulator-name = "usb_otg1_vbus";
743- regulator-min-microvolt = <5000000>;
744- regulator-max-microvolt = <5000000>;
745- gpio = <&gpio4 0 0>;
746- enable-active-high;
747- };
748-
749- reg_usb_otg2_vbus: usb_otg2_vbus {
750- compatible = "regulator-fixed";
751- regulator-name = "usb_otg2_vbus";
752- regulator-min-microvolt = <5000000>;
753- regulator-max-microvolt = <5000000>;
754- gpio = <&gpio4 2 0>;
755- enable-active-high;
756- };
757- };
758-
759- backlight {
760- compatible = "pwm-backlight";
761- pwms = <&pwm1 0 5000000>;
762- brightness-levels = <0 4 8 16 32 64 128 255>;
763- default-brightness-level = <6>;
764- };
765-
766- csi_v4l2_cap {
767- compatible = "fsl,imx6sl-csi-v4l2";
768- status = "disabled";
769- };
770-
771- pxp_v4l2_out {
772- compatible = "fsl,imx6sl-pxp-v4l2";
773- status = "okay";
774- };
775-
776- sound {
777- compatible = "fsl,imx6q-sabresd-wm8962",
778- "fsl,imx-audio-wm8962";
779- model = "wm8962-audio";
780- ssi-controller = <&ssi2>;
781- audio-codec = <&codec>;
782- audio-routing =
783- "Headphone Jack", "HPOUTL",
784- "Headphone Jack", "HPOUTR",
785- "Ext Spk", "SPKOUTL",
786- "Ext Spk", "SPKOUTR",
787- "AMIC", "MICBIAS",
788- "IN3R", "AMIC";
789- amic-mono;
790- mux-int-port = <2>;
791- mux-ext-port = <3>;
792- hp-det-gpios = <&gpio4 19 1>;
793- };
794-
795- sound-spdif {
796- compatible = "fsl,imx-audio-spdif",
797- "fsl,imx6sl-evk-spdif";
798- model = "imx-spdif";
799- spdif-controller = <&spdif>;
800- spdif-out;
801- };
802-
803- sii902x_reset: sii902x-reset {
804- compatible = "gpio-reset";
805- reset-gpios = <&gpio2 19 1>;
806- reset-delay-us = <100000>;
807- #reset-cells = <0>;
808- };
809-};
810-
811-&audmux {
812- pinctrl-names = "default";
813- pinctrl-0 = <&pinctrl_audmux_1>;
814- status = "okay";
815-};
816-
817-&csi {
818- status = "disabled";
819-};
820-
821-&ecspi1 {
822- fsl,spi-num-chipselects = <1>;
823- cs-gpios = <&gpio4 11 0>;
824- pinctrl-names = "default";
825- pinctrl-0 = <&pinctrl_ecspi1_1>;
826- status = "okay";
827-
828- flash: m25p80@0 {
829- #address-cells = <1>;
830- #size-cells = <1>;
831- compatible = "st,m25p32";
832- spi-max-frequency = <20000000>;
833- reg = <0>;
834- };
835-};
836-
837-&epdc {
838- pinctrl-names = "default";
839- pinctrl-0 = <&pinctrl_epdc_0>;
840- V3P3-supply = <&V3P3_reg>;
841- VCOM-supply = <&VCOM_reg>;
842- DISPLAY-supply = <&DISPLAY_reg>;
843- status = "okay";
844-};
845-
846-&cpu0 {
847- arm-supply = <&sw1a_reg>;
848- soc-supply = <&sw1c_reg>;
849- pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
850-};
851-
852-&fec {
853- pinctrl-names = "default", "sleep";
854- pinctrl-0 = <&pinctrl_fec_1>;
855- pinctrl-1 = <&pinctrl_fec_1_sleep>;
856- phy-mode = "rmii";
857- phy-reset-gpios = <&gpio4 21 0>; /* GPIO4_21 */
858- phy-reset-duration = <1>;
859- status = "okay";
860-};
861-
862-&gpc {
863- fsl,cpu_pupscr_sw2iso = <0xf>;
864- fsl,cpu_pupscr_sw = <0xf>;
865- fsl,cpu_pdnscr_iso2sw = <0x1>;
866- fsl,cpu_pdnscr_iso = <0x1>;
867- fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
868- fsl,wdog-reset = <1>; /* watchdog select of reset source */
869- pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
870-};
871-
872-&gpu {
873- pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
874 };
875
876 &i2c1 {
877- clock-frequency = <100000>;
878- pinctrl-names = "default";
879- pinctrl-0 = <&pinctrl_i2c1_1>;
880- status = "okay";
881-
882 pmic: pfuze100@08 {
883 compatible = "fsl,pfuze100";
884 reg = <0x08>;
885@@ -297,314 +116,4 @@
886 };
887 };
888 };
889-
890- elan@10 {
891- compatible = "elan,elan-touch";
892- reg = <0x10>;
893- interrupt-parent = <&gpio2>;
894- interrupts = <10 2>;
895- gpio_elan_cs = <&gpio2 9 0>;
896- gpio_elan_rst = <&gpio4 4 0>;
897- gpio_intr = <&gpio2 10 0>;
898- status = "okay";
899- };
900-
901- max17135@48 {
902- compatible = "maxim,max17135";
903- reg = <0x48>;
904- vneg_pwrup = <1>;
905- gvee_pwrup = <2>;
906- vpos_pwrup = <10>;
907- gvdd_pwrup = <12>;
908- gvdd_pwrdn = <1>;
909- vpos_pwrdn = <2>;
910- gvee_pwrdn = <8>;
911- vneg_pwrdn = <10>;
912- gpio_pmic_pwrgood = <&gpio2 13 0>;
913- gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
914- gpio_pmic_wakeup = <&gpio2 14 0>;
915- gpio_pmic_v3p3 = <&gpio2 7 0>;
916- gpio_pmic_intr = <&gpio2 12 0>;
917-
918- regulators {
919- DISPLAY_reg: DISPLAY {
920- regulator-name = "DISPLAY";
921- };
922-
923- GVDD_reg: GVDD {
924- /* 20v */
925- regulator-name = "GVDD";
926- };
927-
928- GVEE_reg: GVEE {
929- /* -22v */
930- regulator-name = "GVEE";
931- };
932-
933- HVINN_reg: HVINN {
934- /* -22v */
935- regulator-name = "HVINN";
936- };
937-
938- HVINP_reg: HVINP {
939- /* 20v */
940- regulator-name = "HVINP";
941- };
942-
943- VCOM_reg: VCOM {
944- regulator-name = "VCOM";
945- /* 2's-compliment, -4325000 */
946- regulator-min-microvolt = <0xffbe0178>;
947- /* 2's-compliment, -500000 */
948- regulator-max-microvolt = <0xfff85ee0>;
949- };
950-
951- VNEG_reg: VNEG {
952- /* -15v */
953- regulator-name = "VNEG";
954- };
955-
956- VPOS_reg: VPOS {
957- /* 15v */
958- regulator-name = "VPOS";
959- };
960-
961- V3P3_reg: V3P3 {
962- regulator-name = "V3P3";
963- };
964- };
965- };
966-
967- mma8450@1c {
968- compatible = "fsl,mma8450";
969- reg = <0x1c>;
970- };
971-};
972-
973-&i2c2 {
974- clock-frequency = <100000>;
975- pinctrl-names = "default";
976- pinctrl-0 = <&pinctrl_i2c2_1>;
977- status = "okay";
978-
979- codec: wm8962@1a {
980- compatible = "wlf,wm8962";
981- reg = <0x1a>;
982- clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
983- DCVDD-supply = <&vgen3_reg>;
984- DBVDD-supply = <&reg_aud3v>;
985- AVDD-supply = <&vgen3_reg>;
986- CPVDD-supply = <&vgen3_reg>;
987- MICVDD-supply = <&reg_aud3v>;
988- PLLVDD-supply = <&vgen3_reg>;
989- SPKVDD1-supply = <&reg_aud4v>;
990- SPKVDD2-supply = <&reg_aud4v>;
991- amic-mono;
992- };
993-
994- sii902x@39 {
995- compatible = "SiI,sii902x";
996- interrupt-parent = <&gpio2>;
997- interrupts = <10 2>;
998- mode_str ="1280x720M@60";
999- bits-per-pixel = <32>;
1000- resets = <&sii902x_reset>;
1001- reg = <0x39>;
1002- };
1003-};
1004-
1005-&i2c3 {
1006- clock-frequency = <100000>;
1007- pinctrl-names = "default";
1008- pinctrl-0 = <&pinctrl_i2c3_1>;
1009- status = "disabled";
1010-
1011- ov564x: ov564x@3c {
1012- compatible = "ovti,ov564x";
1013- reg = <0x3c>;
1014- pinctrl-names = "default";
1015- pinctrl-0 = <&pinctrl_csi_0>;
1016- clocks = <&clks IMX6SL_CLK_CSI>;
1017- clock-names = "csi_mclk";
1018- AVDD-supply = <&vgen6_reg>; /* 2.8v */
1019- DVDD-supply = <&vgen2_reg>; /* 1.5v*/
1020- pwn-gpios = <&gpio1 25 1>;
1021- rst-gpios = <&gpio1 26 0>;
1022- csi_id = <0>;
1023- mclk = <24000000>;
1024- mclk_source = <0>;
1025- };
1026-};
1027-
1028-&iomuxc {
1029- pinctrl-names = "default", "sleep";
1030- pinctrl-0 = <&pinctrl_hog>;
1031- pinctrl-1 = <&pinctrl_hog_sleep>;
1032-
1033- hog {
1034- pinctrl_hog: hoggrp {
1035- fsl,pins = <
1036- MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
1037- MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
1038- MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
1039- MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
1040- MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
1041- MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x80000000
1042- MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x110b0
1043- MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000
1044- MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x80000000
1045- MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x80000000
1046- MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x80000000
1047- MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x80000000
1048- MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x170b0
1049- MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
1050- MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
1051- MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
1052- MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
1053- MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
1054- MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
1055- MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0
1056- MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
1057- MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
1058- >;
1059- };
1060-
1061- pinctrl_hog_sleep: hoggrp_sleep {
1062- fsl,pins = <
1063- MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x3080
1064- MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x3080
1065- MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x3080
1066- >;
1067- };
1068- };
1069-};
1070-
1071-&kpp {
1072- pinctrl-names = "default", "sleep";
1073- pinctrl-0 = <&pinctrl_kpp_1>;
1074- pinctrl-1 = <&pinctrl_kpp_1_sleep>;
1075- linux,keymap = <
1076- 0x00000067 /* KEY_UP */
1077- 0x0001006c /* KEY_DOWN */
1078- 0x0002001c /* KEY_ENTER */
1079- 0x01000066 /* KEY_HOME */
1080- 0x0101006a /* KEY_RIGHT */
1081- 0x01020069 /* KEY_LEFT */
1082- 0x02000072 /* KEY_VOLUMEDOWN */
1083- 0x02010073 /* KEY_VOLUMEUP */
1084- >;
1085- status = "okay";
1086-};
1087-
1088-&lcdif {
1089- pinctrl-names = "default";
1090- pinctrl-0 = <&pinctrl_lcdif_dat_0
1091- &pinctrl_lcdif_ctrl_0>;
1092- lcd-supply = <&reg_lcd_3v3>;
1093- display = <&display>;
1094- status = "okay";
1095-
1096- display: display {
1097- bits-per-pixel = <16>;
1098- bus-width = <24>;
1099-
1100- display-timings {
1101- native-mode = <&timing0>;
1102- timing0: timing0 {
1103- clock-frequency = <33500000>;
1104- hactive = <800>;
1105- vactive = <480>;
1106- hback-porch = <89>;
1107- hfront-porch = <164>;
1108- vback-porch = <23>;
1109- vfront-porch = <10>;
1110- hsync-len = <10>;
1111- vsync-len = <10>;
1112- hsync-active = <0>;
1113- vsync-active = <0>;
1114- de-active = <1>;
1115- pixelclk-active = <0>;
1116- };
1117- };
1118- };
1119-};
1120-
1121-&pwm1 {
1122- pinctrl-names = "default", "sleep";
1123- pinctrl-0 = <&pinctrl_pwm1_0>;
1124- pinctrl-1 = <&pinctrl_pwm1_0_sleep>;
1125- status = "okay";
1126-};
1127-
1128-&pxp {
1129- status = "okay";
1130-};
1131-
1132-&spdif {
1133- pinctrl-names = "default";
1134- pinctrl-0 = <&pinctrl_spdif_1>;
1135- status = "okay";
1136-};
1137-
1138-&ssi2 {
1139- fsl,mode = "i2s-slave";
1140- status = "okay";
1141-};
1142-
1143-&uart1 {
1144- pinctrl-names = "default";
1145- pinctrl-0 = <&pinctrl_uart1_1>;
1146- status = "okay";
1147-};
1148-
1149-&usbotg1 {
1150- vbus-supply = <&reg_usb_otg1_vbus>;
1151- pinctrl-names = "default";
1152- pinctrl-0 = <&pinctrl_usbotg1_1>;
1153- disable-over-current;
1154- imx6-usb-charger-detection;
1155- status = "okay";
1156-};
1157-
1158-&usbotg2 {
1159- vbus-supply = <&reg_usb_otg2_vbus>;
1160- dr_mode = "host";
1161- disable-over-current;
1162- status = "okay";
1163-};
1164-
1165-&usdhc1 {
1166- pinctrl-names = "default", "state_100mhz", "state_200mhz";
1167- pinctrl-0 = <&pinctrl_usdhc1_1>;
1168- pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
1169- pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
1170- bus-width = <8>;
1171- cd-gpios = <&gpio4 7 0>;
1172- wp-gpios = <&gpio4 6 0>;
1173- keep-power-in-suspend;
1174- enable-sdio-wakeup;
1175- status = "okay";
1176-};
1177-
1178-&usdhc2 {
1179- pinctrl-names = "default", "state_100mhz", "state_200mhz";
1180- pinctrl-0 = <&pinctrl_usdhc2_1>;
1181- pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
1182- pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
1183- cd-gpios = <&gpio5 0 0>;
1184- wp-gpios = <&gpio4 29 0>;
1185- keep-power-in-suspend;
1186- enable-sdio-wakeup;
1187- status = "okay";
1188-};
1189-
1190-&usdhc3 {
1191- pinctrl-names = "default", "state_100mhz", "state_200mhz";
1192- pinctrl-0 = <&pinctrl_usdhc3_1>;
1193- pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
1194- pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
1195- cd-gpios = <&gpio3 22 0>;
1196- keep-power-in-suspend;
1197- enable-sdio-wakeup;
1198- status = "okay";
1199 };
1200--
12012.1.0
1202
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0010-ENGR00318392-ARM-imx6x-Save-restore-SCU-and-some-CP1.patch b/recipes-kernel/linux/linux-imx-3.10.17/0010-ENGR00318392-ARM-imx6x-Save-restore-SCU-and-some-CP1.patch
new file mode 100644
index 0000000..4459576
--- /dev/null
+++ b/recipes-kernel/linux/linux-imx-3.10.17/0010-ENGR00318392-ARM-imx6x-Save-restore-SCU-and-some-CP1.patch
@@ -0,0 +1,133 @@
1From 4a46352d23f1f7b4f513487cb1701a8592ba980f Mon Sep 17 00:00:00 2001
2From: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
3Date: Fri, 13 Jun 2014 15:43:14 -0500
4Subject: [PATCH 10/10] ENGR00318392 ARM:imx6x: Save/restore SCU and some CP15
5 registers across suspend/resume
6Organization: O.S. Systems Software LTDA.
7
8This patch ensures that the SCU and certain A9 CP15 registers state are maintained across
9a suspend/resume cycle:
101. Need to ensure that SCU standby bit is set again after suspend/resume cycle, else
11the system will never WAIT mode after a suspend/resume cycle. This bit should be enabled
12on all SMP systems immaterial of whether CPUIDLE is enabled or not.
132. Several A9 errata workarounds involve setting bits in the ARM diagnostic register.
14Save/restore this register across a suspend/resume cycle.
153. Save and restore the A9 power control register also.
16
17Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
18(cherry picked from commit 7b5b4ef5b3cdc65c0576f87cfa52bcca1bda8b33)
19
20Upstream-Status: Pending
21---
22 arch/arm/mach-imx/cpuidle-imx6q.c | 5 +----
23 arch/arm/mach-imx/platsmp.c | 4 +++-
24 arch/arm/mach-imx/pm-imx6.c | 36 ++++++++++++++++++++++++++++++++++++
25 3 files changed, 40 insertions(+), 5 deletions(-)
26
27diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
28index d74d0ce..9ffbd34 100644
29--- a/arch/arm/mach-imx/cpuidle-imx6q.c
30+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
31@@ -1,5 +1,5 @@
32 /*
33- * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
34+ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
35 *
36 * This program is free software; you can redistribute it and/or modify
37 * it under the terms of the GNU General Public License version 2 as
38@@ -65,9 +65,6 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
39
40 int __init imx6q_cpuidle_init(void)
41 {
42- /* Need to enable SCU standby for entering WAIT modes */
43- imx_scu_standby_enable();
44-
45 /* Set cache lpm bit for reliable WAIT mode support */
46 imx6_set_cache_lpm_in_wait(true);
47
48diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
49index c6e1ab5..d2fa7ec 100644
50--- a/arch/arm/mach-imx/platsmp.c
51+++ b/arch/arm/mach-imx/platsmp.c
52@@ -1,5 +1,5 @@
53 /*
54- * Copyright 2011 Freescale Semiconductor, Inc.
55+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
56 * Copyright 2011 Linaro Ltd.
57 *
58 * The code contained herein is licensed under the GNU General Public
59@@ -77,6 +77,8 @@ static void __init imx_smp_init_cpus(void)
60 void imx_smp_prepare(void)
61 {
62 scu_enable(scu_base);
63+ /* Need to enable SCU standby for entering WAIT mode */
64+ imx_scu_standby_enable();
65 }
66
67 static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
68diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
69index de46b87..587cc7e 100644
70--- a/arch/arm/mach-imx/pm-imx6.c
71+++ b/arch/arm/mach-imx/pm-imx6.c
72@@ -73,6 +73,8 @@ static int (*suspend_in_iram_fn)(void *iram_vbase,
73 unsigned long iram_pbase, unsigned int cpu_type);
74 static unsigned int cpu_type;
75 static void __iomem *ccm_base;
76+static unsigned long dcr;
77+static unsigned long pcr;
78
79 unsigned long save_ttbr1(void)
80 {
81@@ -111,6 +113,34 @@ void imx6_set_cache_lpm_in_wait(bool enable)
82 }
83 }
84
85+static void imx6_save_cpu_arch_regs(void)
86+{
87+ /* Save the Diagnostic Control Register. */
88+ asm volatile(
89+ "mrc p15, 0, %0, c15, c0, 1\n"
90+ : "=r" (dcr)
91+ );
92+ /* Save the Power Control Register. */
93+ asm volatile(
94+ "mrc p15, 0, %0, c15, c0, 0\n"
95+ : "=r" (pcr)
96+ );
97+}
98+
99+static void imx6_restore_cpu_arch_regs(void)
100+{
101+ /* Restore the diagnostic Control Register. */
102+ asm volatile(
103+ "mcr p15, 0, %0, c15, c0, 1\n"
104+ : : "r" (dcr)
105+ );
106+ /* Restore the Power Control Register. */
107+ asm volatile(
108+ "mcr p15, 0, %0, c15, c0, 0\n"
109+ : : "r" (pcr)
110+ );
111+}
112+
113 static void imx6_enable_rbc(bool enable)
114 {
115 u32 val;
116@@ -290,8 +320,14 @@ static int imx6_pm_enter(suspend_state_t state)
117 imx_gpc_pre_suspend(true);
118 imx_anatop_pre_suspend();
119 imx_set_cpu_jump(0, v7_cpu_resume);
120+
121+ imx6_save_cpu_arch_regs();
122+
123 /* Zzz ... */
124 cpu_suspend(0, imx6_suspend_finish);
125+
126+ imx6_restore_cpu_arch_regs();
127+
128 if (!cpu_is_imx6sl())
129 imx_smp_prepare();
130 imx_anatop_post_resume();
131--
1322.1.0
133
diff --git a/recipes-kernel/linux/linux-imx_3.10.17.bb b/recipes-kernel/linux/linux-imx_3.10.17.bb
index 9ec3a3e..1b34520 100644
--- a/recipes-kernel/linux/linux-imx_3.10.17.bb
+++ b/recipes-kernel/linux/linux-imx_3.10.17.bb
@@ -14,4 +14,15 @@ SRCBRANCH = "imx_3.10.17_1.0.1_ga"
14SRCREV = "dac46dcf913585956a0e7a838e6f4b7465f00f57" 14SRCREV = "dac46dcf913585956a0e7a838e6f4b7465f00f57"
15LOCALVERSION = "-1.0.1_ga" 15LOCALVERSION = "-1.0.1_ga"
16 16
17SRC_URI += "file://0001-ENGR00309838-ARM-imx6sl-gpc-add-chip-revision-check-.patch \
18 file://0002-regulator-pfuze100-Fix-address-of-FABID.patch \
19 file://0003-regulator-pfuze100-add-pfuze200-support.patch \
20 file://0004-regulator-pfuze100-Add-terminate-entry-for-i2c-of-_d.patch \
21 file://0005-regulator-pfuze100-Add-PFUZE200-support-to-Kconfig-a.patch \
22 file://0006-regulator-pfuze100-Use-of_get_child_by_name.patch \
23 file://0007-pfuze100-regulator-Fix-of_node_get-parameter.patch \
24 file://0008-ENGR00301078-1-ARM-dts-imx6dl-sabresd-add-support-fo.patch \
25 file://0009-ENGR00301078-2-ARM-dts-imx6sl-evk-add-support-for-pf.patch \
26 file://0010-ENGR00318392-ARM-imx6x-Save-restore-SCU-and-some-CP1.patch"
27
17COMPATIBLE_MACHINE = "(mx6)" 28COMPATIBLE_MACHINE = "(mx6)"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-05 14:28:27 +0000