From a2385484a70264bfcd06f65242aafcac53cdf661 Mon Sep 17 00:00:00 2001 From: Jerry Pei Date: Mon, 23 Apr 2012 12:28:50 +0800 Subject: [PATCH 1/7] add lsi acp3448v2 bsp patches to mainline linux-3.0.6 Signed-off-by: Jerry Pei --- Documentation/powerpc/dts-bindings/open-pic.txt | 98 + arch/powerpc/Kconfig | 2 +- arch/powerpc/Makefile | 13 + arch/powerpc/boot/Makefile | 38 +- arch/powerpc/boot/acp.c | 262 ++ arch/powerpc/boot/crt0.S | 63 + arch/powerpc/boot/dts/acp.dts | 129 + arch/powerpc/boot/dts/acpiss.dts | 175 + arch/powerpc/boot/dts/acpx1.dts | 129 + arch/powerpc/boot/dts/iss476-amp1.dts | 124 + arch/powerpc/boot/dts/iss476-amp2.dts | 123 + arch/powerpc/boot/dts/iss4xx-mpic.dts | 5 +- arch/powerpc/boot/main.c | 6 +- arch/powerpc/boot/serial.c | 16 + arch/powerpc/boot/treeboot-acp.c | 65 + arch/powerpc/boot/treeboot-acpiss.c | 56 + arch/powerpc/boot/treeboot-iss4xx-hi.c | 65 + arch/powerpc/boot/wrapper | 10 +- arch/powerpc/configs/acp_ACP344xV1_defconfig | 1267 +++++++ arch/powerpc/configs/acp_dbgconfig | 1655 +++++++++ arch/powerpc/configs/acp_defconfig | 1641 ++++++++ arch/powerpc/configs/acp_mel_defconfig | 1859 ++++++++++ arch/powerpc/configs/acp_srio_defconfig | 1640 ++++++++ arch/powerpc/configs/acpiss_defconfig | 1054 ++++++ arch/powerpc/include/asm/asm-compat.h | 23 + arch/powerpc/include/asm/cputable.h | 2 + arch/powerpc/include/asm/dcr-native.h | 26 +- arch/powerpc/include/asm/lsi.h | 6 + arch/powerpc/include/asm/mpic.h | 2 + arch/powerpc/include/asm/ppc-opcode.h | 4 + arch/powerpc/include/asm/reg.h | 3 +- arch/powerpc/include/asm/reg_booke.h | 10 + arch/powerpc/include/asm/spinlock.h | 50 +- arch/powerpc/kernel/cputable.c | 34 +- arch/powerpc/kernel/entry_32.S | 35 +- arch/powerpc/kernel/head_booke.h | 6 +- arch/powerpc/kernel/misc_32.S | 33 +- arch/powerpc/kernel/misc_64.S | 22 + arch/powerpc/kernel/smp.c | 13 +- arch/powerpc/kernel/traps.c | 45 + arch/powerpc/kernel/udbg.c | 2 + arch/powerpc/kernel/udbg_16550.c | 132 +- arch/powerpc/lib/copy_32.S | 7 +- arch/powerpc/mm/44x_mmu.c | 4 - arch/powerpc/mm/init_32.c | 5 + arch/powerpc/platforms/44x/Kconfig | 26 + arch/powerpc/platforms/44x/Makefile | 2 + arch/powerpc/platforms/44x/acpx1.c | 182 + arch/powerpc/sysdev/mpic.c | 31 +- arch/powerpc/sysdev/ppc4xx_soc.c | 90 + drivers/Kconfig | 2 + drivers/Makefile | 2 + drivers/block/Kconfig | 4 + drivers/block/Makefile | 1 + drivers/block/iss_blk.c | 394 ++ drivers/dma/Kconfig | 4 + drivers/dma/lsi-dma.c | 549 +++ drivers/dma/lsi-dma.h | 42 + drivers/i2c/busses/Kconfig | 6 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-lsi.c | 352 ++ drivers/i2c/busses/i2c-lsi.h | 60 + drivers/lsi/Kconfig | 104 + drivers/lsi/Makefile | 1 + drivers/lsi/acp/Makefile | 13 + drivers/lsi/acp/clocks.c | 253 ++ drivers/lsi/acp/nand.c | 3666 ++++++++++++++++++ drivers/lsi/acp/ncr.c | 280 ++ drivers/lsi/acp/ncr.h | 40 + drivers/lsi/acp/net.c | 4534 +++++++++++++++++++++++ drivers/lsi/acp/pci_plx.c | 795 ++++ drivers/lsi/acp/serial.c | 1342 +++++++ drivers/lsi/acp/test.c | 300 ++ drivers/lsi/acp/ubootenv.c | 557 +++ drivers/lsi/acp/version.c | 347 ++ drivers/lsi/acp/wrappers.c | 257 ++ drivers/lsi/common/debug.h | 63 + drivers/lsi/common/version.h | 28 + drivers/mtd/devices/phram.c | 1 + drivers/mtd/nand/nand_base.c | 88 +- drivers/mtd/nand/nand_ids.c | 1 + drivers/rapidio/Kconfig | 2 + drivers/rapidio/Makefile | 1 + drivers/rapidio/mports/Kconfig | 23 + drivers/rapidio/mports/Makefile | 5 + drivers/rapidio/mports/tsi620/Makefile | 6 + drivers/rapidio/mports/tsi620/tsi620.c | 703 ++++ drivers/rapidio/mports/tsi620/tsi620.h | 123 + drivers/rapidio/rio-scan.c | 11 +- drivers/rapidio/rio.c | 31 +- drivers/usb/host/Kconfig | 13 + drivers/usb/host/ci13612.h | 887 +++++ drivers/usb/host/ehci-ci13612.c | 215 ++ drivers/usb/host/ehci-ci13612.h | 54 + drivers/usb/host/ehci-hcd.c | 31 + include/linux/rio.h | 14 + kernel/smp.c | 19 +- scripts/rw.sh | 120 + scripts/tags.sh | 3 +- 103 files changed, 28496 insertions(+), 89 deletions(-) create mode 100644 Documentation/powerpc/dts-bindings/open-pic.txt create mode 100644 arch/powerpc/boot/acp.c create mode 100644 arch/powerpc/boot/dts/acp.dts create mode 100644 arch/powerpc/boot/dts/acpiss.dts create mode 100644 arch/powerpc/boot/dts/acpx1.dts create mode 100644 arch/powerpc/boot/dts/iss476-amp1.dts create mode 100644 arch/powerpc/boot/dts/iss476-amp2.dts create mode 100644 arch/powerpc/boot/treeboot-acp.c create mode 100644 arch/powerpc/boot/treeboot-acpiss.c create mode 100644 arch/powerpc/boot/treeboot-iss4xx-hi.c create mode 100644 arch/powerpc/configs/acp_ACP344xV1_defconfig create mode 100644 arch/powerpc/configs/acp_dbgconfig create mode 100644 arch/powerpc/configs/acp_defconfig create mode 100644 arch/powerpc/configs/acp_mel_defconfig create mode 100644 arch/powerpc/configs/acp_srio_defconfig create mode 100644 arch/powerpc/configs/acpiss_defconfig create mode 100644 arch/powerpc/include/asm/lsi.h create mode 100644 arch/powerpc/platforms/44x/acpx1.c create mode 100644 drivers/block/iss_blk.c create mode 100644 drivers/dma/lsi-dma.c create mode 100644 drivers/dma/lsi-dma.h create mode 100644 drivers/i2c/busses/i2c-lsi.c create mode 100644 drivers/i2c/busses/i2c-lsi.h create mode 100644 drivers/lsi/Kconfig create mode 100644 drivers/lsi/Makefile create mode 100644 drivers/lsi/acp/Makefile create mode 100644 drivers/lsi/acp/clocks.c create mode 100644 drivers/lsi/acp/nand.c create mode 100644 drivers/lsi/acp/ncr.c create mode 100644 drivers/lsi/acp/ncr.h create mode 100644 drivers/lsi/acp/net.c create mode 100644 drivers/lsi/acp/pci_plx.c create mode 100644 drivers/lsi/acp/serial.c create mode 100644 drivers/lsi/acp/test.c create mode 100644 drivers/lsi/acp/ubootenv.c create mode 100644 drivers/lsi/acp/version.c create mode 100644 drivers/lsi/acp/wrappers.c create mode 100644 drivers/lsi/common/debug.h create mode 100644 drivers/lsi/common/version.h create mode 100644 drivers/rapidio/mports/Kconfig create mode 100644 drivers/rapidio/mports/Makefile create mode 100644 drivers/rapidio/mports/tsi620/Makefile create mode 100644 drivers/rapidio/mports/tsi620/tsi620.c create mode 100644 drivers/rapidio/mports/tsi620/tsi620.h create mode 100644 drivers/usb/host/ci13612.h create mode 100644 drivers/usb/host/ehci-ci13612.c create mode 100644 drivers/usb/host/ehci-ci13612.h create mode 100644 scripts/rw.sh diff --git a/Documentation/powerpc/dts-bindings/open-pic.txt b/Documentation/powerpc/dts-bindings/open-pic.txt new file mode 100644 index 0000000..909a902 --- /dev/null +++ b/Documentation/powerpc/dts-bindings/open-pic.txt @@ -0,0 +1,98 @@ +* Open PIC Binding + +This binding specifies what properties must be available in the device tree +representation of an Open PIC compliant interrupt controller. This binding is +based on the binding defined for Open PIC in [1] and is a superset of that +binding. + +Required properties: + + NOTE: Many of these descriptions were paraphrased here from [1] to aid + readability. + + - compatible: Specifies the compatibility list for the PIC. The type + shall be and the value shall include "open-pic". + + - reg: Specifies the base physical address(s) and size(s) of this + PIC's addressable register space. The type shall be . + + - interrupt-controller: The presence of this property identifies the node + as an Open PIC. No property value shall be defined. + + - #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 2. + + - #address-cells: Specifies the number of cells needed to encode an + address. The type shall be and the value shall be 0. As such, + 'interrupt-map' nodes do not have to specify a parent unit address. + +Optional properties: + + - pic-no-reset: The presence of this property indicates that the PIC + shall not be reset during runtime initialization. No property value shall + be defined. The presence of this property also mandates that any + initialization related to interrupt sources shall be limited to sources + explicitly referenced in the device tree. + +* Interrupt Specifier Definition + + Interrupt specifiers consists of 2 cells encoded as + follows: + + - <1st-cell>: The interrupt-number that identifies the interrupt source. + + - <2nd-cell>: The level-sense information, encoded as follows: + 0 = low-to-high edge triggered + 1 = active low level-sensitive + 2 = active high level-sensitive + 3 = high-to-low edge triggered + +* Examples + +Example 1: + + /* + * An Open PIC interrupt controller + */ + mpic: pic@40000 { + // This is an interrupt controller node. + interrupt-controller; + + // No address cells so that 'interrupt-map' nodes which reference + // this Open PIC node do not need a parent address specifier. + #address-cells = <0>; + + // Two cells to encode interrupt sources. + #interrupt-cells = <2>; + + // Offset address of 0x40000 and size of 0x40000. + reg = <0x40000 0x40000>; + + // Compatible with Open PIC. + compatible = "open-pic"; + + // The PIC shall not be reset. + pic-no-reset; + }; + +Example 2: + + /* + * An interrupt generating device that is wired to an Open PIC. + */ + serial0: serial@4500 { + // Interrupt source '42' that is active high level-sensitive. + // Note that there are only two cells as specified in the interrupt + // parent's '#interrupt-cells' property. + interrupts = <42 2>; + + // The interrupt controller that this device is wired to. + interrupt-parent = <&mpic>; + }; + +* References + +[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform + Requirements (ePAPR), Version 1.0, July 2008. + (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf) + diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 2729c66..da004ed 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -890,7 +890,7 @@ config KERNEL_START config PHYSICAL_START_BOOL bool "Set physical address where the kernel is loaded" - depends on ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE + depends on ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE || ACP help This gives the physical address where the kernel is loaded. diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index b7212b6..22019af 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -130,7 +130,9 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) KBUILD_CFLAGS += -mno-sched-epilog endif +ifneq ($(CONFIG_ACP),y) cpu-as-$(CONFIG_4xx) += -Wa,-m405 +endif cpu-as-$(CONFIG_6xx) += -Wa,-maltivec cpu-as-$(CONFIG_POWER4) += -Wa,-maltivec cpu-as-$(CONFIG_E500) += -Wa,-me500 @@ -187,6 +189,17 @@ $(BOOT_TARGETS1): vmlinux $(BOOT_TARGETS2): vmlinux $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@) +vmlinux.bin: vmlinux + @echo -e " OBJCOPY => vmlinux.bin" + $(Q)$(OBJCOPY) -O binary -R .note -R .comment -S vmlinux vmlinux.bin +# +# Generate search path for RISCWatch +# --------------------------------------------------------------------------- +quiet_cmd_rw = GEN + cmd_rw = $(CONFIG_SHELL) $(srctree)/scripts/rw.sh + +rw.path: + $(call cmd,rw) bootwrapper_install: $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@) diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index c26200b..3d75d98 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -16,6 +16,8 @@ # To make it easier to setup a cross compiler, # CROSS32_COMPILE is setup as a prefix just like CROSS_COMPILE # in the toplevel makefile. +# +# These patches add ACP3400 support signed-off-by: john.jacques@lsi.com all: $(obj)/zImage @@ -29,6 +31,16 @@ ifdef CONFIG_DEBUG_INFO BOOTCFLAGS += -g endif +ifdef CONFIG_ACP +BOOTCFLAGS += -DCONFIG_ACP +BOOTAFLAGS += -DCONFIG_ACP +endif + +ifdef CONFIG_ACPISS +BOOTCFLAGS += -DCONFIG_ACPISS +BOOTAFLAGS += -DCONFIG_ACPISS +endif + ifeq ($(call cc-option-yn, -fstack-protector),y) BOOTCFLAGS += -fno-stack-protector endif @@ -45,7 +57,11 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 +$(obj)/treeboot-iss476-amp1.o: BOOTCFLAGS += -mcpu=405 +$(obj)/treeboot-iss476-amp2.o: BOOTCFLAGS += -mcpu=405 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405 +$(obj)/treeboot-acpiss.o: BOOTCFLAGS += -mcpu=405 +$(obj)/treeboot-acp.o: BOOTCFLAGS += -mcpu=405 zlib := inffast.c inflate.c inftrees.c @@ -67,7 +83,7 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \ gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \ 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \ cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \ - fsl-soc.c mpc8xx.c pq2.c ugecon.c + fsl-soc.c mpc8xx.c pq2.c ugecon.c acp.c src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \ cuboot-ebony.c cuboot-hotfoot.c epapr.c treeboot-ebony.c \ prpmc2800.c \ @@ -79,7 +95,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \ - gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c + gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c \ + treeboot-iss4xx-hi.c treeboot-acpiss.c treeboot-acp.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -210,7 +227,12 @@ image-$(CONFIG_KATMAI) += cuImage.katmai image-$(CONFIG_WARP) += cuImage.warp image-$(CONFIG_YOSEMITE) += cuImage.yosemite image-$(CONFIG_ISS4xx) += treeImage.iss4xx \ - treeImage.iss4xx-mpic + treeImage.iss4xx-mpic \ + treeImage.iss476-amp1 \ + treeImage.iss476-amp2 +image-$(CONFIG_ACPISS) += treeImage.acpiss +image-$(CONFIG_ACP) += treeImage.acp + # Board ports in arch/powerpc/platform/8xx/Kconfig image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads @@ -283,20 +305,20 @@ initrd-y := $(patsubst zImage%, zImage.initrd%, \ initrd-y := $(filter-out $(image-y), $(initrd-y)) targets += $(image-y) $(initrd-y) -$(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz +$(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image # Don't put the ramdisk on the pattern rule; when its missing make will try # the pattern rule with less dependencies that also matches (even with the # hard dependency listed). $(obj)/zImage.initrd.%: vmlinux $(wrapperbits) - $(call if_changed,wrap,$*,,,$(obj)/ramdisk.image.gz) + $(call if_changed,wrap,$*,,,$(obj)/ramdisk.image) $(obj)/zImage.%: vmlinux $(wrapperbits) $(call if_changed,wrap,$*) # dtbImage% - a dtbImage is a zImage with an embedded device tree blob $(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(obj)/%.dtb - $(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz) + $(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image) $(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb $(call if_changed,wrap,$*,,$(obj)/$*.dtb) @@ -322,13 +344,13 @@ $(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb) $(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits) - $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz) + $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image) $(obj)/simpleImage.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb) $(obj)/treeImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits) - $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz) + $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image) $(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits) $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb) diff --git a/arch/powerpc/boot/acp.c b/arch/powerpc/boot/acp.c new file mode 100644 index 0000000..a68c8fd --- /dev/null +++ b/arch/powerpc/boot/acp.c @@ -0,0 +1,262 @@ +/* + * arch/powerpc/boot/acp.c + * + * Copyright (C) 2010 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "io.h" +#include "ops.h" + +#if 1 +#define writeapb(offset, value) out_le32((offset), (value)) +#define readapb(offset) in_le32((offset)) +#else +static inline void +writeapb(unsigned *address, int value) +{ + __asm__ __volatile__("stwbrx %1,0,%2" + : "=m" (*address) + : "r" (value), "r" (address)); +} +static inline unsigned +readapb(const unsigned *address) +{ + unsigned value; + + __asm__ __volatile__("lwbrx %0,0,%1; twi 0,%0,0" + : "=r" (value) + : "r" (address), "m" (*address)); + + return value; +} +#endif + +/* + ====================================================================== + ====================================================================== + Clocks and Divisors... + ====================================================================== + ====================================================================== +*/ + +static void *timer_base; + +#define TIMER_LOAD 0x00 +#define TIMER_VALUE 0x04 +#define TIMER_CONTROL 0x08 +#define TIMER_CONTROL_ENABLE 0x80 +#define TIMER_CONTROL_MODE 0x40 +#define TIMER_CONTROL_INTERRUPT_ENABLE 0x20 +#define TIMER_CONTROL_OUTPUT_MODE 0x10 +#define TIMER_CONTROL_PRESCALER 0x0c +#define TIMER_CONTROL_SIZE 0x02 +#define TIMER_CONTROL_ONE_SHOT 0x01 +#define TIMER_INTCLR 0x0C +#define TIMER_RIS 0x10 +#define TIMER_MIS 0x14 +#define TIMER_BGLOAD 0x18 + +/* + ====================================================================== +*/ + +struct clock_stuff { + + unsigned char ibrd; + unsigned char fbrd; + +}; + +/* + ---------------------------------------------------------------------- + get_clock_stuff +*/ + +static int +get_clock_stuff(int baud_rate, struct clock_stuff *clock_stuff) +{ + + unsigned long speed_; + unsigned long divisor_; + unsigned long ibrd_, fbrd_; + + speed_ = 6500000; + + /* + The UART clock is derived from the ARM core clock using the second + timer (timer 1). Each time timer 1 crosses zero, the UART clock + gets toggled. The timer load value acts as a divisor. + + Since the IBDR (integer part of the baud rate divisor) is a 16 bit + quatity, find the minimum load value that will let the IBDR/FBDR + result in the desired baud rate. + */ + + divisor_ = 1; + + do { + ibrd_ = (speed_ / ++divisor_) / (16 * baud_rate); + } while (0xff < ibrd_); + + /* + The following forumla is from the ARM document (ARM DDI 0183E). + + Baud Rate Divisor = (Uart Clock / (16 * Baud Rate)) + + Baud Rate Divisor is then split into integral and fractional + parts. The IBRD value is simply the itegral part. The FBRD is + calculated as follows. + + FBRD = fractional part of the Baud Rate Divisor * 64 + 0.5 + + The fractional part of the Baud Rate Divisor can be represented as + follows. + + (Uart Clock % (16 * baud_rate)) / (16 * baud_rate) + + As long as the division isn't done till the end. So, the above * + 64 + 0.5 is the FBRD. Also note that x/y + 1/2 = (2x+y)/2y. This + leads to + + ((Uart Clock % (16 * baud_rate)) * 64 * 2 + (16 * baud_rate)) + --------------------------------------------------------------------- + 2 * (16 * baud_rate) + */ + + fbrd_ = (speed_ / divisor_) % (16 * baud_rate); + fbrd_ *= 128; + fbrd_ += (16 * baud_rate); + fbrd_ /= (2 * (16 * baud_rate)); + + --divisor_; + clock_stuff->ibrd = ibrd_; + clock_stuff->fbrd = fbrd_; + + /* + * Set up the clock. + */ + + writeapb(timer_base + TIMER_CONTROL, 0); + writeapb(timer_base + TIMER_LOAD, divisor_); + writeapb(timer_base + TIMER_CONTROL, + (TIMER_CONTROL_ENABLE | TIMER_CONTROL_MODE)); + + return 0; + +} + +/* + ====================================================================== + ====================================================================== + serial + ====================================================================== + ====================================================================== +*/ + +static void *uart0_base; + +#define UART_DR 0x00 +#define UART_FR 0x18 +#define UART_IBRD 0x24 +#define UART_FBRD 0x28 +#define UART_LCR_H 0x2c +#define UART_CR 0x30 +#define UART_IFLS 0x34 +#define UART_IMSC 0x38 +#define UART_ECR 0x04 + +#define FR_RXFE 0x10 +#define FR_TXFF 0x20 + +static int +acp_serial_open(void) +{ + struct clock_stuff clock_stuff; + + get_clock_stuff(9600, &clock_stuff); + writeapb(uart0_base + UART_IBRD, clock_stuff.ibrd); + writeapb(uart0_base + UART_FBRD, clock_stuff.fbrd); + writeapb(uart0_base + UART_LCR_H, 0x70); + writeapb(uart0_base + UART_CR, 0x301); + writeapb(uart0_base + UART_IFLS, 0); + writeapb(uart0_base + UART_IMSC, 0x700); + writeapb(uart0_base + UART_ECR, 0); + + return 0; +} + +static void +acp_serial_putc(unsigned char c) +{ + while (0 != (readapb(uart0_base + UART_FR) & FR_TXFF)) + ; + + if ('\n' == c) { + writeapb(uart0_base + UART_DR, '\r'); + while (0 != (readapb(uart0_base + UART_FR) & FR_TXFF)) + ; + } + + writeapb(uart0_base + UART_DR, c); + + return; +} + +static unsigned char +acp_serial_getc(void) +{ + while (0 != (readapb(uart0_base + UART_FR) & FR_RXFE)) + ; + return readapb(uart0_base + UART_DR); +} + +static unsigned char +acp_serial_tstc(void) +{ + return (0 != (readapb(uart0_base + UART_FR) & FR_RXFE)); +} + +int +acp_console_init(void *devp, struct serial_console_data *scdp) +{ +#if 0 + unsigned long reg_offset; + + if (dt_get_virtual_reg(devp, (void **) &uart0_base, 1) < 1) + return -1; + + if (sizeof(reg_offset) == + getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset))) + uart0_base += reg_offset; + + if (sizeof(reg_shift) != + getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift))) + reg_shift = 0; +#else + uart0_base = (void *) 0xf0004000; + /*uart0_base = (void *) 0xf0024000;*/ + timer_base = (void *) 0xf0008040; + /*timer_base = (void *) 0xf0029040;*/ +#endif + scdp->open = acp_serial_open; + scdp->putc = acp_serial_putc; + scdp->getc = acp_serial_getc; + scdp->tstc = acp_serial_tstc; + scdp->close = NULL; + + return 0; +} diff --git a/arch/powerpc/boot/crt0.S b/arch/powerpc/boot/crt0.S index 0f7428a..db5db46 100644 --- a/arch/powerpc/boot/crt0.S +++ b/arch/powerpc/boot/crt0.S @@ -34,6 +34,69 @@ p_pstack: .long _platform_stack_top _zimage_start: .globl _zimage_start_lib _zimage_start_lib: + +#ifdef CONFIG_PPC47x + /* Clear all UTLB entries as recommended by IBM (work-around) */ + + addis r3,0,0x8000 + addi r4,0,0 + addi r5,0,0 + b clear_utlb_entry + + #; Align the loop to speed things up a bit. + .align 6 + +clear_utlb_entry: + + tlbwe r4,r3,0 + tlbwe r5,r3,1 + tlbwe r5,r3,2 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + addis r3,r3,0x2000 + cmpwi r3,0 + bne clear_utlb_entry + addis r3,0,0x8000 + addis r4,r4,0x100 + cmpwi r4,0 + bne clear_utlb_entry + + #; Restore the inital UTLB entries. + addi r23,0,0 + addi r24,0,0xbf0 + addi r25,0,0 + lis r26,(0x00030307)@h + ori r26,r26,(0x00030307)@l + tlbwe r24,r23,0 + tlbwe r25,r23,1 + tlbwe r26,r23,2 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + lis r23,(0x00f00000)@h + ori r23,r23,(0x00f0000)@l + lis r24,(0xf0000870)@h + ori r24,r24,(0xf0000870)@l + lis r25,(0x00400020)@h + ori r25,r25,(0x00400020)@l + lis r26,(0x00030707)@h + ori r26,r26,(0x00030707)@l + tlbwe r24,r23,0 + tlbwe r25,r23,1 + tlbwe r26,r23,2 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + addo r6,r6,r6 + isync +#endif + /* Work out the offset between the address we were linked at and the address where we're running. */ bl .+4 diff --git a/arch/powerpc/boot/dts/acp.dts b/arch/powerpc/boot/dts/acp.dts new file mode 100644 index 0000000..90965db --- /dev/null +++ b/arch/powerpc/boot/dts/acp.dts @@ -0,0 +1,129 @@ +/* + * Device Tree Source for IBM Embedded PPC 476 Platform + * + * Copyright 2009 Torez Smith, IBM Corporation. + * + * Based on earlier code: + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer , David Gibson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com + */ + +/dts-v1/; + +/memreserve/ 0x01f00000 0x00100000; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,acpx1-4xx"; + compatible = "ibm,acpx1-4xx"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + serial0 = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <0>; + clock-frequency = <12500000>; // 12.5 MHz + //timebase-frequency = <781250>; // CCR1 is div by 16 + timebase-frequency = <12500000>; // 12.5 MHz + //timebase-frequency = <50000000>; // 50 MHz + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + }; + }; + + memory { + device_type = "memory"; + /* + * Originally we have 256M of RAM on the system. Start at 4M + * offset and define the RAM to be 252M instead (256M - 4M). + * + * Since we are hard coding RAM, comment out the + * line platform_ops.fixups = iss_4xx_fixups; + * inside file arch/powerpc/boot/treeboot-iss4xx.c + * This allows us to statically define it instead of later calling + * dt_fixup_memory() to define it and re-write found value inside + * device tree. + * + * Using 2 Address Cell and 1 Size Cell notation + */ + /* + * This is the original RAM line...filled in later by dt_fixup_memory() + * routine. + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage + */ + + reg = < 0x0 0x400000 0xFC00000 >; // hardcode 252M starting at 4M + }; + + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + + }; + + plb { + compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + clock-frequency = <0>; // Filled in by zImage + UART0: serial@00404000 { + device_type = "serial"; + compatible = "acp-uart0"; + reg = <0x00404000 0x00001000>; + virtual-reg = <0xf0004000>; + clock-frequency = <33333333>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <22>; + }; + }; + }; + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + iss-block { + compatible = "ibm,iss-sim-block-device"; + reg = <0 0xEF701000 0x1000>; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@40000200"; + }; +}; diff --git a/arch/powerpc/boot/dts/acpiss.dts b/arch/powerpc/boot/dts/acpiss.dts new file mode 100644 index 0000000..5dbc143 --- /dev/null +++ b/arch/powerpc/boot/dts/acpiss.dts @@ -0,0 +1,175 @@ +/* + * Device Tree Source for IBM Embedded PPC 476 Platform + * + * Copyright 2009 Torez Smith, IBM Corporation. + * + * Based on earlier code: + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer , David Gibson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com + */ + +/dts-v1/; + +/memreserve/ 0x01f00000 0x00100000; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,iss-4xx"; + compatible = "ibm,iss-4xx"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + serial0 = &UART0; + serial1 = &UART1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <0>; + clock-frequency = <0x5f5e1000>; // 1.6Ghz :-) + timebase-frequency = <0x5f5e1000>; + //clock-frequency = <100000000>; // 100Mhz :-) + //timebase-frequency = <100000000>; + i-cache-line-size = <32>; // may need fixup in sim + d-cache-line-size = <32>; // may need fixup in sim + i-cache-size = <32768>; /* may need fixup in sim */ + d-cache-size = <32768>; /* may need fixup in sim */ + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + }; + cpu@1 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <1>; + clock-frequency = <0x5f5e1000>; // 1.6Ghz :-) + timebase-frequency = <0x5f5e1000>; + //clock-frequency = <100000000>; // 100Mhz :-) + //timebase-frequency = <100000000>; + i-cache-line-size = <32>; // may need fixup in sim + d-cache-line-size = <32>; // may need fixup in sim + i-cache-size = <32768>; /* may need fixup in sim */ + d-cache-size = <32768>; /* may need fixup in sim */ + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0x01f00100>; + }; + cpu@2 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <2>; + clock-frequency = <0x5f5e1000>; // 1.6Ghz :-) + timebase-frequency = <0x5f5e1000>; + //clock-frequency = <100000000>; // 100Mhz :-) + //timebase-frequency = <100000000>; + i-cache-line-size = <32>; // may need fixup in sim + d-cache-line-size = <32>; // may need fixup in sim + i-cache-size = <32768>; /* may need fixup in sim */ + d-cache-size = <32768>; /* may need fixup in sim */ + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0x01f00200>; + }; + cpu@3 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <3>; + clock-frequency = <0x5f5e1000>; // 1.6Ghz :-) + timebase-frequency = <0x5f5e1000>; + //clock-frequency = <100000000>; // 100Mhz :-) + //timebase-frequency = <100000000>; + i-cache-line-size = <32>; // may need fixup in sim + d-cache-line-size = <32>; // may need fixup in sim + i-cache-size = <32768>; /* may need fixup in sim */ + d-cache-size = <32768>; /* may need fixup in sim */ + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0x01f00300>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage + }; + + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + + }; + + plb { + compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + clock-frequency = <0>; // Filled in by zImage + UART0: serial@40000200 { + device_type = "serial"; + compatible = "ns16550", "ns16550a"; + reg = <0x40000200 0x00000008>; + virtual-reg = <0xe0000200>; + clock-frequency = <11059200>; + current-speed = <115200>; + interrupt-parent = <&MPIC>; + interrupts = <0x0 0x2>; + }; + UART1: serial@40000300 { + device_type = "serial"; + compatible = "ns16550", "ns16550a"; + reg = <0x40000300 0x00000008>; + virtual-reg = <0xe0000300>; + clock-frequency = <11059200>; + current-speed = <115200>; + interrupt-parent = <&MPIC>; + interrupts = <23 0x2>; + }; + }; + }; + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + iss-block { + compatible = "ibm,iss-sim-block-device"; + reg = <0 0xEF701000 0x1000>; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@40000200"; + }; +}; diff --git a/arch/powerpc/boot/dts/acpx1.dts b/arch/powerpc/boot/dts/acpx1.dts new file mode 100644 index 0000000..90965db --- /dev/null +++ b/arch/powerpc/boot/dts/acpx1.dts @@ -0,0 +1,129 @@ +/* + * Device Tree Source for IBM Embedded PPC 476 Platform + * + * Copyright 2009 Torez Smith, IBM Corporation. + * + * Based on earlier code: + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer , David Gibson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com + */ + +/dts-v1/; + +/memreserve/ 0x01f00000 0x00100000; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,acpx1-4xx"; + compatible = "ibm,acpx1-4xx"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + serial0 = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <0>; + clock-frequency = <12500000>; // 12.5 MHz + //timebase-frequency = <781250>; // CCR1 is div by 16 + timebase-frequency = <12500000>; // 12.5 MHz + //timebase-frequency = <50000000>; // 50 MHz + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + }; + }; + + memory { + device_type = "memory"; + /* + * Originally we have 256M of RAM on the system. Start at 4M + * offset and define the RAM to be 252M instead (256M - 4M). + * + * Since we are hard coding RAM, comment out the + * line platform_ops.fixups = iss_4xx_fixups; + * inside file arch/powerpc/boot/treeboot-iss4xx.c + * This allows us to statically define it instead of later calling + * dt_fixup_memory() to define it and re-write found value inside + * device tree. + * + * Using 2 Address Cell and 1 Size Cell notation + */ + /* + * This is the original RAM line...filled in later by dt_fixup_memory() + * routine. + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage + */ + + reg = < 0x0 0x400000 0xFC00000 >; // hardcode 252M starting at 4M + }; + + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + + }; + + plb { + compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + clock-frequency = <0>; // Filled in by zImage + UART0: serial@00404000 { + device_type = "serial"; + compatible = "acp-uart0"; + reg = <0x00404000 0x00001000>; + virtual-reg = <0xf0004000>; + clock-frequency = <33333333>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <22>; + }; + }; + }; + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + iss-block { + compatible = "ibm,iss-sim-block-device"; + reg = <0 0xEF701000 0x1000>; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@40000200"; + }; +}; diff --git a/arch/powerpc/boot/dts/iss476-amp1.dts b/arch/powerpc/boot/dts/iss476-amp1.dts new file mode 100644 index 0000000..1b4e6e4 --- /dev/null +++ b/arch/powerpc/boot/dts/iss476-amp1.dts @@ -0,0 +1,124 @@ +/* + * Device Tree Source for IBM Embedded PPC 476 Platform + * + * Copyright 2010 Torez Smith, IBM Corporation. + * + * Based on earlier code: + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer , David Gibson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/memreserve/ 0x01f00000 0x00100000; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,iss-4xx"; + compatible = "ibm,iss-4xx", "ibm,47x-AMP"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + serial0 = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <0>; + clock-frequency = <100000000>; // 100Mhz :-) + timebase-frequency = <100000000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + }; + cpu@1 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <1>; + clock-frequency = <100000000>; // 100Mhz :-) + timebase-frequency = <100000000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0x01f00100>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage + + }; + + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + + }; + + plb { + compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + clock-frequency = <0>; // Filled in by zImage + UART0: serial@40000200 { + device_type = "serial"; + compatible = "ns16550a"; + reg = <0x40000200 0x00000008>; + virtual-reg = <0xe0000200>; + clock-frequency = <11059200>; + current-speed = <115200>; + interrupt-parent = <&MPIC>; + interrupts = <0x0 0x2>; + }; + }; + }; + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + + iss-block { + compatible = "ibm,iss-sim-block-device"; + reg = <0 0xEF701000 0x1000>; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@40000200"; + }; +}; diff --git a/arch/powerpc/boot/dts/iss476-amp2.dts b/arch/powerpc/boot/dts/iss476-amp2.dts new file mode 100644 index 0000000..df38ee5 --- /dev/null +++ b/arch/powerpc/boot/dts/iss476-amp2.dts @@ -0,0 +1,123 @@ +/* + * Device Tree Source for IBM Embedded PPC 476 Platform + * + * Copyright 2010 Torez Smith, IBM Corporation. + * + * Based on earlier code: + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer , David Gibson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/memreserve/ 0x11f00000 0x00100000; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,iss-4xx"; + compatible = "ibm,iss-4xx", "ibm,47x-AMP"; + dcr-parent = <&{/cpus/cpu@2}>; + + aliases { + serial0 = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@2 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <2>; + clock-frequency = <100000000>; // 100Mhz :-) + timebase-frequency = <100000000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + }; + cpu@3 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <3>; + clock-frequency = <100000000>; // 100Mhz :-) + timebase-frequency = <100000000>; + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0x11f00300>; + }; + }; + + memory { + device_type = "memory"; +/* + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage + */ + reg = < 0x0 0x10000000 0x02000000 >; + + }; + + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + + }; + + plb { + compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <0x00000000 0x00000001 0x00000000 0x80000000 + 0x80000000 0x00000001 0x80000000 0x80000000>; + clock-frequency = <0>; // Filled in by zImage + UART0: serial@40001200 { + device_type = "serial"; + compatible = "ns16550a"; + reg = <0x40001200 0x00000008>; + virtual-reg = <0xe0001200>; + clock-frequency = <11059200>; + current-speed = <115200>; + interrupt-parent = <&MPIC>; + interrupts = <0x1 0x2>; + }; + }; + }; + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + + chosen { + bootargs = "uart_addr=0xf0001200"; + linux,stdout-path = "/plb/opb/serial@40001200"; + }; +}; diff --git a/arch/powerpc/boot/dts/iss4xx-mpic.dts b/arch/powerpc/boot/dts/iss4xx-mpic.dts index 23e9d9b..b899a10 100644 --- a/arch/powerpc/boot/dts/iss4xx-mpic.dts +++ b/arch/powerpc/boot/dts/iss4xx-mpic.dts @@ -97,7 +97,10 @@ memory { device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage +/* + reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage +*/ + reg = <0x0 0x400000 0x1C00000>; }; diff --git a/arch/powerpc/boot/main.c b/arch/powerpc/boot/main.c index a28f021..adc778d 100644 --- a/arch/powerpc/boot/main.c +++ b/arch/powerpc/boot/main.c @@ -7,6 +7,8 @@ * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com */ #include #include @@ -32,7 +34,7 @@ static struct addr_range prep_kernel(void) char elfheader[256]; void *vmlinuz_addr = _vmlinux_start; unsigned long vmlinuz_size = _vmlinux_end - _vmlinux_start; - void *addr = 0; + void *addr = 0x400000; /* This NEEDS to be tunable.... */ struct elf_info ei; int len; @@ -149,8 +151,10 @@ static void prep_cmdline(void *chosen) printf("\n\rLinux/PowerPC load: %s", cmdline); /* If possible, edit the command line */ +#if 0 if (console_ops.edit_cmdline) console_ops.edit_cmdline(cmdline, COMMAND_LINE_SIZE); +#endif printf("\n\r"); /* Put the command line back into the devtree for the kernel */ diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c index f2156f0..6bf7cef 100644 --- a/arch/powerpc/boot/serial.c +++ b/arch/powerpc/boot/serial.c @@ -10,6 +10,8 @@ * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com */ #include #include @@ -113,6 +115,19 @@ int serial_console_init(void) void *devp; int rc = -1; +#if defined(CONFIG_ACPX1) && !defined(CONFIG_ACPISS) + rc = acp_console_init(devp, &serial_cd); + + if (0 != rc) + return -1; + + console_ops.open = serial_open; + console_ops.write = serial_write; + console_ops.close = serial_close; + console_ops.data = &serial_cd; + + return 0; +#else devp = serial_get_stdout_devp(); if (devp == NULL) goto err_out; @@ -148,4 +163,5 @@ int serial_console_init(void) } err_out: return -1; +#endif } diff --git a/arch/powerpc/boot/treeboot-acp.c b/arch/powerpc/boot/treeboot-acp.c new file mode 100644 index 0000000..3a126a3 --- /dev/null +++ b/arch/powerpc/boot/treeboot-acp.c @@ -0,0 +1,65 @@ +/* + * Copyright 2008 Ben. Herrenschmidt, IBM Corporation. + * + * Based on earlier code: + * Copyright (C) Paul Mackerras 1997. + * + * Matt Porter + * Copyright 2002-2005 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003, 2004 Zultys Technologies + * + * Copyright 2007 David Gibson, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include "types.h" +#include "elf.h" +#include "string.h" +#include "stdio.h" +#include "page.h" +#include "ops.h" +#include "reg.h" +#include "io.h" +#include "dcr.h" +#include "4xx.h" +#include "44x.h" +#include "libfdt.h" + +BSS_STACK(4096); + +static void iss_4xx_fixups(void) +{ + ibm4xx_sdram_fixup_memsize(); + + /* Need to fixup icache/dcache info base on core type */ +} +#define SPRN_PIR 0x11E /* Processor Identification Register */ +void platform_init(void) +{ + /* Sim has at least 128M of RAM ok ? */ + unsigned long end_of_ram = 0x08000000; + unsigned long avail_ram = end_of_ram - (unsigned long)_end; + u32 pir_reg; + + simple_alloc_init(_end, avail_ram, 128, 64); + /* + * Hard code RAM to be 252M with a 4M offset... + * and don't dynamically determine the size. This should + * change when we start working on real HW and have the + * ability to query the HW to determine where memory is + * located. + platform_ops.fixups = iss_4xx_fixups; + */ + platform_ops.exit = ibm44x_dbcr_reset; + pir_reg = mfspr(SPRN_PIR); + fdt_set_boot_cpuid_phys(_dtb_start, pir_reg); + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/treeboot-acpiss.c b/arch/powerpc/boot/treeboot-acpiss.c new file mode 100644 index 0000000..479ed00 --- /dev/null +++ b/arch/powerpc/boot/treeboot-acpiss.c @@ -0,0 +1,56 @@ +/* + * Copyright 2008 Ben. Herrenschmidt, IBM Corporation. + * + * Based on earlier code: + * Copyright (C) Paul Mackerras 1997. + * + * Matt Porter + * Copyright 2002-2005 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003, 2004 Zultys Technologies + * + * Copyright 2007 David Gibson, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com + */ +#include +#include +#include "types.h" +#include "elf.h" +#include "string.h" +#include "stdio.h" +#include "page.h" +#include "ops.h" +#include "reg.h" +#include "io.h" +#include "dcr.h" +#include "4xx.h" +#include "44x.h" + +BSS_STACK(4096); + +static void iss_4xx_fixups(void) +{ + ibm4xx_sdram_fixup_memsize(); + + /* Need to fixup icache/dcache info base on core type */ +} + +void platform_init(void) +{ + /* Sim has at least 128M of RAM ok ? */ + unsigned long end_of_ram = 0x08000000; + unsigned long avail_ram = end_of_ram - (unsigned long)_end; + + simple_alloc_init(_end, avail_ram, 128, 64); + platform_ops.fixups = iss_4xx_fixups; + platform_ops.exit = ibm44x_dbcr_reset; + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/treeboot-iss4xx-hi.c b/arch/powerpc/boot/treeboot-iss4xx-hi.c new file mode 100644 index 0000000..c6f376f --- /dev/null +++ b/arch/powerpc/boot/treeboot-iss4xx-hi.c @@ -0,0 +1,65 @@ +/* + * Copyright 2010 Ben. Herrenschmidt, IBM Corporation. + * + * Based on earlier code: + * Copyright (C) Paul Mackerras 1997. + * + * Matt Porter + * Copyright 2002-2005 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003, 2004 Zultys Technologies + * + * Copyright 2007 David Gibson, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include "types.h" +#include "elf.h" +#include "string.h" +#include "stdio.h" +#include "page.h" +#include "ops.h" +#include "reg.h" +#include "io.h" +#include "dcr.h" +#include "4xx.h" +#include "44x.h" +#include "libfdt.h" + +BSS_STACK(4096); + +static void iss_4xx_fixups(void) +{ + ibm4xx_sdram_fixup_memsize(); +} + +/* + * Quick and dirty hack for loading a kernel at fixed address 0x10000000 + */ +static void *iss_4xx_vmlinux_alloc(unsigned long size) +{ + return (void *)0x10000000; +} + +#define SPRN_PIR 0x11E /* Processor Indentification Register */ +void platform_init(void) +{ + unsigned long end_of_ram = 0x08000000; + unsigned long avail_ram = end_of_ram - (unsigned long)_end; + u32 pir_reg; + + simple_alloc_init(_end, avail_ram, 128, 64); + /* platform_ops.fixups = iss_4xx_fixups; */ + platform_ops.vmlinux_alloc = iss_4xx_vmlinux_alloc; + platform_ops.exit = ibm44x_dbcr_reset; + pir_reg = mfspr(SPRN_PIR); + fdt_set_boot_cpuid_phys(_dtb_start, pir_reg); + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index c74531a..6475baa 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -143,7 +143,7 @@ objflags=-S tmp=$tmpdir/zImage.$$.o ksection=.kernel:vmlinux.strip isection=.kernel:initrd -link_address='0x400000' +link_address='0x800000' case "$platform" in pseries) @@ -247,6 +247,14 @@ gamecube|wii) treeboot-iss4xx-mpic) platformo="$object/treeboot-iss4xx.o" ;; +treeboot-iss476-amp1) + platformo="$object/treeboot-iss4xx.o" + link_address='0x400000' + ;; +treeboot-iss476-amp2) + platformo="$object/treeboot-iss4xx-hi.o" + link_address='0x10400000' + ;; epapr) link_address='0x20000000' pie=-pie diff --git a/arch/powerpc/configs/acp_ACP344xV1_defconfig b/arch/powerpc/configs/acp_ACP344xV1_defconfig new file mode 100644 index 0000000..7e164dc --- /dev/null +++ b/arch/powerpc/configs/acp_ACP344xV1_defconfig @@ -0,0 +1,1267 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35 +# Mon Jul 18 18:05:45 2011 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="powerpc-linux-" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set +CONFIG_PPC4xx_PCI_EXPRESS=y +CONFIG_PPC_MSI_BITMAP=y +# CONFIG_RAPIDIO_FSL is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_PPC_47x=y +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +# CONFIG_ISS4xx is not set +# CONFIG_ICON is not set +CONFIG_ACP=y +# CONFIG_ACPISS is not set +CONFIG_ACP_X1V1=y +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_440GP=y +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +CONFIG_HIGHMEM=y +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_IRQ_ALL_CPUS is not set +CONFIG_SPARSE_IRQ=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_STDBINUTILS=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_PROC_DEVICETREE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0 mtdparts=acp-nand:512K(2ndStage),512K(env-0),512K(env-1),512K(3rdStage),-(fs) ip=dhcp root=/dev/nfs" +CONFIG_EXTRA_TARGETS="" +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +# CONFIG_NEED_DMA_MAP_STATE is not set +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +CONFIG_HAS_RAPIDIO=y +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_ACP=y +CONFIG_RAPIDIO_ACP_RX_SIZE=128 +# CONFIG_RAPIDIO_TSI57X is not set +# CONFIG_RAPIDIO_CPS_XX is not set +# CONFIG_RAPIDIO_TSI568 is not set +# CONFIG_RAPIDIO_TSI500 is not set +# CONFIG_RAPIDIO_DEBUG is not set + +# +# Advanced setup +# +CONFIG_ADVANCED_OPTIONS=y +# CONFIG_LOWMEM_SIZE_BOOL is not set +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_RELOCATABLE=y +CONFIG_PAGE_OFFSET_BOOL=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0xc0400000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE_BOOL=y +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_RPS=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_BLK_DEV_ISS is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +CONFIG_IBM_NEW_EMAC_ZMII=y +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_XILINX_EMACLITE is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_IP1000 is not set +CONFIG_IGB=y +CONFIG_IGBVF=y +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_AIRO is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_RIONET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=20 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# LSI Drivers (APP3, APP3K, and ACP) +# +CONFIG_SERIAL_ACP=y +CONFIG_SERIAL_ACP_CONSOLE=y +# CONFIG_SERIAL_ACP_CONSOLE_POLL is not set +CONFIG_LSI_NET=y +CONFIG_LSI_NET_NUM_RX_DESC=16 +CONFIG_LSI_NET_RX_BUF_SZ=131072 +CONFIG_LSI_NET_NUM_TX_DESC=8 +CONFIG_LSI_NET_TX_BUF_SZ=65536 +CONFIG_LSI_NAND=y +CONFIG_LSI_UBOOTENV=y +# CONFIG_LSI_PLX_PCIE_BRIDGE is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +CONFIG_XMON=y +CONFIG_XMON_DEFAULT=y +CONFIG_XMON_DISASSEMBLY=y +CONFIG_DEBUGGER=y +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=y +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_CRYPTO_DEV_PPC4XX=y +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/acp_dbgconfig b/arch/powerpc/configs/acp_dbgconfig new file mode 100644 index 0000000..2d206e5 --- /dev/null +++ b/arch/powerpc/configs/acp_dbgconfig @@ -0,0 +1,1655 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35 +# Tue Sep 13 11:37:01 2011 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="powerpc-linux-" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set +CONFIG_PPC4xx_PCI_EXPRESS=y +CONFIG_PPC_MSI_BITMAP=y +# CONFIG_RAPIDIO_FSL is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_PPC_47x=y +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +# CONFIG_ISS4xx is not set +# CONFIG_ICON is not set +CONFIG_ACP=y +# CONFIG_ACPISS is not set +# CONFIG_ACP_X1V1 is not set +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_440GP=y +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +CONFIG_HIGHMEM=y +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_IRQ_ALL_CPUS is not set +CONFIG_SPARSE_IRQ=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_STDBINUTILS=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_PROC_DEVICETREE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0 mtdparts=acp-nand:512K(2ndStage),512K(env-0),512K(env-1),512K(3rdStage),-(fs) ip=dhcp root=/dev/nfs" +CONFIG_EXTRA_TARGETS="" +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +# CONFIG_NEED_DMA_MAP_STATE is not set +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +CONFIG_HAS_RAPIDIO=y +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +# CONFIG_RAPIDIO_ACP is not set +CONFIG_RAPIDIO_TSI57X=y +CONFIG_RAPIDIO_CPS_XX=y +CONFIG_RAPIDIO_TSI568=y +CONFIG_RAPIDIO_TSI500=y +CONFIG_RAPIDIO_DEBUG=y + +# +# Advanced setup +# +CONFIG_ADVANCED_OPTIONS=y +# CONFIG_LOWMEM_SIZE_BOOL is not set +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_RELOCATABLE=y +CONFIG_PAGE_OFFSET_BOOL=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0xc0400000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE_BOOL=y +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_RPS=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_UB=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_BLK_DEV_ISS is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +# CONFIG_MD_RAID456 is not set +CONFIG_MD_MULTIPATH=y +CONFIG_MD_FAULTY=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_MIRROR=y +# CONFIG_DM_LOG_USERSPACE is not set +CONFIG_DM_ZERO=y +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +CONFIG_IBM_NEW_EMAC_ZMII=y +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_XILINX_EMACLITE is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_IP1000 is not set +CONFIG_IGB=y +CONFIG_IGBVF=y +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_AIRO is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +CONFIG_USB_ZD1201=y +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +# CONFIG_RIONET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +CONFIG_PPPOE=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_NET_FC is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_N_GSM=y +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=20 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_3M_PCT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_XPS_USB_HCD_XILINX=y +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_CI13612_HCD=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# LSI Drivers (APP3, APP3K, and ACP) +# +CONFIG_SERIAL_ACP=y +CONFIG_SERIAL_ACP_CONSOLE=y +# CONFIG_SERIAL_ACP_CONSOLE_POLL is not set +CONFIG_LSI_NET=y +CONFIG_LSI_NET_NUM_RX_DESC=16 +CONFIG_LSI_NET_RX_BUF_SZ=131072 +CONFIG_LSI_NET_NUM_TX_DESC=8 +CONFIG_LSI_NET_TX_BUF_SZ=65536 +CONFIG_LSI_NAND=y +CONFIG_LSI_UBOOTENV=y +CONFIG_LSI_PLX_PCIE_BRIDGE=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +CONFIG_NLS_CODEPAGE_865=y +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +CONFIG_XMON=y +CONFIG_XMON_DEFAULT=y +CONFIG_XMON_DISASSEMBLY=y +CONFIG_DEBUGGER=y +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BDI_SWITCH is not set +CONFIG_PPC_EARLY_DEBUG=y +# CONFIG_PPC_EARLY_DEBUG_LPAR is not set +# CONFIG_PPC_EARLY_DEBUG_G5 is not set +# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set +# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set +# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set +# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set +# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set +# CONFIG_PPC_EARLY_DEBUG_BEAT is not set +CONFIG_PPC_EARLY_DEBUG_44x=y +# CONFIG_PPC_EARLY_DEBUG_40x is not set +# CONFIG_PPC_EARLY_DEBUG_CPM is not set +# CONFIG_PPC_EARLY_DEBUG_USBGECKO is not set +CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0x00424000 +CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x20 + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=y +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_CRYPTO_DEV_PPC4XX=y +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/acp_defconfig b/arch/powerpc/configs/acp_defconfig new file mode 100644 index 0000000..cc35347 --- /dev/null +++ b/arch/powerpc/configs/acp_defconfig @@ -0,0 +1,1641 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35 +# Fri Jul 15 11:26:48 2011 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="powerpc-linux-" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set +CONFIG_PPC4xx_PCI_EXPRESS=y +CONFIG_PPC_MSI_BITMAP=y +# CONFIG_RAPIDIO_FSL is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_PPC_47x=y +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +# CONFIG_ISS4xx is not set +# CONFIG_ICON is not set +CONFIG_ACP=y +# CONFIG_ACPISS is not set +# CONFIG_ACP_X1V1 is not set +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_440GP=y +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +CONFIG_HIGHMEM=y +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_IRQ_ALL_CPUS is not set +CONFIG_SPARSE_IRQ=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_STDBINUTILS=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_PROC_DEVICETREE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0 mtdparts=acp-nand:512K(2ndStage),512K(env-0),512K(env-1),512K(3rdStage),-(fs) ip=dhcp root=/dev/nfs" +CONFIG_EXTRA_TARGETS="" +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +# CONFIG_NEED_DMA_MAP_STATE is not set +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +CONFIG_HAS_RAPIDIO=y +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +# CONFIG_RAPIDIO_ACP is not set +CONFIG_RAPIDIO_TSI57X=y +CONFIG_RAPIDIO_CPS_XX=y +CONFIG_RAPIDIO_TSI568=y +CONFIG_RAPIDIO_TSI500=y +CONFIG_RAPIDIO_DEBUG=y + +# +# Advanced setup +# +CONFIG_ADVANCED_OPTIONS=y +# CONFIG_LOWMEM_SIZE_BOOL is not set +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_RELOCATABLE=y +CONFIG_PAGE_OFFSET_BOOL=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0xc0400000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE_BOOL=y +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_RPS=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_UB=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_BLK_DEV_ISS is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +# CONFIG_MD_RAID456 is not set +CONFIG_MD_MULTIPATH=y +CONFIG_MD_FAULTY=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_MIRROR=y +# CONFIG_DM_LOG_USERSPACE is not set +CONFIG_DM_ZERO=y +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +CONFIG_IBM_NEW_EMAC_ZMII=y +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_XILINX_EMACLITE is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_IP1000 is not set +CONFIG_IGB=y +CONFIG_IGBVF=y +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_AIRO is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +CONFIG_USB_ZD1201=y +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +# CONFIG_RIONET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +CONFIG_PPPOE=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_NET_FC is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_N_GSM=y +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=20 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_3M_PCT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_XPS_USB_HCD_XILINX=y +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_CI13612_HCD=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# LSI Drivers (APP3, APP3K, and ACP) +# +CONFIG_SERIAL_ACP=y +CONFIG_SERIAL_ACP_CONSOLE=y +# CONFIG_SERIAL_ACP_CONSOLE_POLL is not set +CONFIG_LSI_NET=y +CONFIG_LSI_NET_NUM_RX_DESC=16 +CONFIG_LSI_NET_RX_BUF_SZ=131072 +CONFIG_LSI_NET_NUM_TX_DESC=8 +CONFIG_LSI_NET_TX_BUF_SZ=65536 +CONFIG_LSI_NAND=y +CONFIG_LSI_UBOOTENV=y +CONFIG_LSI_PLX_PCIE_BRIDGE=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +CONFIG_NLS_CODEPAGE_865=y +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +CONFIG_XMON=y +CONFIG_XMON_DEFAULT=y +CONFIG_XMON_DISASSEMBLY=y +CONFIG_DEBUGGER=y +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=y +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_CRYPTO_DEV_PPC4XX=y +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/acp_mel_defconfig b/arch/powerpc/configs/acp_mel_defconfig new file mode 100644 index 0000000..d18cc50 --- /dev/null +++ b/arch/powerpc/configs/acp_mel_defconfig @@ -0,0 +1,1859 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/powerpc 3.1.0-rc9 Kernel Configuration +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_32BIT=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +# CONFIG_EPAPR_BOOT is not set +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="powerpc-linux-gnu-" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_DEFAULT_HOSTNAME="el-paso" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_SPARSE_IRQ=y + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y +CONFIG_PPC4xx_PCI_EXPRESS=y +# CONFIG_PPC4xx_MSI is not set +CONFIG_PPC_MSI_BITMAP=y +# CONFIG_PPC_XICS is not set +# CONFIG_PPC_ICP_NATIVE is not set +# CONFIG_PPC_ICP_HV is not set +# CONFIG_PPC_ICS_RTAS is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_PPC_47x=y +# CONFIG_BAMBOO is not set +# CONFIG_BLUESTONE is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +# CONFIG_ISS4xx is not set +# CONFIG_ICON is not set +CONFIG_ACP=y +# CONFIG_ACPISS is not set +# CONFIG_ACP_X1V1 is not set +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +CONFIG_PPC4xx_GPIO=y +CONFIG_440GP=y +# CONFIG_PPC_WSP is not set +# CONFIG_KVM_GUEST is not set +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_PPC_EPAPR_HV_PIC is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_MPIC_U3_HT_IRQS is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_P7_NAP is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +CONFIG_SIMPLE_GPIO=y + +# +# Kernel options +# +CONFIG_HIGHMEM=y +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_HOTPLUG_CPU=y +CONFIG_ARCH_CPU_PROBE_RELEASE=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_IRQ_ALL_CPUS is not set +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_STDBINUTILS=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_CMDLINE_BOOL is not set +CONFIG_EXTRA_TARGETS="" +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_RUNTIME is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +# CONFIG_NEED_DMA_MAP_STATE is not set +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_PPC4xx_CPM=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +CONFIG_HAS_RAPIDIO=y +CONFIG_RAPIDIO=y +# CONFIG_FSL_RIO is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +# CONFIG_RAPIDIO_ACP is not set +CONFIG_RAPIDIO_TSI57X=y +CONFIG_RAPIDIO_CPS_XX=y +CONFIG_RAPIDIO_TSI568=y +# CONFIG_RAPIDIO_CPS_GEN2 is not set +CONFIG_RAPIDIO_TSI500=y +CONFIG_RAPIDIO_DEBUG=y + +# +# Advanced setup +# +CONFIG_ADVANCED_OPTIONS=y +# CONFIG_LOWMEM_SIZE_BOOL is not set +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_RELOCATABLE=y +CONFIG_PAGE_OFFSET_BOOL=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0xc0400000 +CONFIG_PHYSICAL_START_BOOL=y +CONFIG_PHYSICAL_START=0x00400000 +CONFIG_TASK_SIZE_BOOL=y +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV6 is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_DEBUG_DRIVER=y +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_UB=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_BLK_DEV_ISS is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +# CONFIG_MD_RAID456 is not set +CONFIG_MD_MULTIPATH=y +CONFIG_MD_FAULTY=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_MIRROR=y +# CONFIG_DM_RAID is not set +# CONFIG_DM_LOG_USERSPACE is not set +CONFIG_DM_ZERO=y +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_MII=y +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +CONFIG_IBM_NEW_EMAC_ZMII=y +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_XILINX_EMACLITE is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_IP1000 is not set +CONFIG_IGB=y +CONFIG_IGBVF=y +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_STMMAC_ETH is not set +# CONFIG_PCH_GBE is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_AIRO is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +CONFIG_USB_ZD1201=y +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set + +# +# CAIF transport drivers +# +# CONFIG_RIONET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +CONFIG_PPPOE=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_NET_FC is not set +CONFIG_NETCONSOLE=y +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=20 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +CONFIG_N_GSM=y +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_XILINX is not set + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_STUB_POULSBO is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_XPS_USB_HCD_XILINX=y +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_CI13612_HCD=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +CONFIG_RTC_DRV_DS1742=y +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_GENERIC is not set +CONFIG_DMADEVICES=y +CONFIG_DMADEVICES_DEBUG=y +CONFIG_DMADEVICES_VDEBUG=y + +# +# DMA Devices +# +# CONFIG_TIMB_DMA is not set +CONFIG_LSI_DMA=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +CONFIG_DMATEST=m +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_STAGING is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set + +# +# LSI Drivers (APP3, APP3K, and ACP) +# +CONFIG_SERIAL_ACP=y +CONFIG_SERIAL_ACP_CONSOLE=y +# CONFIG_SERIAL_ACP_CONSOLE_POLL is not set +CONFIG_LSI_NET=y +CONFIG_LSI_NET_NUM_RX_DESC=16 +CONFIG_LSI_NET_RX_BUF_SZ=131072 +CONFIG_LSI_NET_NUM_TX_DESC=8 +CONFIG_LSI_NET_TX_BUF_SZ=65536 +CONFIG_LSI_NAND=y +CONFIG_LSI_UBOOTENV=y +CONFIG_LSI_PLX_PCIE_BRIDGE=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=m +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=m +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +CONFIG_NLS_CODEPAGE_865=y +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_VERBOSE=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +CONFIG_XMON=y +CONFIG_XMON_DEFAULT=y +CONFIG_XMON_DISASSEMBLY=y +CONFIG_DEBUGGER=y +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=y +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_CRYPTO_DEV_PPC4XX=y +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/acp_srio_defconfig b/arch/powerpc/configs/acp_srio_defconfig new file mode 100644 index 0000000..9e81676 --- /dev/null +++ b/arch/powerpc/configs/acp_srio_defconfig @@ -0,0 +1,1640 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35 +# Thu Jun 2 16:17:43 2011 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="powerpc-linux-" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set +CONFIG_PPC4xx_PCI_EXPRESS=y +CONFIG_PPC_MSI_BITMAP=y +# CONFIG_RAPIDIO_FSL is not set + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_PPC_47x=y +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +# CONFIG_ISS4xx is not set +# CONFIG_ICON is not set +CONFIG_ACP=y +# CONFIG_ACPISS is not set +# CONFIG_ACP_X1V1 is not set +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_440GP=y +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +CONFIG_HIGHMEM=y +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_IRQ_ALL_CPUS is not set +CONFIG_SPARSE_IRQ=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_STDBINUTILS=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_PROC_DEVICETREE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0 mtdparts=acp-nand:512K(2ndStage),512K(env-0),512K(env-1),512K(3rdStage),-(fs) ip=dhcp root=/dev/nfs" +CONFIG_EXTRA_TARGETS="" +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +# CONFIG_NEED_DMA_MAP_STATE is not set +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +CONFIG_HAS_RAPIDIO=y +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +# CONFIG_RAPIDIO_ACP is not set +CONFIG_RAPIDIO_TSI57X=y +CONFIG_RAPIDIO_CPS_XX=y +CONFIG_RAPIDIO_TSI568=y +CONFIG_RAPIDIO_TSI500=y +CONFIG_RAPIDIO_DEBUG=y + +# +# Advanced setup +# +CONFIG_ADVANCED_OPTIONS=y +# CONFIG_LOWMEM_SIZE_BOOL is not set +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_RELOCATABLE=y +CONFIG_PAGE_OFFSET_BOOL=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0xc0400000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE_BOOL=y +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_RPS=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_UB=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_BLK_DEV_ISS is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +# CONFIG_MD_RAID456 is not set +CONFIG_MD_MULTIPATH=y +CONFIG_MD_FAULTY=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_MIRROR=y +# CONFIG_DM_LOG_USERSPACE is not set +CONFIG_DM_ZERO=y +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC is not set +CONFIG_IBM_NEW_EMAC_ZMII=y +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_ATL2 is not set +# CONFIG_XILINX_EMACLITE is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_IP1000 is not set +CONFIG_IGB=y +CONFIG_IGBVF=y +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_AIRO is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +CONFIG_USB_ZD1201=y +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +# CONFIG_RIONET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +CONFIG_PPPOE=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_NET_FC is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_XILINX_XPS_PS2 is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_N_GSM=y +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=20 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_3M_PCT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CANDO is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MOSART is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_STANTUM is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_XPS_USB_HCD_XILINX=y +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_CI13612_HCD=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# LSI Drivers (APP3, APP3K, and ACP) +# +CONFIG_SERIAL_ACP=y +CONFIG_SERIAL_ACP_CONSOLE=y +# CONFIG_SERIAL_ACP_CONSOLE_POLL is not set +CONFIG_LSI_NET=y +CONFIG_LSI_NET_NUM_RX_DESC=16 +CONFIG_LSI_NET_RX_BUF_SZ=131072 +CONFIG_LSI_NET_NUM_TX_DESC=8 +CONFIG_LSI_NET_TX_BUF_SZ=65536 +CONFIG_LSI_NAND=y +CONFIG_LSI_UBOOTENV=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +CONFIG_NLS_CODEPAGE_865=y +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +CONFIG_XMON=y +CONFIG_XMON_DEFAULT=y +CONFIG_XMON_DISASSEMBLY=y +CONFIG_DEBUGGER=y +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=y +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_CRYPTO_DEV_PPC4XX=y +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/configs/acpiss_defconfig b/arch/powerpc/configs/acpiss_defconfig new file mode 100644 index 0000000..a9e909f --- /dev/null +++ b/arch/powerpc/configs/acpiss_defconfig @@ -0,0 +1,1054 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35 +# Wed Sep 14 11:18:14 2011 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="powerpc-linux-" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set +CONFIG_PPC4xx_PCI_EXPRESS=y + +# +# Platform support +# +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_PPC_47x=y +# CONFIG_BAMBOO is not set +# CONFIG_EBONY is not set +# CONFIG_SAM440EP is not set +# CONFIG_SEQUOIA is not set +# CONFIG_TAISHAN is not set +# CONFIG_KATMAI is not set +# CONFIG_RAINIER is not set +# CONFIG_WARP is not set +# CONFIG_ARCHES is not set +# CONFIG_CANYONLANDS is not set +# CONFIG_GLACIER is not set +# CONFIG_REDWOOD is not set +# CONFIG_EIGER is not set +# CONFIG_YOSEMITE is not set +# CONFIG_ISS4xx is not set +# CONFIG_ICON is not set +CONFIG_ACP=y +CONFIG_ACPISS=y +# CONFIG_ACP_X1V1 is not set +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +# CONFIG_PPC44x_SIMPLE is not set +# CONFIG_PPC4xx_GPIO is not set +CONFIG_440GP=y +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_FSL_ULI1575 is not set +CONFIG_OF_RTC=y +# CONFIG_SIMPLE_GPIO is not set + +# +# Kernel options +# +# CONFIG_HIGHMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_MATH_EMULATION=y +# CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_IRQ_ALL_CPUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_MAX_ACTIVE_REGIONS=32 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_STDBINUTILS=y +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_PROC_DEVICETREE=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="root=/dev/issblk3 rw mem=256M lpj=15990784" +CONFIG_EXTRA_TARGETS="" +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +# CONFIG_NEED_DMA_MAP_STATE is not set +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_4xx_SOC=y +CONFIG_PPC_PCI_CHOICE=y +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set +CONFIG_HAS_RAPIDIO=y +# CONFIG_RAPIDIO is not set + +# +# Advanced setup +# +CONFIG_ADVANCED_OPTIONS=y +# CONFIG_LOWMEM_SIZE_BOOL is not set +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_RELOCATABLE=y +CONFIG_PAGE_OFFSET_BOOL=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0xc0400000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_TASK_SIZE_BOOL=y +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_RPS=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_DEVICE=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=35000 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLK_DEV_ISS=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_IBM_NEW_EMAC_ZMII=y +CONFIG_NETDEV_1000=y +# CONFIG_MV643XX_ETH is not set +# CONFIG_XILINX_LL_TEMAC is not set +CONFIG_NETDEV_10000=y +CONFIG_WLAN=y +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_HVC_UDBG is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# LSI Drivers (APP3, APP3K, and ACP) +# +# CONFIG_SERIAL_ACP is not set +# CONFIG_LSI_NET is not set +# CONFIG_LSI_NAND is not set +# CONFIG_LSI_PLX_PCIE_BRIDGE is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_PPC_DISABLE_WERROR is not set +CONFIG_PPC_WERROR=y +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_XMON is not set +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index decad95..1e65560 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -71,6 +71,29 @@ #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif + +#ifdef CONFIG_PPC_47x +#define PPC476_ERR_DCBx() \ + BEGIN_FTR_SECTION; \ + lwsync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#define PPC476_ERR_MTPID PPC476_ERR_DCBx +#define PPC476_ERR_DCI() \ + BEGIN_FTR_SECTION; \ + dci; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1) +#define PPC476_ERR_ISYNC() \ + BEGIN_FTR_SECTION; \ + isync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#else /* ! CONFIG_PPC_47x */ +#define PPC476_ERR_DCBx() +#define PPC476_ERR_MTPID() +#define PPC476_ERR_DCI() +#define PPC476_ERR_ISYNC() +#endif /* CONFIG_PPC_47x */ + #endif + #endif /* _ASM_POWERPC_ASM_COMPAT_H */ diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index c0d842c..49c4c6a 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -158,6 +158,7 @@ extern const char *powerpc_base_platform; #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000) +#define CPU_FTR_476_DD1_1 CPU_FTR_DEBUG_LVL_EXC #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) @@ -168,6 +169,7 @@ extern const char *powerpc_base_platform; #define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000) #define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000) +#define CPU_FTR_476_DD1 ASM_CONST(0x0000000040000000) /* * Add the 64-bit processor unique features in the top half of the word; diff --git a/arch/powerpc/include/asm/dcr-native.h b/arch/powerpc/include/asm/dcr-native.h index 7d2e623..52e2ae7 100644 --- a/arch/powerpc/include/asm/dcr-native.h +++ b/arch/powerpc/include/asm/dcr-native.h @@ -50,15 +50,35 @@ extern unsigned int __mfdcr(unsigned int reg); static inline unsigned int mfdcrx(unsigned int reg) { unsigned int ret; - asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)" + asm volatile( +#ifdef CONFIG_PPC_47x + /* + * Workaround: move reg to an spr prior to mfdcrx instruction + */ + /* __stringify(BEGIN_FTR_SECTION) */ + "mtspr "__stringify(SPRN_SPRG_WSCRATCH_CRIT)",%1;" + /* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */ +#endif + ".long 0x7c000206 | (%0 << 21) | (%1 << 16)" : "=r" (ret) : "r" (reg)); return ret; } static inline void mtdcrx(unsigned int reg, unsigned int val) { - asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)" - : : "r" (val), "r" (reg)); + asm volatile( +#ifdef CONFIG_PPC_47x + /* + * Workaround: move reg to an spr prior to mtdcrx instruction. + * (Would love to get the FTR_SECTION macros working for + * inlined assembler -- shaggy) + */ + /* __stringify(BEGIN_FTR_SECTION) */ + "mtspr "__stringify(SPRN_SPRG_WSCRATCH_CRIT)",%1;" + /* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */ +#endif + ".long 0x7c000306 | (%0 << 21) | (%1 << 16)" + : : "r" (val), "r" (reg)); } #define mfdcr(rn) \ diff --git a/arch/powerpc/include/asm/lsi.h b/arch/powerpc/include/asm/lsi.h new file mode 100644 index 0000000..c2a3d44 --- /dev/null +++ b/arch/powerpc/include/asm/lsi.h @@ -0,0 +1,6 @@ +#ifndef __ASM_LSI_H +#define __ASM_LSI_H + +extern int acp_clock_get(int, unsigned long *); + +#endif diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index df18989..8cc514e 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -323,6 +323,8 @@ struct mpic #ifdef CONFIG_PM struct mpic_irq_save *save_data; #endif + + int cpu; }; /* diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index e472659..25e15a9 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -19,6 +19,10 @@ #define PPC_INST_DCBA 0x7c0005ec #define PPC_INST_DCBA_MASK 0xfc0007fe #define PPC_INST_DCBAL 0x7c2005ec +#define PPC_INST_DCBF 0x7c0000ac +#define PPC_INST_DCBF_MASK 0xfc0007fe +#define PPC_INST_DCBZ 0x7c0007ec +#define PPC_INST_DCBZ_MASK 0xfc0007fe #define PPC_INST_DCBZL 0x7c2007ec #define PPC_INST_ISEL 0x7c00001e #define PPC_INST_ISEL_MASK 0xfc00003e diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index c5cae0d..a1dcdb3 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -933,7 +933,8 @@ #define PVR_403GC 0x00200200 #define PVR_403GCX 0x00201400 #define PVR_405GP 0x40110000 -#define PVR_476 0x11a52000 +#define PVR_476 0x00050000 +#define PVR_476X2 0x11b22080 #define PVR_STB03XXX 0x40310000 #define PVR_NP405H 0x41410000 #define PVR_NP405L 0x41610000 diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 0f0ad9f..85aaed6 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -307,6 +307,8 @@ #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_POT1 0x20000000 /* 476 - IOCR1 trap */ +#define ESR_POT2 0x10000000 /* 476 - IOCR2 trap */ #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ #define ESR_PPR 0x04000000 /* Program Exception - Privileged */ #define ESR_PTR 0x02000000 /* Program Exception - Trap */ @@ -658,6 +660,14 @@ #define MMUBE1_VBE3 0x00000004 #define MMUBE1_VBE4 0x00000002 #define MMUBE1_VBE5 0x00000001 +#define SPRN_IOCCR 860 +#define IOCCR_IOCR1EN 0x80000000 +#define IOCCR_IOCR1M 0x40000000 +#define IOCCR_IOCR2EN 0x20000000 +#define IOCCR_IOCR2M 0x10000000 +#define SPRN_IOCR1 861 +#define SPRN_IOCR2 862 + #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h index f9611bd..3d783e6 100644 --- a/arch/powerpc/include/asm/spinlock.h +++ b/arch/powerpc/include/asm/spinlock.h @@ -109,16 +109,14 @@ extern void __rw_yield(arch_rwlock_t *lock); static inline void arch_spin_lock(arch_spinlock_t *lock) { CLEAR_IO_SYNC; - while (1) { - if (likely(__arch_spin_trylock(lock) == 0)) - break; - do { - HMT_low(); - if (SHARED_PROCESSOR) - __spin_yield(lock); - } while (unlikely(lock->slock != 0)); - HMT_medium(); - } + if (likely(__arch_spin_trylock(lock) == 0)) + return; + do { + HMT_low(); + if (SHARED_PROCESSOR) + __spin_yield(lock); + } while (unlikely(__arch_spin_trylock(lock) != 0)); + HMT_medium(); } static inline @@ -132,11 +130,9 @@ void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags) break; local_save_flags(flags_dis); local_irq_restore(flags); - do { - HMT_low(); - if (SHARED_PROCESSOR) - __spin_yield(lock); - } while (unlikely(lock->slock != 0)); + HMT_low(); + if (SHARED_PROCESSOR) + __spin_yield(lock); HMT_medium(); local_irq_restore(flags_dis); } @@ -229,28 +225,20 @@ static inline long __arch_write_trylock(arch_rwlock_t *rw) static inline void arch_read_lock(arch_rwlock_t *rw) { - while (1) { - if (likely(__arch_read_trylock(rw) > 0)) - break; - do { - HMT_low(); - if (SHARED_PROCESSOR) - __rw_yield(rw); - } while (unlikely(rw->lock < 0)); + while (unlikely(__arch_read_trylock(rw) <= 0)) { + HMT_low(); + if (SHARED_PROCESSOR) + __rw_yield(rw); HMT_medium(); } } static inline void arch_write_lock(arch_rwlock_t *rw) { - while (1) { - if (likely(__arch_write_trylock(rw) == 0)) - break; - do { - HMT_low(); - if (SHARED_PROCESSOR) - __rw_yield(rw); - } while (unlikely(rw->lock != 0)); + while (unlikely(__arch_write_trylock(rw) != 0)) { + HMT_low(); + if (SHARED_PROCESSOR) + __rw_yield(rw); HMT_medium(); } } diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 9fb9332..7096cc1 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -8,6 +8,8 @@ * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com */ #include @@ -1816,9 +1818,35 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_440A, .platform = "ppc440", }, + { /* 476 DD1 core - needs DD1.1 feature as well */ + .pvr_mask = 0x800fffff, + .pvr_value = 0x11a50000, + .cpu_name = "476 DD1", + .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1 | + CPU_FTR_476_DD1_1 | CPU_FTR_FPU_UNAVAILABLE, + .cpu_user_features = COMMON_USER_BOOKE, + .mmu_features = MMU_FTR_TYPE_47x, + .icache_bsize = 32, + .dcache_bsize = 128, + .machine_check = machine_check_47x, + .platform = "ppc470", + }, + { /* 476 DD1.1 core */ + .pvr_mask = 0x800fffff, + .pvr_value = 0x00052040, + .cpu_name = "476", + .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1_1 | + CPU_FTR_FPU_UNAVAILABLE, + .cpu_user_features = COMMON_USER_BOOKE, + .mmu_features = MMU_FTR_TYPE_47x, + .icache_bsize = 32, + .dcache_bsize = 128, + .machine_check = machine_check_47x, + .platform = "ppc470", + }, { /* 476 DD2 core */ - .pvr_mask = 0xffffffff, - .pvr_value = 0x11a52080, + .pvr_mask = 0x800fffff, + .pvr_value = 0x00052080, .cpu_name = "476", .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, .cpu_user_features = COMMON_USER_BOOKE | @@ -1833,7 +1861,7 @@ static struct cpu_spec __initdata cpu_specs[] = { { /* 476 iss */ .pvr_mask = 0xffff0000, .pvr_value = 0x00050000, - .cpu_name = "476", + .cpu_name = "476 ISS", .cpu_features = CPU_FTRS_47X, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 56212bc..49e40c5 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -143,6 +143,12 @@ transfer_to_handler: addi r2,r12,-THREAD tovirt(r2,r2) /* set r2 to current */ beq 2f /* if from user, fix up THREAD.regs */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ addi r11,r1,STACK_FRAME_OVERHEAD stw r11,PT_REGS(r12) #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) @@ -281,6 +287,12 @@ stack_ovf: 0: _GLOBAL(DoSyscall) +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ stw r3,ORIG_GPR3(r1) li r12,0 stw r12,RESULT(r1) @@ -382,6 +394,16 @@ BEGIN_MMU_FTR_SECTION 1: END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x) #endif /* CONFIG_44x */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + lwz r7,_MSR(r1) + andi. r5,r7,MSR_PR + beq 11f + lis r4,(IOCCR_IOCR1EN|IOCCR_IOCR2EN)@h + mtspr SPRN_IOCCR,r4 +11: +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ BEGIN_FTR_SECTION lwarx r7,0,r1 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) @@ -717,7 +739,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE) fast_exception_return: #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) andi. r10,r9,MSR_RI /* check for recoverable interrupt */ - beq 1f /* if not, we've got problems */ + beq try_recov_exception /* if not, we've got problems */ #endif 2: REST_4GPRS(3, r11) @@ -737,7 +759,8 @@ fast_exception_return: #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) /* check if the exception happened in a restartable section */ -1: lis r3,exc_exit_restart_end@ha +try_recov_exception: + lis r3,exc_exit_restart_end@ha addi r3,r3,exc_exit_restart_end@l cmplw r12,r3 bge 3f @@ -811,6 +834,14 @@ restore_user: bnel- load_dbcr0 #endif +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + lis r0,(IOCCR_IOCR1EN|IOCCR_IOCR2EN)@h + mtspr SPRN_IOCCR,r0 +1: +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ + #ifdef CONFIG_PREEMPT b restore diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index a0bf158..c8e38c8 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -164,7 +164,8 @@ */ #define START_EXCEPTION(label) \ .align 5; \ -label: +label: \ + PPC476_ERR_ISYNC() #define FINISH_EXCEPTION(func) \ bl transfer_to_handler_full; \ @@ -173,12 +174,14 @@ label: #define EXCEPTION(n, label, hdlr, xfer) \ START_EXCEPTION(label); \ + PPC476_ERR_DCI(); \ NORMAL_EXCEPTION_PROLOG; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ xfer(n, hdlr) #define CRITICAL_EXCEPTION(n, label, hdlr) \ START_EXCEPTION(label); \ + PPC476_ERR_DCI(); \ CRITICAL_EXCEPTION_PROLOG; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ @@ -378,6 +381,7 @@ label: #define DECREMENTER_EXCEPTION \ START_EXCEPTION(Decrementer) \ + PPC476_ERR_DCI(); \ NORMAL_EXCEPTION_PROLOG; \ lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 998a100..88c1793 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -392,7 +392,10 @@ _GLOBAL(flush_dcache_range) beqlr mtctr r4 -1: dcbf 0,r3 +1: PPC476_ERR_DCBx() + dcbf 0,r3 + PPC476_ERR_DCBx() + addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ @@ -506,7 +509,9 @@ _GLOBAL(clear_pages) li r0,PAGE_SIZE/L1_CACHE_BYTES slw r0,r0,r4 mtctr r0 -1: dcbz 0,r3 +1: PPC476_ERR_DCBx() + dcbz 0,r3 + PPC476_ERR_DCBx() addi r3,r3,L1_CACHE_BYTES bdnz 1b blr @@ -550,7 +555,9 @@ _GLOBAL(copy_page) mtctr r0 1: dcbt r11,r4 + PPC476_ERR_DCBx() dcbz r5,r3 + PPC476_ERR_DCBx() COPY_16_BYTES #if L1_CACHE_BYTES >= 32 COPY_16_BYTES @@ -837,3 +844,25 @@ relocate_new_kernel_end: relocate_new_kernel_size: .long relocate_new_kernel_end - relocate_new_kernel #endif + +#ifdef CONFIG_PPC_47x +_GLOBAL(__dcbf) + lwsync +1: dcbf 0,r3 + lwsync + li r3,0 + blr +_GLOBAL(__dcbz) + lwsync +2: dcbz 0,r3 + lwsync + li r3,0 + blr +3: li r3,-EFAULT + blr + .section __ex_table,"a" + .align 2 + .long 1b,3b + .long 2b,3b + .text +#endif /* CONFIG_PPC_47x */ diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index e89df59..6238a0d 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -631,3 +631,25 @@ _GLOBAL(kexec_sequence) li r5,0 blr /* image->start(physid, image->start, 0); */ #endif /* CONFIG_KEXEC */ + +#ifdef CONFIG_PPC_47x +_GLOBAL(__dcbf) + lwsync +1: dcbf 0,r3 + lwsync + li r3,0 + blr +_GLOBAL(__dcbz) + lwsync +2: dcbz 0,r3 + lwsync + li r3,0 + blr +3: li r3,-EFAULT + blr + .section __ex_table,"a" + .align 2 + .long 1b,3b + .long 2b,3b + .text +#endif /* CONFIG_PPC_47x */ diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 8ebc670..fae9a08 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -13,6 +13,8 @@ * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com */ #undef DEBUG @@ -357,6 +359,9 @@ int generic_cpu_disable(void) { unsigned int cpu = smp_processor_id(); +#ifdef CONFIG_ACP + printk("%s:%d - cpu=%u\n", __FILE__, __LINE__, cpu); +#endif if (cpu == boot_cpuid) return -EBUSY; @@ -493,9 +498,15 @@ int __cpuinit __cpu_up(unsigned int cpu) * use this value that I found through experimentation. * -- Cort */ - if (system_state < SYSTEM_RUNNING) + if (system_state < SYSTEM_RUNNING) { +#ifndef CONFIG_ACPISS for (c = 50000; c && !cpu_callin_map[cpu]; c--) udelay(100); +#else /* CONFIG_ACPISS */ + for (c = 500; c && !cpu_callin_map[cpu]; c--) + udelay(10); +#endif /* CONFIG_ACPISS */ + } #ifdef CONFIG_HOTPLUG_CPU else /* diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 1a01414..f404950 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -866,6 +866,31 @@ static int emulate_isel(struct pt_regs *regs, u32 instword) return 0; } +#ifdef CONFIG_PPC_47x + +extern int __dcbf(unsigned long ea); +extern int __dcbz(unsigned long ea); + +static int emulate_dcbf(struct pt_regs *regs, u32 instword) +{ + u8 rA = (instword >> 16) & 0x1f; + u8 rB = (instword >> 11) & 0x1f; + unsigned long ea = regs->gpr[rB] + ((rA == 0) ? 0 : regs->gpr[rA]); + + return __dcbf(ea); +} + +static int emulate_dcbz(struct pt_regs *regs, u32 instword) +{ + u8 rA = (instword >> 16) & 0x1f; + u8 rB = (instword >> 11) & 0x1f; + unsigned long ea = regs->gpr[rB] + ((rA == 0) ? 0 : regs->gpr[rA]); + + return __dcbz(ea); +} + +#endif /* CONFIG_PPC_47x */ + static int emulate_instruction(struct pt_regs *regs) { u32 instword; @@ -941,6 +966,18 @@ static int emulate_instruction(struct pt_regs *regs) } #endif +#ifdef CONFIG_PPC_47x + /* Emulate dcbf instruction */ + if ((instword & PPC_INST_DCBF_MASK) == PPC_INST_DCBF) { + return emulate_dcbf(regs, instword); + } + + /* Emulate dcbz instruction */ + if ((instword & PPC_INST_DCBZ_MASK) == PPC_INST_DCBZ) { + return emulate_dcbz(regs, instword); + } +#endif /* CONFIG_47x */ + return -EINVAL; } @@ -956,6 +993,14 @@ void __kprobes program_check_exception(struct pt_regs *regs) /* We can now get here via a FP Unavailable exception if the core * has no FPU, in that case the reason flags will be 0 */ +#ifdef CONFIG_PPC_47x + /* Make IOC instruction traps look like illegal instructions + * so we hit the proper emulation code path + */ + if (mmu_has_feature(MMU_FTR_TYPE_47x) && + (reason & (ESR_POT1 | ESR_POT2))) + reason |= ESR_PIL; +#endif /* CONFIG_PPC_47x */ if (reason & REASON_FP) { /* IEEE FP exception */ diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c index 23d65ab..2f5a3f4 100644 --- a/arch/powerpc/kernel/udbg.c +++ b/arch/powerpc/kernel/udbg.c @@ -7,6 +7,8 @@ * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com */ #include diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c index 6837f83..9470841 100644 --- a/arch/powerpc/kernel/udbg_16550.c +++ b/arch/powerpc/kernel/udbg_16550.c @@ -3,11 +3,108 @@ * * Copyright (C) 2001-2005 PPC 64 Team, IBM Corp * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com */ + +#if defined(CONFIG_ACP) && !defined(CONFIG_ACPISS) + +#include +#include + +/* + ====================================================================== + ====================================================================== + serial + ====================================================================== + ====================================================================== +*/ + +static void *uart_base; + +#define UART_DR 0x00 +#define UART_FR 0x18 +#define UART_IBRD 0x24 +#define UART_FBRD 0x28 +#define UART_LCR_H 0x2c +#define UART_CR 0x30 +#define UART_IFLS 0x34 +#define UART_IMSC 0x38 +#define UART_ECR 0x04 + +#define FR_RXFE 0x10 +#define FR_TXFF 0x20 + +#if defined(CONFIG_PPC_EARLY_DEBUG_44x) || defined(CONFIG_ACPISS) +static void +acp_putc(char c) +{ + while (0 != (in_le32(uart_base + UART_FR) & FR_TXFF)) + ; + + if ('\n' == c) { + out_le32(uart_base + UART_DR, '\r'); + while (0 != (in_le32(uart_base + UART_FR) & FR_TXFF)) + ; + } + + out_le32(uart_base + UART_DR, c); + + return; +} + +static int +acp_getc(void) +{ + while (0 != (in_le32(uart_base + UART_FR) & FR_RXFE)) + ; + return in_le32(uart_base + UART_DR); +} +#endif + +unsigned int +udbg_probe_uart_speed(void __iomem *comport, unsigned int clock) +{ + return 9600; +} + +void +udbg_init_uart(void __iomem *comport, unsigned int speed, unsigned int clock) +{ + out_le32(uart_base + UART_IFLS, 0); + out_le32(uart_base + UART_IMSC, 0x700); + out_le32(uart_base + UART_ECR, 0); + + return; +} + +void __init +udbg_init_44x_as1(void) +{ +#if defined(CONFIG_ACPISS) + uart_base = (void *)0xf0004000; + udbg_putc = acp_putc; + udbg_getc = acp_getc; +#elif defined(CONFIG_PPC_EARLY_DEBUG_44x) + unsigned long long uart_phys_address; + + uart_phys_address = + ((unsigned long long)CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH << 32) | + (unsigned long long)CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW; + uart_base = ioremap(uart_phys_address, 0x1000); + udbg_putc = acp_putc; + udbg_getc = acp_getc; +#endif + + return; +} + +#else + #include #include #include @@ -36,14 +133,14 @@ struct NS16550 { #define dlm ier #define dlab lcr -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ #define LSR_THRE 0x20 /* Xmit holding register empty */ #define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ +#define LSR_ERR 0x80 /* Error */ #define LCR_DLAB 0x80 @@ -220,6 +317,17 @@ void udbg_init_pas_realmode(void) #ifdef CONFIG_PPC_EARLY_DEBUG_44x #include +static unsigned long udbg_44x_comport = PPC44x_EARLY_DEBUG_VIRTADDR; + +static int __init early_parse_comport(char *p) +{ + if (!p || !(*p)) + return 0; + udbg_44x_comport = simple_strtoul(p, 0, 16); + return 0; +} +early_param("uart_addr", early_parse_comport); + static void udbg_44x_as1_flush(void) { if (udbg_comport) { @@ -251,7 +359,7 @@ static int udbg_44x_as1_getc(void) void __init udbg_init_44x_as1(void) { udbg_comport = - (struct NS16550 __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR; + (struct NS16550 __iomem *)udbg_44x_comport; udbg_putc = udbg_44x_as1_putc; udbg_flush = udbg_44x_as1_flush; @@ -349,3 +457,5 @@ void __init udbg_init_wsp(void) udbg_getc_poll = udbg_wsp_getc_poll; } #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */ + +#endif diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index 55f19f9..b47a0f6 100644 --- a/arch/powerpc/lib/copy_32.S +++ b/arch/powerpc/lib/copy_32.S @@ -12,6 +12,7 @@ #include #include #include +#include #define COPY_16_BYTES \ lwz r7,4(r4); \ @@ -98,7 +99,9 @@ _GLOBAL(cacheable_memzero) bdnz 4b 3: mtctr r9 li r7,4 -10: dcbz r7,r6 +10: PPC476_ERR_DCBx() + dcbz r7,r6 + PPC476_ERR_DCBx() addi r6,r6,CACHELINE_BYTES bdnz 10b clrlwi r5,r8,32-LG_CACHELINE_BYTES @@ -368,7 +371,9 @@ _GLOBAL(__copy_tofrom_user) mtctr r8 53: dcbt r3,r4 + PPC476_ERR_DCBx() 54: dcbz r11,r6 + PPC476_ERR_DCBx() .section __ex_table,"a" .align 2 .long 54b,105f diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c index 024acab..c16d796 100644 --- a/arch/powerpc/mm/44x_mmu.c +++ b/arch/powerpc/mm/44x_mmu.c @@ -78,11 +78,7 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys) "tlbwe %1,%3,%5\n" "tlbwe %0,%3,%6\n" : -#ifdef CONFIG_PPC47x - : "r" (PPC47x_TLB2_S_RWX), -#else : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), -#endif "r" (phys), "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M), "r" (entry), diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c index 5de0f25..960b9cc 100644 --- a/arch/powerpc/mm/init_32.c +++ b/arch/powerpc/mm/init_32.c @@ -141,6 +141,11 @@ void __init MMU_init(void) * entries, so we need to adjust lowmem to match the amount we can map * in the fixed entries */ adjust_total_lowmem(); +#elif CONFIG_PPC_47x && CONFIG_RELOCATABLE + /* + * FIXME: Probably not the safest calculation, but it works for now + */ +/* __initial_memory_limit_addr += memstart_addr; */ #endif /* CONFIG_FSL_BOOKE */ if (total_lowmem > __max_low_memory) { diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig index e958b6f..e187e4a 100644 --- a/arch/powerpc/platforms/44x/Kconfig +++ b/arch/powerpc/platforms/44x/Kconfig @@ -197,6 +197,32 @@ config ICON help This option enables support for the AMCC PPC440SPe evaluation board. +config ACP + bool "Support for LSI's ACP Platform" + depends on (44x || 40x) + select PPC4xx_PCI_EXPRESS + default n + select 440GP + select PPC_FPU + select HAS_RAPIDIO + +config ACPISS + bool "ACP on the ISS 4xx Simulator" + depends on ACP + default n + select OF_RTC + help + This option enables support for the ACP on the IBM ISS + simulation environment + +config ACP_X1V1 + bool "ACP, X1V1 Version" + depends on ACP + default n + select HAS_RAPIDIO + help + Workarounds for the X1V1 version of the ACP. + #config LUAN # bool "Luan" # depends on 44x diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile index 553db60..d3388ed 100644 --- a/arch/powerpc/platforms/44x/Makefile +++ b/arch/powerpc/platforms/44x/Makefile @@ -10,3 +10,5 @@ obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o obj-$(CONFIG_ISS4xx) += iss4xx.o obj-$(CONFIG_CANYONLANDS)+= canyonlands.o +obj-$(CONFIG_ACPISS) += iss4xx.o +obj-$(CONFIG_ACP) += acpx1.o diff --git a/arch/powerpc/platforms/44x/acpx1.c b/arch/powerpc/platforms/44x/acpx1.c new file mode 100644 index 0000000..85d4059 --- /dev/null +++ b/arch/powerpc/platforms/44x/acpx1.c @@ -0,0 +1,182 @@ +/* + * PPC476 board specific routines + * + * Copyright 2009 Torez Smith, IBM Corporation. + * + * Based on earlier code: + * Matt Porter + * Copyright 2002-2005 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003-2005 Zultys Technologies + * + * Rewritten and ported to the merged powerpc tree: + * Copyright 2007 David Gibson , IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static __initdata struct of_device_id acpx14xx_of_bus[] = { + { .compatible = "ibm,plb4", }, + { .compatible = "ibm,plb6", }, + { .compatible = "ibm,opb", }, + { .compatible = "ibm,ebc", }, + { .compatible = "acp,rapidio-delta", }, + {}, +}; + +static __initdata struct of_device_id acp_rtc[] = { + { .compatible = "ds1743-nvram", }, + {} +}; + + +static int __init acpx14xx_device_probe(void) +{ + struct device_node *child; + + of_platform_bus_probe(NULL, acpx14xx_of_bus, NULL); + + for_each_child_of_node(of_find_node_by_path("/"), child) { + if (of_match_node(acp_rtc, child)) { + of_platform_device_create(child, "rtc", NULL); + } + } + + return 0; +} +machine_device_initcall(acpx14xx, acpx14xx_device_probe); + +/* We can have either UICs or MPICs */ +static void __init acpx14xx_init_irq(void) +{ + struct device_node *np; + + /* Find top level interrupt controller */ + for_each_node_with_property(np, "interrupt-controller") { + if (of_get_property(np, "interrupts", NULL) == NULL) + break; + } + if (np == NULL) + panic("Can't find top level interrupt controller"); + + /* Check type and do appropriate initialization */ + if (of_device_is_compatible(np, "chrp,open-pic")) { + /* The MPIC driver will get everything it needs from the + * device-tree, just pass 0 to all arguments + */ + struct mpic *mpic = + mpic_alloc(np, 0, MPIC_PRIMARY, 0, 0, " MPIC "); + BUG_ON(mpic == NULL); + mpic_init(mpic); + ppc_md.get_irq = mpic_get_irq; + } else + panic("Unrecognized top level interrupt controller"); +} + +#ifdef CONFIG_SMP +static void __cpuinit smp_acpx14xx_setup_cpu(int cpu) +{ + mpic_setup_this_cpu(); +} + +static int __cpuinit smp_acpx14xx_kick_cpu(int cpu) +{ + struct device_node *cpunode = of_get_cpu_node(cpu, NULL); + const u64 *spin_table_addr_prop; + u32 *spin_table; + extern void start_secondary_47x(void); + + BUG_ON(cpunode == NULL); + + /* Assume spin table. We could test for the enable-method in + * the device-tree but currently there's little point as it's + * our only supported method + */ + spin_table_addr_prop = + of_get_property(cpunode, "cpu-release-addr", NULL); + + if (spin_table_addr_prop == NULL) { + pr_err("CPU%d: Can't start, macpx1ing cpu-release-addr !\n", + cpu); + return -ENOSYS; + } + + /* Assume it's mapped as part of the linear mapping. This is a bit + * fishy but will work fine for now + */ + spin_table = (u32 *)__va(*spin_table_addr_prop); + pr_debug("CPU%d: Spin table mapped at %p\n", cpu, spin_table); + + spin_table[3] = cpu; + smp_wmb(); + spin_table[1] = __pa(start_secondary_47x); + mb(); + + return 0; +} + +static struct smp_ops_t acpx1_smp_ops = { + .probe = smp_mpic_probe, + .message_pass = smp_mpic_message_pass, + .setup_cpu = smp_acpx14xx_setup_cpu, + .kick_cpu = smp_acpx14xx_kick_cpu, + .give_timebase = smp_generic_give_timebase, + .take_timebase = smp_generic_take_timebase, +}; + +static void __init acpx14xx_smp_init(void) +{ + if (mmu_has_feature(MMU_FTR_TYPE_47x)) + smp_ops = &acpx1_smp_ops; +} + +#else /* CONFIG_SMP */ +static void __init acpx14xx_smp_init(void) { } +#endif /* CONFIG_SMP */ + +static void __init acpx14xx_setup_arch(void) +{ + acpx14xx_smp_init(); +} + +/* + * Called very early, MMU is off, device-tree isn't unflattened + */ +static int __init acpx14xx_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (!of_flat_dt_is_compatible(root, "ibm,acpx1-4xx")) + return 0; + + return 1; +} + +define_machine(acpx14xx) { + .name = "ACPX1", + .probe = acpx14xx_probe, + .progress = udbg_progress, + .init_IRQ = acpx14xx_init_irq, + .setup_arch = acpx14xx_setup_arch, + .restart = ppc4xx_reset_system, + .calibrate_decr = generic_calibrate_decr, +}; diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 58d7a53..862bf7b 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -155,7 +155,7 @@ static inline unsigned int mpic_processor_id(struct mpic *mpic) unsigned int cpu = 0; if (mpic->flags & MPIC_PRIMARY) - cpu = hard_smp_processor_id(); + cpu = raw_smp_processor_id(); return cpu; } @@ -340,6 +340,15 @@ static inline void mpic_map(struct mpic *mpic, struct device_node *node, #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) #endif /* !CONFIG_PPC_DCR */ +static inline void mpic_init_vector(struct mpic *mpic, int source) +{ + /* start with vector = source number, and masked */ + u32 vecpri = MPIC_VECPRI_MASK | source | (8 << MPIC_VECPRI_PRIORITY_SHIFT); + + /* init hw */ + mpic_irq_write(source, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); + mpic_irq_write(source, MPIC_INFO(IRQ_DESTINATION), 1 << mpic->cpu); +} /* Check if we have one of those nice broken MPICs with a flipped endian on @@ -701,6 +710,14 @@ static inline void mpic_eoi(struct mpic *mpic) * Linux descriptor level callbacks */ +/* Determine if the linux irq is a timer interrupt */ +static unsigned int mpic_is_timer_interrupt(struct mpic *mpic, unsigned int irq) +{ + unsigned int src = virq_to_hw(irq); + + return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[3]); +} + void mpic_unmask_irq(struct irq_data *d) { @@ -1051,6 +1068,15 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, if (hw >= mpic->irq_count) return -EINVAL; + /* If the MPIC was reset, then all vectors have already been + * initialized. Otherwise, the appropriate vector needs to be + * initialized here to ensure that only used sources are setup with + * a vector. + */ + if (mpic->flags & MPIC_NO_RESET) + if (!(mpic_is_ipi(mpic, hw) || mpic_is_timer_interrupt(mpic, hw))) + mpic_init_vector(mpic, hw); + mpic_msi_reserve_hwirq(mpic, hw); /* Default chip */ @@ -1417,8 +1443,7 @@ void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) void __init mpic_init(struct mpic *mpic) { - int i; - int cpu; + int i, cpu; BUG_ON(mpic->num_sources == 0); diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c index d3d6ce3..76f423c 100644 --- a/arch/powerpc/sysdev/ppc4xx_soc.c +++ b/arch/powerpc/sysdev/ppc4xx_soc.c @@ -20,10 +20,14 @@ #include #include #include +#include #include #include #include +#ifdef CONFIG_ACP +#include +#endif static u32 dcrbase_l2c; @@ -190,6 +194,48 @@ static int __init ppc4xx_l2c_probe(void) } arch_initcall(ppc4xx_l2c_probe); +#ifdef CONFIG_ACP + +static int restart_mode = 0; + +/* + * Issue a "core" reset. + */ + +void +acp_jump_to_boot_loader(void *input) +{ + mpic_teardown_this_cpu(0); + /* This is only valid in the "core" reset case, so 0x10000000. */ + mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | 0x10000000); + + while (1) + ; /* Just in case the jump fails. */ +} + +/* + * Get all other cores to run "acp_jump_to_boot_loader()" then go + * there as well. + */ + +void +acp_reset_cores(void) +{ + int cpu; + + for_each_possible_cpu(cpu) { + if (cpu != smp_processor_id()) + smp_call_function_single(cpu, acp_jump_to_boot_loader, + NULL, 0); + } + + acp_jump_to_boot_loader(NULL); +} + + +#endif + + /* * Apply a system reset. Alternatively a board specific value may be * provided via the "reset-type" property in the cpu node. @@ -214,8 +260,52 @@ void ppc4xx_reset_system(char *cmd) reset_type = prop[0] << 28; } +#ifdef CONFIG_ACP + if (restart_mode) /* cold reset */ + reset_type = DBCR0_RST_SYSTEM; + printk(KERN_DEBUG"Resetting using '%s' mode\n", restart_mode ? "cold" : "warm"); + + if (DBCR0_RST_CORE == reset_type) { + acp_reset_cores(); + } else { + mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | reset_type); + } +#else mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | reset_type); +#endif while (1) ; /* Just in case the reset doesn't work */ } + +#ifdef CONFIG_ACP +static ssize_t restart_mode_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", restart_mode ? "cold" : "warm"); +} + +static ssize_t restart_mode_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + if (strncmp(buf, "cold", min_t(int, n, 4)) == 0) + restart_mode = 1; + else if (strncmp(buf, "warm", min_t(int, n, 4)) == 0) + restart_mode = 0; + else + return -EINVAL; + return n; +} + +static struct kobj_attribute restart_mode_attr = + __ATTR(restart_mode, 0600, restart_mode_show, restart_mode_store); + +static int __init restart_mode_sysfs(void) +{ + extern struct kobject *power_kobj; + return sysfs_create_file(power_kobj, &restart_mode_attr.attr); +} + +late_initcall(restart_mode_sysfs); +#endif diff --git a/drivers/Kconfig b/drivers/Kconfig index 3bb154d..ff5f578 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -126,4 +126,6 @@ source "drivers/hwspinlock/Kconfig" source "drivers/clocksource/Kconfig" +source "drivers/lsi/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 09f3232..5444771 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -116,6 +116,8 @@ obj-$(CONFIG_BCMA) += bcma/ obj-$(CONFIG_VHOST_NET) += vhost/ obj-$(CONFIG_VLYNQ) += vlynq/ obj-$(CONFIG_STAGING) += staging/ +obj-$(CONFIG_ACPISS) += lsi/ +obj-$(CONFIG_ACP) += lsi/ obj-y += platform/ obj-y += ieee802154/ #common clk code diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 717d6e4..5812725 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -383,6 +383,10 @@ config BLK_DEV_XIP will prevent RAM block device backing store memory from being allocated from highmem (only a problem for highmem systems). +config BLK_DEV_ISS + bool "Support ISS Simulator Block Device" + default n + config CDROM_PKTCDVD tristate "Packet writing on CD/DVD media" depends on !UML diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 76646e9..ab74aa6 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_VIODASD) += viodasd.o obj-$(CONFIG_BLK_DEV_SX8) += sx8.o obj-$(CONFIG_BLK_DEV_UB) += ub.o obj-$(CONFIG_BLK_DEV_HD) += hd.o +obj-$(CONFIG_BLK_DEV_ISS) += iss_blk.o obj-$(CONFIG_XEN_BLKDEV_FRONTEND) += xen-blkfront.o obj-$(CONFIG_XEN_BLKDEV_BACKEND) += xen-blkback/ diff --git a/drivers/block/iss_blk.c b/drivers/block/iss_blk.c new file mode 100644 index 0000000..be9128d --- /dev/null +++ b/drivers/block/iss_blk.c @@ -0,0 +1,394 @@ +/* + * PPC476 board specific routines + * + * Copyright 2009 Torez Smith, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * Simple block device for the ISS simulator + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MAJOR_NR 63 /* FIXME */ +#define NUM_ISS_BLK_MINOR 4 + +/* Command codes */ +enum { + ISS_BD_CMD_NOP = 0, + ISS_BD_CMD_OPEN = 1, + ISS_BD_CMD_CLOSE = 2, + ISS_BD_CMD_READ = 3, + ISS_BD_CMD_WRITE = 4, + ISS_BD_CMD_STATUS = 5, + ISS_BD_CMD_CHKCHANGE = 6, + ISS_BD_CMD_SYNC = 7, + ISS_BD_CMD_GET_BLKSIZE = 8, + ISS_BD_CMD_GET_DEVSIZE = 9, +}; + +/* Status codes */ +enum { + ISS_BD_STATUS_OK = 0, + ISS_BD_STATUS_OP_ER = 1, /* Open error */ + ISS_BD_ALREADY_OPEN = 2, /* Block file already open */ + ISS_BD_NOT_OPEN = 3, /* Block file not open */ + ISS_BD_BAD_DEV_NUM = 4, /* Bad device number */ + ISS_BD_BAD_SEC_CNT = 5, /* Bad sector number */ + ISS_BD_SEEK_ERROR = 6, /* Bad sector count */ + ISS_BD_RW_ERROR = 7, /* Read/Write error */ + ISS_BD_SIZE_ERROR = 8, /* Unable to determine file size */ + ISS_BD_FILE_CHANGED = 9, /* Media has changed */ +}; + +struct iss_blk_regs { + u8 cmd; + u8 pad0[3]; + u32 stat; + u32 sector; + u32 count; + u32 devno; + u32 size; + u8 pad1[0x1e8]; + u8 data[0x800]; +}; + +struct iss_blk { + struct gendisk *disk; + unsigned int devno; + unsigned int sectsize; + unsigned int capacity; + unsigned int present; + unsigned int changed; +} iss_blks[NUM_ISS_BLK_MINOR]; + +static spinlock_t iss_blk_qlock; +static spinlock_t iss_blk_reglock; +static struct iss_blk_regs __iomem *iss_blk_regs; + +struct request *iss_req; +static bool iss_end_request(int err) +{ + unsigned int bytes = blk_rq_cur_bytes(iss_req); + + if (__blk_end_request(iss_req, err, bytes)) + return true; + iss_req = NULL; + return false; +} + +static void iss_blk_setup(struct iss_blk *ib) +{ + unsigned long flags; + u32 stat; + + pr_debug("iss_blk_setup %d\n", ib->devno); + + spin_lock_irqsave(&iss_blk_reglock, flags); + out_8(iss_blk_regs->data, 0); + out_be32(&iss_blk_regs->devno, ib->devno); + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_OPEN); + stat = in_be32(&iss_blk_regs->stat); + if (stat != ISS_BD_STATUS_OK) { + pr_debug(" -> no file\n"); + goto failed; + } + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_GET_BLKSIZE); + ib->sectsize = in_be32(&iss_blk_regs->size); + if (ib->sectsize != 512) { + pr_err("issblk: unsupported sector size %d\n", ib->sectsize); + goto failed; + } + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_GET_DEVSIZE); + ib->capacity = in_be32(&iss_blk_regs->size); + ib->present = 1; + ib->changed = 0; + spin_unlock_irqrestore(&iss_blk_reglock, flags); + + pr_debug(" -> 0x%x sectors 0f %d bytes\n", + ib->capacity, ib->sectsize); + + blk_queue_bounce_limit(ib->disk->queue, BLK_BOUNCE_HIGH); + blk_queue_logical_block_size(ib->disk->queue, ib->sectsize); + set_capacity(ib->disk, ib->capacity); + return; + + failed: + spin_unlock_irqrestore(&iss_blk_reglock, flags); +} + +static int __iss_blk_read(struct iss_blk *ib, void *buffer, + unsigned long sector, unsigned long count) +{ + unsigned long lcount, flags; + u32 stat; + + pr_debug("__iss_blk_read 0x%ld sectors @ 0x%lx\n", count, sector); + + while (count) { + lcount = min(count, 4ul); + spin_lock_irqsave(&iss_blk_reglock, flags); + out_be32(&iss_blk_regs->devno, ib->devno); + out_be32(&iss_blk_regs->sector, sector); + out_be32(&iss_blk_regs->count, lcount); + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_READ); + stat = in_be32(&iss_blk_regs->stat); + if (stat != ISS_BD_STATUS_OK) { + spin_unlock_irqrestore(&iss_blk_reglock, flags); + return -EIO; + } + memcpy_fromio(buffer, &iss_blk_regs->data, + lcount * ib->sectsize); + spin_unlock_irqrestore(&iss_blk_reglock, flags); + count -= lcount; + sector += lcount; + buffer += lcount * ib->sectsize; + } + return 0; +} + +static int __iss_blk_write(struct iss_blk *ib, void *buffer, + unsigned long sector, unsigned long count) +{ + unsigned long lcount, flags; + u32 stat; + + pr_debug("__iss_blk_write 0x%ld sectors @ 0x%lx\n", count, sector); + + while (count) { + lcount = min(count, 4ul); + spin_lock_irqsave(&iss_blk_reglock, flags); + out_be32(&iss_blk_regs->devno, ib->devno); + out_be32(&iss_blk_regs->sector, sector); + out_be32(&iss_blk_regs->count, lcount); + memcpy_toio(&iss_blk_regs->data, buffer, lcount * ib->sectsize); + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_WRITE); + stat = in_be32(&iss_blk_regs->stat); + spin_unlock_irqrestore(&iss_blk_reglock, flags); + if (stat != ISS_BD_STATUS_OK) + return -EIO; + count -= lcount; + sector += lcount; + buffer += lcount * ib->sectsize; + } + return 0; +} + +static void iss_blk_do_request(struct request_queue *q) +{ + struct iss_blk *ib = q->queuedata; + int rc = 0; + + pr_debug("iss_do_request dev %d\n", ib->devno); + + while (iss_req || ((iss_req = blk_fetch_request(q)) != NULL)) { + pr_debug(" -> req @ %p, changed: %d\n", iss_req, ib->changed); + if (ib->changed) { + iss_end_request(-EIO); /* failure */ + continue; + } + switch (rq_data_dir(iss_req)) { + case READ: + rc = __iss_blk_read(ib, iss_req->buffer, + blk_rq_pos(iss_req), + blk_rq_cur_sectors(iss_req)); + break; + case WRITE: + rc = __iss_blk_write(ib, iss_req->buffer, + blk_rq_pos(iss_req), + blk_rq_cur_sectors(iss_req)); + }; + + pr_debug(" -> ending request, rc = %d\n", rc); + if (rc) + iss_end_request(-EIO); + else + iss_end_request(0); + } +} + +static int iss_blk_release(struct gendisk *disk, fmode_t mode) +{ + struct iss_blk *ib = disk->private_data; + unsigned long flags; + + pr_debug("issblk%d: release !\n", disk->first_minor); + + spin_lock_irqsave(&iss_blk_reglock, flags); + out_be32(&iss_blk_regs->devno, ib->devno); + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_SYNC); + spin_unlock_irqrestore(&iss_blk_reglock, flags); + + return 0; +} + +static int iss_blk_revalidate(struct gendisk *disk) +{ + struct iss_blk *ib = disk->private_data; + unsigned long flags; + + pr_debug("issblk%d: revalidate !\n", disk->first_minor); + + if (ib->present && ib->changed) { + spin_lock_irqsave(&iss_blk_reglock, flags); + out_be32(&iss_blk_regs->devno, ib->devno); + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_CLOSE); + ib->present = ib->changed = 0; + spin_unlock_irqrestore(&iss_blk_reglock, flags); + } + iss_blk_setup(ib); + return 0; +} + +static int iss_blk_media_changed(struct gendisk *disk) +{ + struct iss_blk *ib = disk->private_data; + u32 stat; + + pr_debug("issblk%d: media_changed !\n", disk->first_minor); + + out_be32(&iss_blk_regs->devno, ib->devno); + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_STATUS); + stat = in_be32(&iss_blk_regs->stat); + if (stat == ISS_BD_FILE_CHANGED) + ib->changed = 1; + + return ib->changed; +} + +static int iss_blk_open(struct block_device *bdev, fmode_t mode) +{ + struct gendisk *disk = bdev->bd_disk; + struct iss_blk *ib = disk->private_data; + + pr_debug("issblk%d: open !\n", disk->first_minor); + + check_disk_change(bdev); + if (ib->changed) + iss_blk_setup(ib); + if (!ib->present) + return -ENOMEDIUM; + return 0; +} + +static struct block_device_operations iss_blk_fops = { + .owner = THIS_MODULE, + .open = iss_blk_open, + .release = iss_blk_release, + .media_changed = iss_blk_media_changed, + .revalidate_disk = iss_blk_revalidate, +}; + +static int __init iss_blk_init(void) +{ + struct device_node *np; + int i; + + pr_debug("iss_regs offsets:\n"); + pr_debug(" cmd : 0x%x\n", offsetof(struct iss_blk_regs, cmd)); + pr_debug(" stat : 0x%x\n", offsetof(struct iss_blk_regs, stat)); + pr_debug(" sector : 0x%x\n", offsetof(struct iss_blk_regs, sector)); + pr_debug(" count : 0x%x\n", offsetof(struct iss_blk_regs, count)); + pr_debug(" devno : 0x%x\n", offsetof(struct iss_blk_regs, devno)); + pr_debug(" size : 0x%x\n", offsetof(struct iss_blk_regs, size)); + pr_debug(" data : 0x%x\n", offsetof(struct iss_blk_regs, data)); + + np = of_find_node_by_path("/iss-block"); + if (np == NULL) + return -ENODEV; + iss_blk_regs = of_iomap(np, 0); + if (iss_blk_regs == NULL) { + pr_err("issblk: Failed to map registers\n"); + return -ENOMEM; + } + + if (register_blkdev(MAJOR_NR, "iss_blk")) + return -EIO; + + spin_lock_init(&iss_blk_qlock); + spin_lock_init(&iss_blk_reglock); + + printk(KERN_INFO "ISS Block driver initializing for %d minors\n", + NUM_ISS_BLK_MINOR); + + for (i = 0; i < NUM_ISS_BLK_MINOR; i++) { + struct gendisk *disk = alloc_disk(1); + struct request_queue *q; + struct iss_blk *ib = &iss_blks[i]; + + if (!disk) { + pr_err("issblk%d: Failed to allocate disk\n", i); + break; + } + + q = blk_init_queue(iss_blk_do_request, &iss_blk_qlock); + if (q == NULL) { + pr_err("issblk%d: Failed to init queue\n", i); + put_disk(disk); + break; + } + q->queuedata = ib; + + ib->disk = disk; + ib->devno = i; + ib->present = 0; + ib->changed = 0; + ib->capacity = 0; + ib->sectsize = 512; + + disk->major = MAJOR_NR; + disk->first_minor = i; + disk->fops = &iss_blk_fops; + disk->private_data = &iss_blks[i]; + disk->flags = GENHD_FL_REMOVABLE; + disk->queue = q; + sprintf(disk->disk_name, "issblk%d", i); + + iss_blk_setup(ib); + + add_disk(disk); + } + + return 0; +} + +static void __exit iss_blk_exit(void) +{ + int i; + + unregister_blkdev(MAJOR_NR, "iss_blk"); + + for (i = 0; i < NUM_ISS_BLK_MINOR; i++) { + struct iss_blk *ib = &iss_blks[i]; + + if (ib->present) { + out_be32(&iss_blk_regs->devno, ib->devno); + out_8(&iss_blk_regs->cmd, ISS_BD_CMD_CLOSE); + } + } +} + +module_init(iss_blk_init); +module_exit(iss_blk_exit); + +MODULE_DESCRIPTION("ISS Simulator Block Device"); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 25cf327..188a686 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -33,6 +33,10 @@ if DMADEVICES comment "DMA Devices" +config LSI_DMA + select DMA_ENGINE + tristate "ACP GP-DMA" + config INTEL_MID_DMAC tristate "Intel MID DMA support for Peripheral DMA controllers" depends on PCI && X86 diff --git a/drivers/dma/lsi-dma.c b/drivers/dma/lsi-dma.c new file mode 100644 index 0000000..307e01d --- /dev/null +++ b/drivers/dma/lsi-dma.c @@ -0,0 +1,549 @@ +/* + * drivers/dma/lsu-dma.c + * + * This file contains a driver for the LSI ACP 34xx DMA engine + * + * Copyright 2011 Mentor Graphics + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "lsi-dma.h" + +#define MAX_DMA_CHANNELS 4 +#define GP_DMA_IRQ (35) + +struct lsidma_engine; + +struct lsidma_channel { + struct lsidma_engine *lsidma_engine; + unsigned int channel; + unsigned int lsidma_channel; + int irq; + + struct dma_chan chan; + + spinlock_t lock; + struct dma_async_tx_descriptor desc; + dma_cookie_t last_completed; + enum dma_status status; + + enum dma_slave_buswidth word_size; + dma_addr_t per_address; + u32 watermark_level; + int dma_request; + struct scatterlist *sg_list; +}; + +struct lsidma_engine { + struct device *dev; + struct device_dma_parameters dma_parms; + struct dma_device dma_device; + struct lsidma_channel channel[MAX_DMA_CHANNELS]; + bool done; + void __iomem *base; +}; + +static struct lsidma_channel *to_lsidma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct lsidma_channel, chan); +} + +static inline void __iomem *BASE(struct lsidma_channel *dmac) +{ + return dmac->lsidma_engine->base + dmac->lsidma_channel * 0x40; +} + +#if 0 +static void imxdma_handle(struct imxdma_channel *imxdmac) +{ + if (imxdmac->desc.callback) + imxdmac->desc.callback(imxdmac->desc.callback_param); + imxdmac->last_completed = imxdmac->desc.cookie; +} + + +static void imxdma_irq_handler(int channel, void *data) +{ + struct imxdma_channel *imxdmac = data; + + imxdmac->status = DMA_SUCCESS; + imxdma_handle(imxdmac); +} + +static void imxdma_err_handler(int channel, void *data, int error) +{ + struct imxdma_channel *imxdmac = data; + + imxdmac->status = DMA_ERROR; + imxdma_handle(imxdmac); +} + +static void imxdma_progression(int channel, void *data, + struct scatterlist *sg) +{ + struct imxdma_channel *imxdmac = data; + + imxdmac->status = DMA_SUCCESS; + imxdma_handle(imxdmac); +} + +static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) +{ + struct imxdma_channel *imxdmac = to_imxdma_chan(chan); + struct dma_slave_config *dmaengine_cfg = (void *)arg; + int ret; + unsigned int mode = 0; + + switch (cmd) { + case DMA_TERMINATE_ALL: + imxdmac->status = DMA_ERROR; + imx_dma_disable(imxdmac->imxdma_channel); + return 0; + case DMA_SLAVE_CONFIG: + if (dmaengine_cfg->direction == DMA_FROM_DEVICE) { + imxdmac->per_address = dmaengine_cfg->src_addr; + imxdmac->watermark_level = dmaengine_cfg->src_maxburst; + imxdmac->word_size = dmaengine_cfg->src_addr_width; + } else { + imxdmac->per_address = dmaengine_cfg->dst_addr; + imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; + imxdmac->word_size = dmaengine_cfg->dst_addr_width; + } + + switch (imxdmac->word_size) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + mode = IMX_DMA_MEMSIZE_8; + break; + case DMA_SLAVE_BUSWIDTH_2_BYTES: + mode = IMX_DMA_MEMSIZE_16; + break; + default: + case DMA_SLAVE_BUSWIDTH_4_BYTES: + mode = IMX_DMA_MEMSIZE_32; + break; + } + ret = imx_dma_config_channel(imxdmac->imxdma_channel, + mode | IMX_DMA_TYPE_FIFO, + IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, + imxdmac->dma_request, 1); + + if (ret) + return ret; + + imx_dma_config_burstlen(imxdmac->imxdma_channel, + imxdmac->watermark_level * imxdmac->word_size); + + return 0; + default: + return -ENOSYS; + } + + return -EINVAL; +} + +static void imxdma_free_chan_resources(struct dma_chan *chan) +{ + struct imxdma_channel *imxdmac = to_imxdma_chan(chan); + + imx_dma_disable(imxdmac->imxdma_channel); + + if (imxdmac->sg_list) { + kfree(imxdmac->sg_list); + imxdmac->sg_list = NULL; + } +} + +static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( + struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_data_direction direction, + unsigned long flags) +{ + struct imxdma_channel *imxdmac = to_imxdma_chan(chan); + struct scatterlist *sg; + int i, ret, dma_length = 0; + unsigned int dmamode; + + if (imxdmac->status == DMA_IN_PROGRESS) + return NULL; + + imxdmac->status = DMA_IN_PROGRESS; + + for_each_sg(sgl, sg, sg_len, i) { + dma_length += sg->length; + } + + if (direction == DMA_FROM_DEVICE) + dmamode = DMA_MODE_READ; + else + dmamode = DMA_MODE_WRITE; + + switch (imxdmac->word_size) { + case DMA_SLAVE_BUSWIDTH_4_BYTES: + if (sgl->length & 3 || sgl->dma_address & 3) + return NULL; + break; + case DMA_SLAVE_BUSWIDTH_2_BYTES: + if (sgl->length & 1 || sgl->dma_address & 1) + return NULL; + break; + case DMA_SLAVE_BUSWIDTH_1_BYTE: + break; + default: + return NULL; + } + + ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len, + dma_length, imxdmac->per_address, dmamode); + if (ret) + return NULL; + + return &imxdmac->desc; +} + +static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( + struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, + size_t period_len, enum dma_data_direction direction) +{ + struct imxdma_channel *imxdmac = to_imxdma_chan(chan); + struct imxdma_engine *imxdma = imxdmac->imxdma; + int i, ret; + unsigned int periods = buf_len / period_len; + unsigned int dmamode; + + dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", + __func__, imxdmac->channel, buf_len, period_len); + + if (imxdmac->status == DMA_IN_PROGRESS) + return NULL; + imxdmac->status = DMA_IN_PROGRESS; + + ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel, + imxdma_progression); + if (ret) { + dev_err(imxdma->dev, "Failed to setup the DMA handler\n"); + return NULL; + } + + if (imxdmac->sg_list) + kfree(imxdmac->sg_list); + + imxdmac->sg_list = kcalloc(periods + 1, + sizeof(struct scatterlist), GFP_KERNEL); + if (!imxdmac->sg_list) + return NULL; + + sg_init_table(imxdmac->sg_list, periods); + + for (i = 0; i < periods; i++) { + imxdmac->sg_list[i].page_link = 0; + imxdmac->sg_list[i].offset = 0; + imxdmac->sg_list[i].dma_address = dma_addr; + imxdmac->sg_list[i].length = period_len; + dma_addr += period_len; + } + + /* close the loop */ + imxdmac->sg_list[periods].offset = 0; + imxdmac->sg_list[periods].length = 0; + imxdmac->sg_list[periods].page_link = + ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; + + if (direction == DMA_FROM_DEVICE) + dmamode = DMA_MODE_READ; + else + dmamode = DMA_MODE_WRITE; + + ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods, + IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode); + if (ret) + return NULL; + + return &imxdmac->desc; +} + +#endif + +static void lsidma_dump(struct lsidma_engine *e) +{ + int i; + + printk("DMA Engine register dump (mmapped src = %p)\n", e->base); + for (i = 0; i < 0x40 * MAX_DMA_CHANNELS / sizeof(u32); i ++ ) { + printk("%08X ", __raw_readl(e->base + i * sizeof(u32))); + if ((i + 1 ) % 4 == 0) + printk("\n"); + } + printk("\n"); +} + +static void lsidma_handle(struct lsidma_channel *dmac, enum dma_status status) +{ + if (dmac->desc.callback) + dmac->desc.callback(dmac->desc.callback_param); + dmac->last_completed = dmac->desc.cookie; + dmac->status = DMA_SUCCESS; +} + +static irqreturn_t lsidma_isr(int _irq, void *_dmac) +{ + struct lsidma_channel *dmac = _dmac; + void __iomem *base = BASE(dmac); + u32 status; + + status = __raw_readl(base + DMA_STATUS); + + /* confirm and clear the interrupt */ + __raw_writel(status, base + DMA_STATUS); + + printk("%s: channel status %08x\n", __func__, status); + + if (status & (1<<3)) { + lsidma_handle(dmac, DMA_SUCCESS); + return IRQ_HANDLED; + } + + if (status & 0xF0) { + lsidma_handle(dmac, DMA_ERROR); + return IRQ_HANDLED; + } + + return IRQ_HANDLED; +} + +static dma_cookie_t lsidma_assign_cookie(struct lsidma_channel *dmac) +{ + dma_cookie_t cookie = dmac->chan.cookie; + + if (++cookie < 0) + cookie = 1; + + dmac->chan.cookie = dmac->desc.cookie = cookie; + return cookie; +} + + +static dma_cookie_t lsidma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct lsidma_channel *dmac = to_lsidma_chan(tx->chan); + dma_cookie_t cookie; + void __iomem *base = BASE(dmac); + u32 cfg; + + spin_lock_irq(&dmac->lock); + cookie = lsidma_assign_cookie(dmac); + + cfg = __raw_readl(base + DMA_CHANNEL_CONFIG); + printk("%s: current cfg = %08x\n", __func__, cfg); + __raw_writel(cfg | DMA_CONFIG_TX_EN, base + DMA_CHANNEL_CONFIG); + + printk("%s: SUBMITTED the work item!\n", __func__); + spin_unlock_irq(&dmac->lock); + + return cookie; +} + + +static int lsidma_alloc_chan_resources(struct dma_chan *chan) +{ + struct lsidma_channel *dmac = to_lsidma_chan(chan); + void __iomem *base = BASE(dmac); + + printk("%s\n", __func__); + + dma_async_tx_descriptor_init(&dmac->desc, chan); + dmac->desc.tx_submit = lsidma_tx_submit; + dmac->desc.flags = DMA_CTRL_ACK; + dmac->status = DMA_SUCCESS; + + printk("about to enable channel\n"); + ssleep(5); + __raw_writel(DMA_CONFIG_CHAN_EN, base + DMA_CHANNEL_CONFIG); + ssleep(5); + + lsidma_dump(dmac->lsidma_engine); + + return 0; +} + +static void lsidma_free_chan_resources(struct dma_chan *chan) +{ + struct lsidma_channel *dmac = to_lsidma_chan(chan); + printk("%s\n", __func__); + lsidma_dump(dmac->lsidma_engine); +} + +static void lsidma_issue_pending(struct dma_chan *chan) +{ + /* + * Nothing to do. We only have a single descriptor + */ +} + +static enum dma_status lsidma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + dma_cookie_t last_used = cookie; + struct lsidma_channel *dmac = to_lsidma_chan(chan); + enum dma_status ret = 0; + + printk("%s\n", __func__); + lsidma_dump(dmac->lsidma_engine); + + last_used = chan->cookie; + ret = dma_async_is_complete(cookie, dmac->last_completed, last_used); + dma_set_tx_state(txstate, dmac->last_completed, last_used, 0); + + return ret; +} + +static struct dma_async_tx_descriptor *lsidma_prep_memcpy(struct dma_chan *chan, + dma_addr_t dst, + dma_addr_t src, + size_t size, + unsigned long dma_flags) +{ + struct lsidma_channel *dmac = to_lsidma_chan(chan); + + return &dmac->desc; +} + +static int __exit lsidma_remove(struct device *pdev) +{ + struct lsidma_engine *lsidma = dev_get_drvdata(pdev); + int i; + + if (!lsidma) + return 0; + + if (lsidma->done) + dma_async_device_unregister(&lsidma->dma_device); + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + struct lsidma_channel *dmac = &lsidma->channel[i]; + + if (dmac->channel == i) /* initialized ok */ + free_irq(GP_DMA_IRQ + i, dmac); + } + + iounmap(lsidma->base); + kfree(lsidma); + dev_set_drvdata(pdev, NULL); + + return 0; +} + +static int __init lsidma_probe(struct device *pdev) +{ + struct lsidma_engine *lsidma; + int ret, i; + + printk("%s\n", __func__); + + lsidma = kzalloc(sizeof *lsidma, GFP_KERNEL); + if (!lsidma) + return -ENOMEM; + + lsidma->dev = lsidma->dma_device.dev = pdev; + + dev_set_drvdata(pdev, lsidma); + + dma_cap_zero(lsidma->dma_device.cap_mask); + dma_cap_set(DMA_MEMCPY, lsidma->dma_device.cap_mask); + + lsidma->dma_device.device_alloc_chan_resources = lsidma_alloc_chan_resources; + lsidma->dma_device.device_free_chan_resources = lsidma_free_chan_resources; + lsidma->dma_device.device_tx_status = lsidma_tx_status; + lsidma->dma_device.device_issue_pending = lsidma_issue_pending; + lsidma->dma_device.device_prep_dma_memcpy = lsidma_prep_memcpy; + + INIT_LIST_HEAD(&lsidma->dma_device.channels); + + lsidma->base = ioremap(0x20004e0000ull, 0x40 * MAX_DMA_CHANNELS); + + /* Initialize channel parameters */ + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + struct lsidma_channel *dmac = &lsidma->channel[i]; + + + dmac->lsidma_engine = lsidma; + spin_lock_init(&dmac->lock); + dmac->chan.device = &lsidma->dma_device; + + dmac->irq = irq_create_mapping(NULL, GP_DMA_IRQ + i); + dev_info(pdev, "channel %d, irq %d\n", i, dmac->irq); + ret = request_irq(dmac->irq, lsidma_isr, + IRQF_SHARED, "lsi-dma", dmac); + if (ret) { + dev_err(pdev, "failed to request_irq, error = %d\n", ret); + goto err_init; + } + + dmac->channel = i; + + /* Add the channel to the DMAC list */ + list_add_tail(&dmac->chan.device_node, &lsidma->dma_device.channels); + } + + lsidma_dump(lsidma); + + ret = dma_async_device_register(&lsidma->dma_device); + if (ret) { + dev_err(pdev, "unable to register\n"); + goto err_init; + } + lsidma->done = true; + + return 0; + +err_init: + lsidma_remove(pdev); + dev_set_drvdata(pdev, NULL); + return ret; +} + + +static struct platform_driver lsidma_driver = { + .driver = { + .name = "lsi-dma", + .probe = lsidma_probe, + .remove = __exit_p(lsidma_remove), + .owner = THIS_MODULE, + }, +}; + +static struct platform_device *lsidma_dev = NULL; + +static int __init lsidma_module_init(void) +{ + lsidma_dev = platform_device_register_simple("lsi-dma", -1, NULL, 0); + return platform_driver_register(&lsidma_driver); +} +subsys_initcall(lsidma_module_init); + +static void __exit lsidma_module_exit(void) +{ + platform_driver_unregister(&lsidma_driver); + platform_device_unregister(lsidma_dev); +} +module_exit(lsidma_module_exit) + +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/lsi-dma.h b/drivers/dma/lsi-dma.h new file mode 100644 index 0000000..6137dd5 --- /dev/null +++ b/drivers/dma/lsi-dma.h @@ -0,0 +1,42 @@ +#ifndef __LSI_DMA_H +#define __LSI_DMA_H + +#define DMA_X_SRC_COUNT 0x00 +#define DMA_Y_SRC_COUNT 0x04 +#define DMA_X_MODIF_SRC 0x08 +#define DMA_Y_MODIF_SRC 0x0c +#define DMA_SRC_CUR_ADDR 0x10 +#define DMA_SRC_ACCESS 0x14 + #define DMA_SRC_ACCESS_BURST_TYPE (1<<15) + #define DMA_SRC_ACCESS_TAIL_LENGTH(x) (((x) & 0xF) << 11) + #define DMA_SRC_ACCESS_ROTATOR_LENGTH(x) (((x) & 1F) << 6) + #define DMA_SRC_ACCESS_SRC_SIZE(x) (((x) & 7) << 3) + #define DMA_SRC_ACCESS_SRC_BURST(x) (((x) & 7) << 0) +#define DMA_SRC_MASK 0x18 +#define DMA_X_DST_COUNT 0x1c +#define DMA_Y_DST_COUNT 0x20 +#define DMA_X_MODIF_DST 0x24 +#define DMA_Y_MODIF_DST 0x28 +#define DMA_DST_CUR_ADDR 0x2C +#define DMA_DST_ACCESS 0x30 + #define DMA_DST_ACCESS_DST_SIZE(x) (((x) & 7) << 3) + #define DMA_DST_ACCESS_DST_BURST(x) (((x) & 7) << 0) +#define DMA_NXT_DESCR 0x34 +#define DMA_CHANNEL_CONFIG 0x38 + #define DMA_CONFIG_DST_SPACE(x) (((x) & 7) << 26) + #define DMA_CONFIG_SRC_SPACE(x) (((x) & 7) << 23) + #define DMA_CONFIG_EXT_PRIORITY (1<<22) + #define DMA_CONFIG_PRIORITY_ROW (1<<21) + #define DMA_CONFIG_PRIORITY (1<<20) + #define DMA_CONFIG_CHANNEL_PRIORITY(x) (((x) & 3) << 16) + #define DMA_CONFIG_LAST_BLOCK (1<<15) + #define DMA_CONFIG_CLEAR_FIFO (1<<14) + #define DMA_CONFIG_START_MEM_LOAD (1<<13) + #define DMA_CONFIG_STOP_DST_EOB (1<<11) + #define DMA_CONFIG_INT_DST_EOT (1<<7) + #define DMA_CONFIG_INT_DST_EOB (1<<6) + #define DMA_CONFIG_TX_EN (1<<1) + #define DMA_CONFIG_CHAN_EN (1<<0) +#define DMA_STATUS 0x3C + +#endif /* __LSI_DMA_H */ diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 646068e..246d4d1 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -434,6 +434,12 @@ config I2C_IXP2000 This driver is deprecated and will be dropped soon. Use i2c-gpio instead. +config I2C_LSI + tristate "LSI ACP3448" + depends on PPC + help + no help + config I2C_MPC tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" depends on PPC diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index e6cf294..359d655 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_I2C_IMX) += i2c-imx.o obj-$(CONFIG_I2C_INTEL_MID) += i2c-intel-mid.o obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o +obj-$(CONFIG_I2C_LSI) += i2c-lsi.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o diff --git a/drivers/i2c/busses/i2c-lsi.c b/drivers/i2c/busses/i2c-lsi.c new file mode 100644 index 0000000..79a6ef2 --- /dev/null +++ b/drivers/i2c/busses/i2c-lsi.c @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2011 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "i2c-lsi.h" + +#define DRV_NAME "i2c-lsi" + +struct lsi_iic { + struct device *dev; + void __iomem *base; + u32 interrupt; + wait_queue_head_t queue; + struct i2c_adapter adap; + int irq; + u32 real_clk; +}; + +static void lsi_iic_writel(u32 data, void __iomem *addr) +{ + printk("%s, 0x%x ==> %p\n", __func__, data, addr); + __raw_writel(data, addr); +} + +static u32 lsi_iic_readl(void __iomem *addr) +{ + u32 r; + + r = __raw_readl(addr); + printk("%s, 0x%x <== %p\n", __func__, r, addr); + return r; +} + +static void __devinit lsi_iic_setup_clock(struct lsi_iic *i2c, u32 clock) +{ + unsigned long freq; + u32 divisor; + + BUG_ON(acp_clock_get(1, &freq)); + + divisor = freq / clock; + printk("System clock %ld, requested %d, divisor = %x\n", freq, clock, divisor); + + lsi_iic_writel((MCCFG_LPD(divisor / 2) | MCCFG_HPD(divisor - divisor / 2)), i2c->base + MCCFG); +} + +static irqreturn_t lsi_iic_isr(int irq, void *dev_id) +{ + struct mpc_i2c *i2c = dev_id; +#if 0 + if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { + /* Read again to allow register to stabilise */ + i2c->interrupt = readb(i2c->base + MPC_I2C_SR); + writeb(0, i2c->base + MPC_I2C_SR); + wake_up(&i2c->queue); + } +#endif + return IRQ_HANDLED; +} + +static void lsi_iic_regdump(struct lsi_iic *i2c) +{ +#if 0 + int i; + + printk("%s at %p\n", __func__, i2c->base); + for (i = 0; i <= 0x10; i ++ ) { + printk("%08X: 0x%08x\n", i * 4, lsi_iic_readl(i2c->base + i * 4)); + } +#endif +} + +static int lsi_iic_busyloop(struct lsi_iic *i2c, int offset) +{ + int count = 100; + u32 r; + + lsi_iic_regdump(i2c); + printk("Entering %s...(%d)", __func__, offset); + while (--count > 0) { + r = lsi_iic_readl(i2c->base + offset); + printk("%X,", r); + if (r != 0) + break; + udelay(1000); + } + + printk("\nDone\n"); + return count <= 0 ? -ETIMEDOUT : 0; +} + +static int lsi_iic_read(struct lsi_iic *i2c, int target, u8 *data, int length, int restart, int tenbit) +{ + u32 d1, d2; + int actual_length; + int ret = 0; + + for(;;) { + lsi_iic_writel(MTC_MMA | MTC_STOP | (tenbit ? MTC_TBAM : 0), i2c->base + MTC); + + lsi_iic_writel(MHC_HPD(0x80) | MHC_LPD(0x00), i2c->base + MStartSHC); + lsi_iic_writel(MHC_HPD(0x00) | MHC_LPD(0x80), i2c->base + MStopSHC); + lsi_iic_writel(MHC_HPD(0x14) | MHC_LPD(0x14), i2c->base + MDSHC); + + lsi_iic_writel(target, i2c->base + MSA); + + actual_length = clamp_t(int, length, 0, sizeof(u32) * 2 - 1); + lsi_iic_writel( MRC_RR | MRC_NUMBYTES(actual_length), i2c->base + MRC); + + ret = lsi_iic_busyloop(i2c, MRS); + if (ret < 0) + break; + + d1 = lsi_iic_readl(i2c->base + MRX0); + d2 = lsi_iic_readl(i2c->base + MRX1); + + memcpy(data, &d1, clamp_t(int, actual_length, 0, sizeof(u32))); + actual_length -= sizeof(u32); + length -= sizeof(u32); + data += sizeof(u32); + + memcpy(data, &d2, clamp_t(int, actual_length, 0, sizeof(u32))); + actual_length -= sizeof(u32); + length -= sizeof(u32); + data += sizeof(u32); + + if (length <= 0) + break; + } + return ret >= 0 ? 1 : ret; +} + +static int lsi_iic_write(struct lsi_iic *i2c, int target, u8 *data, int length, int restart, int tenbit) +{ + u32 d1, d2; + int d1_len, d2_len; + int ret = 0; + + for (;;) { + lsi_iic_writel(MTC_MOC | MTC_MMA | MTC_STOP | (tenbit ? MTC_TBAM : 0), i2c->base + MTC); + + lsi_iic_writel(MHC_HPD(0x80) | MHC_LPD(0x00), i2c->base + MStartSHC); + lsi_iic_writel(MHC_HPD(0x00) | MHC_LPD(0x80), i2c->base + MStopSHC); + lsi_iic_writel(MHC_HPD(0x14) | MHC_LPD(0x14), i2c->base + MDSHC); + + lsi_iic_writel(MTC_MMA | MTC_STOP | (tenbit ? MTC_TBAM : 0), i2c->base + MTC); + + lsi_iic_writel(target, i2c->base + MSA); + + d1 = d2 = 0; + + d1_len = clamp_t(int, length, 0, sizeof(u32)); + memcpy(&d1, data, min_t(int, d1_len, sizeof(u32))); + data += d1_len; + length -= d1_len; + + d2_len = clamp_t(int, length, 0, sizeof(u32)); + memcpy(&d2, data, min_t(int, d2_len, sizeof(u32))); + data += d2_len; + length -= d2_len; + + lsi_iic_writel(d1, i2c->base + MTX0); + lsi_iic_writel(d2, i2c->base + MTX1); + + lsi_iic_writel( MTC_MMA | + MTC_STOP | + (tenbit ? MTC_TBAM : 0) | + MTC_NUMBYTES(d1_len + d2_len) | + MTC_TR, + i2c->base + MTC); + + ret = lsi_iic_busyloop(i2c, MTS); + + if (length == 0 || ret < 0) + break; + } + return ret >= 0 ? 1 : ret; +} + +static int lsi_iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + struct i2c_msg *pmsg; + int i, ret = 0; + struct lsi_iic *i2c = i2c_get_adapdata(adap); + + lsi_iic_setup_clock(i2c, 400); + for (i = 0; ret >= 0 && i < num; i++) { + pmsg = &msgs[i]; + printk( /* dev_dbg(i2c->dev, */ + "Doing %s %d bytes from/to 0x%02x - %d of %d messages\n", + pmsg->flags & I2C_M_RD ? "read" : "write", + pmsg->len, pmsg->addr, i + 1, num); + if (pmsg->flags & I2C_M_RD) + ret = lsi_iic_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i, pmsg->flags & I2C_M_TEN); + else + ret = lsi_iic_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i, pmsg->flags & I2C_M_TEN); + } + + return ret; +} + +static u32 lsi_iic_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm lsi_iic_algo = { + .master_xfer = lsi_iic_xfer, + .functionality = lsi_iic_functionality, +}; + +static struct i2c_adapter lsi_iic_ops = { + .owner = THIS_MODULE, + .name = "LSI adapter", + .algo = &lsi_iic_algo, + .timeout = HZ, +}; + +static int __devinit lsi_iic_probe(struct platform_device *op) +{ + struct lsi_iic *i2c; + const u32 *prop; + u32 clock = 0; + int result = 0; + int plen; + + i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + i2c->dev = &op->dev; /* for debug and error output */ + + init_waitqueue_head(&i2c->queue); + + i2c->base = of_iomap(op->dev.of_node, 0); + if (!i2c->base) { + dev_err(i2c->dev, "failed to map controller\n"); + result = -ENOMEM; + goto fail_map; + } + + i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0); + if (i2c->irq) { /* no i2c->irq implies polling */ + result = request_irq(i2c->irq, lsi_iic_isr, + IRQF_SHARED, "i2c-lsi", i2c); + if (result < 0) { + dev_err(i2c->dev, "failed to attach interrupt\n"); + goto fail_request; + } + } + dev_set_drvdata(&op->dev, i2c); + + prop = of_get_property(op->dev.of_node, "clock-frequency", &plen); + if (prop && plen == sizeof(u32)) + clock = *prop; + if (clock == 0) + clock = 400; + lsi_iic_setup_clock(i2c, clock); + + i2c->adap = lsi_iic_ops; + i2c_set_adapdata(&i2c->adap, i2c); + i2c->adap.dev.parent = &op->dev; + i2c->adap.dev.of_node = of_node_get(op->dev.of_node); + + result = i2c_add_adapter(&i2c->adap); + if (result < 0) { + dev_err(i2c->dev, "failed to add adapter\n"); + goto fail_add; + } + + of_i2c_register_devices(&i2c->adap); + printk("%s mmapped at %p, irq %d\n", DRV_NAME, i2c->base, i2c->irq); + + return result; + + fail_add: + dev_set_drvdata(&op->dev, NULL); + free_irq(i2c->irq, i2c); + fail_request: + irq_dispose_mapping(i2c->irq); + iounmap(i2c->base); + fail_map: + kfree(i2c); + return result; +}; + +static int __devexit lsi_iic_remove(struct platform_device *op) +{ + struct lsi_iic *i2c = dev_get_drvdata(&op->dev); + + i2c_del_adapter(&i2c->adap); + dev_set_drvdata(&op->dev, NULL); + + if (i2c->irq) + free_irq(i2c->irq, i2c); + + irq_dispose_mapping(i2c->irq); + iounmap(i2c->base); + kfree(i2c); + return 0; +}; + + +static const struct of_device_id lsi_iic_of_match[] = { + {.compatible = "acp-i2c", }, + {}, +}; +MODULE_DEVICE_TABLE(of, lsi_iic_of_match); + +/* Structure for a device driver */ +static struct platform_driver lsi_iic_driver = { + .probe = lsi_iic_probe, + .remove = __devexit_p(lsi_iic_remove), + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .of_match_table = lsi_iic_of_match, + }, +}; + +static int __init lsi_iic_init(void) +{ + return platform_driver_register(&lsi_iic_driver); +} + +static void __exit lsi_iic_exit(void) +{ + platform_driver_unregister(&lsi_iic_driver); +} + +module_init(lsi_iic_init); +module_exit(lsi_iic_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/i2c-lsi.h b/drivers/i2c/busses/i2c-lsi.h new file mode 100644 index 0000000..da00b65 --- /dev/null +++ b/drivers/i2c/busses/i2c-lsi.h @@ -0,0 +1,60 @@ +#ifndef LSI_I2C_H__ +#define LSI_I2C_H__ + +#define MTC 0x00 /* Master Transmit Config */ +#define MTC_STOP (1<<29) +#define MTC_MOC (1<<10) +#define MTC_TC (1<<9) +#define MTC_MMA (1<<8) +#define MTC_TBAM (1<<7) +#define MTC_LE (1<<5) +#define MTC_TR (1<<0) +#define MTC_NUMBYTES(x) (((x) & 0x0F) << 1) + +#define MRC 0x04 /* Master Receive Config */ +#define MRC_LE (1<<5) +#define MRC_NUMBYTES(x) (((x) & 0x0F) << 1) +#define MRC_RR (1<<0) + +#define MTS 0x08 /* Master Transmit Status */ +#define MTS_ERROR 0x02 +#define MTS_DONE 0x01 + +#define MRS 0x0C /* Master Receive Status */ +#define MRS_NUMBYTES(r) (((r) >> 1) & 0xF) +#define MRS_ERROR 0x02 +#define MRS_DONE 0x01 + +#define MIE 0x10 /* Master Interrupt Enable */ +#define MI_EREI (1<<3) +#define MI_ERCI (1<<2) +#define MI_ETEI (1<<1) +#define MI_ETDI (1<<0) + +#define MIC 0x14 /* Master Interrupt Clear */ + +#define MIS 0x18 /* Master Interrupt Status */ + +#define MCCFG 0x1C /* CLK config */ +#define MCCFG_LPD(x) ((x) & 0x3FF) +#define MCCFG_HPD(x) (((x) & 0x3FF) << 16) + +#define MHC_LPD(x) ((x) & 0x3FF) +#define MHC_HPD(x) (((x) & 0x3FF) << 16) +#define MStartSHC 0x20 /* StartSetupHoldConfig */ +#define MStopSHC 0x24 /* StopSetupHoldConfig */ +#define MDSHC 0x28 /* DataSetupHoldConfig */ + +#define MBM 0x2C /* Master Bypass Mode */ +#define MBM_EPBM (1<<2) +#define MBM_SCLV (1<<1) +#define MBM_SDAV (1<<0) + +#define MSA 0x30 /* Master Slave Address */ + +#define MTX0 0x34 /* Transmit data */ +#define MTX1 0x38 +#define MRX0 0x3C /* Receive data */ +#define MRX1 0x40 + +#endif /* LSI_I2C_H__ */ diff --git a/drivers/lsi/Kconfig b/drivers/lsi/Kconfig new file mode 100644 index 0000000..565f7fc --- /dev/null +++ b/drivers/lsi/Kconfig @@ -0,0 +1,104 @@ +menu "LSI Drivers (APP3, APP3K, and ACP)" + +config SERIAL_ACP + bool "LSI's Serial Driver for the ACP" + select SERIAL_CORE + help + Handles the serial ports (there are two) on LSI's ACP board + and the simulated serial port provided by ISS. + +config SERIAL_ACP_CONSOLE + bool "Console on the ACP serial port" + depends on SERIAL_ACP=y + select SERIAL_CORE_CONSOLE + help + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). This could be useful if some terminal or printer is connected + to that serial port. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyS1". (Try "man bootparam" or see the documentation of + your boot loader (grub or lilo or loadlin) about how to pass options + to the kernel at boot time.) + + If you don't have a VGA card installed and you say Y here, the + kernel will automatically use the first serial line, /dev/ttyS0, as + system console. + + You can set that using a kernel command line option such as + "console=uart8250,io,0x3f8,9600n8" + "console=uart8250,mmio,0xff5e0000,115200n8". + and it will switch to normal serial console when the corresponding + port is ready. + "earlycon=uart8250,io,0x3f8,9600n8" + "earlycon=uart8250,mmio,0xff5e0000,115200n8". + it will not only setup early console. + + If unsure, say N. + +config SERIAL_ACP_CONSOLE_POLL + bool "Don't use interrupts in the ACP serial driver" + depends on SERIAL_ACP_CONSOLE + select CONSOLE_POLL + help + When selected, the ACP serial driver won't use interrupts. + This is only intended to be used for debugging. + + If unsure, say N. + +config LSI_NET + bool "Network interface for LSI's APP and ACP" + help + Network interface driver for LSI's APP and ACP series boards. + +config LSI_NET_NUM_RX_DESC + int "NIC driver: Number of receive descriptors" + depends on LSI_NET + default "4" + help + The number of receive descriptors to allocate. + +config LSI_NET_RX_BUF_SZ + int "NIC driver: Size of the receive buffer" + depends on LSI_NET + default "32768" + help + The size of the receive buffer. + +config LSI_NET_NUM_TX_DESC + int "NIC driver: Number of transmit descriptors" + depends on LSI_NET + default "4" + help + The number of transmit descriptors to allocate. + +config LSI_NET_TX_BUF_SZ + int "NIC driver: Size of the transmit buffer" + depends on LSI_NET + default "32768" + help + The size of the transmit buffer. + +config LSI_NAND + bool "NAND Driver for LSI's APP and ACP" + depends on ACP + select MTD_NAND + help + Add NAND support to LSI's APP/ACP boards. + +config LSI_UBOOTENV + bool "U-Boot Environment Access for LSI's APP and ACP" + depends on ( ACP && LSI_NAND && CRC32 ) + help + Add U-Boot environment access on LSI's APP/ACP boards. + +config LSI_PLX_PCIE_BRIDGE + bool "PLX 8608 PCIe bridge for LSI's ACP" + help + PLX 8608 configuration driver for LSI's ACP boards. + +endmenu diff --git a/drivers/lsi/Makefile b/drivers/lsi/Makefile new file mode 100644 index 0000000..ce6d25a --- /dev/null +++ b/drivers/lsi/Makefile @@ -0,0 +1 @@ +obj-y += acp/ diff --git a/drivers/lsi/acp/Makefile b/drivers/lsi/acp/Makefile new file mode 100644 index 0000000..6a8fca8 --- /dev/null +++ b/drivers/lsi/acp/Makefile @@ -0,0 +1,13 @@ +# Makefile for LSI drivers +# Note that some of these use the U-Boot environment, so nand must be first, +# then ubootenv... +obj-y += clocks.o +obj-$(CONFIG_ACP) += ncr.o +obj-$(CONFIG_LSI_NAND) += nand.o +obj-$(CONFIG_LSI_UBOOTENV) += ubootenv.o +obj-$(CONFIG_ACP) += version.o +obj-y += wrappers.o +obj-$(CONFIG_SERIAL_ACP) += serial.o +obj-$(CONFIG_LSI_NET) += net.o +obj-$(CONFIG_LSI_PLX_PCIE_BRIDGE) +=pci_plx.o +#obj-y += test.o diff --git a/drivers/lsi/acp/clocks.c b/drivers/lsi/acp/clocks.c new file mode 100644 index 0000000..c6d1389 --- /dev/null +++ b/drivers/lsi/acp/clocks.c @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2009 LSI Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define CLK_REF0 125000000 + +extern int is_asic(void); + +/* + =============================================================================== + =============================================================================== + Private Interface + =============================================================================== + =============================================================================== +*/ + +static unsigned char ps[] = {1, 3, 2, 4}; + +static unsigned char idiv[] = { + 1, 16, 17, 30, 13, 18, 7, 31, 14, 11, 19, 21, 27, 8, 23, 32, + 15, 29, 12, 6, 10, 20, 26, 22, 28, 5, 9, 25, 4, 24, 3, 2}; + +static unsigned char odiv[] = { + 1, 2, 28, 27, 22, 21, 30, 29, 24, 23, 12, 11, 16, 15, 32, 31, + 26, 25, 20, 19, 10, 9, 14, 13, 18, 17, 8, 7, 6, 5, 4, 3}; + +static unsigned char mult[] = { + 1, 123, 117, 251, 245, 69, 111, 125, 119, 95, 105, 197, 239, + 163, 63, 253, 247, 187, 57, 223, 233, 207, 157, 71, 113, 15, + 89, 37, 191, 19, 99, 127, 121, 109, 93, 61, 185, 155, 13, 97, + 107, 11, 9, 81, 31, 49, 83, 199, 241, 33, 181, 143, 217, 173, + 51, 165, 65, 85, 151, 147, 227, 41, 201, 255, 249, 243, 195, + 237, 221, 231, 35, 189, 59, 183, 79, 29, 141, 215, 145, 225, + 235, 219, 27, 139, 137, 135, 175, 209, 159, 53, 45, 177, 211, + 23, 167, 73, 115, 67, 103, 161, 55, 205, 87, 17, 91, 153, 7, + 47, 179, 171, 149, 39, 193, 229, 77, 213, 25, 133, 43, 21, + 101, 203, 5, 169, 75, 131, 3, 129, 1, 250, 244, 124, 118, 196, + 238, 252, 246, 222, 232, 70, 112, 36, 190, 126, 120, 60, 184, + 96, 106, 80, 30, 198, 240, 142, 216, 164, 64, 146, 226, 254, + 248, 236, 220, 188, 58, 28, 140, 224, 234, 138, 136, 208, 158, + 176, 210, 72, 114, 160, 54, 16, 90, 46, 178, 38, 192, 212, 24, + 20, 100, 168, 74, 128, 122, 116, 68, 110, 94, 104, 162, 62, + 186, 56, 206, 156, 14, 88, 18, 98, 108, 92, 154, 12, 10, 8, + 48, 82, 32, 180, 172, 50, 84, 150, 40, 200, 242, 194, 230, 34, + 182, 78, 214, 144, 218, 26, 134, 174, 52, 44, 22, 166, 66, + 102, 204, 86, 152, 6, 170, 148, 228, 76, 132, 42, 202, 4, 130, + 2 +}; + +#define PREDIV(value) (idiv[(((value) & 0xfc000000) >> 26)]) +#define MULTINT(value) (((value) & 0x00000ffe) >> 1) +#define MULTINT_PRE(value) (ps[((MULTINT((value)) & 0x300) >> 8)]) +#define MULTINT_MAIN(value) (mult[(MULTINT((value)) & 0xff)]) +#define RANGEA(value) (((value) & 0x03f80000) >> 19) +#define RANGEA_PRE(value) (ps[((RANGEA((value)) & 0x60) >> 5)]) +#define RANGEA_MAIN(value) (odiv[(RANGEA((value)) & 0x1f)]) +#define RANGEB(value) (((value) & 0x0007f000) >> 12) +#define RANGEB_PRE(value) (ps[((RANGEB((value)) & 0x60) >> 5)]) +#define RANGEB_MAIN(value) (odiv[(RANGEB((value)) & 0x1f)]) + +/* + ------------------------------------------------------------------------------ + get_ppc_pll + + Assumes the the PPC PLL is locked... +*/ + +static int +get_ppc_pll(unsigned long *dco, unsigned long *pllouta, unsigned long *plloutb) +{ + unsigned long ctrl; + + ctrl = mfdcr(0xd02); + + *dco = (CLK_REF0 / 1000 / PREDIV(ctrl)); + *dco *= (MULTINT_PRE(ctrl) * MULTINT_MAIN(ctrl)); + *pllouta = *dco / (RANGEA_PRE(ctrl) * RANGEA_MAIN(ctrl)); + *plloutb = *dco / (RANGEB_PRE(ctrl) * RANGEB_MAIN(ctrl)); + +#if 0 + printf("0x%x %d 0x%x (%d %d) 0x%x (%d %d) 0x%x (%d %d)\n", + ctrl, PREDIV(ctrl), + MULTINT(ctrl), MULTINT_PRE(ctrl), MULTINT_MAIN(ctrl), + RANGEA(ctrl), RANGEA_PRE(ctrl), RANGEA_MAIN(ctrl), + RANGEB(ctrl), RANGEB_PRE(ctrl), RANGEB_MAIN(ctrl)); +#endif + + return 0; +} + +/* + ------------------------------------------------------------------------------- + acp_clock_get_asic +*/ + +static int +acp_clock_get_asic(int clock, unsigned long *frequency) +{ + unsigned long mcgc; + unsigned long mcgs; + unsigned long dco = 0; + unsigned long pllouta; + unsigned long plloutb; + + *frequency = 0ULL; + + mcgc = mfdcr(0xd00); + mcgs = mfdcr(0xd01); + + switch (clock) { + case 0: /* PPC */ + if (0 == (mcgc & 0xc0000000)) { + /* ppc_clk is clk_ref0 */ + *frequency = CLK_REF0 / 1000; + } else if (0 == get_ppc_pll(&dco, &pllouta, &plloutb)) { + if (1 == ((mcgc & 0xc0000000) >> 30)) { + *frequency = pllouta; + } else { + *frequency = pllouta / 2; + } + } else { + return -1; + } + break; + case 1: /* Peripheral */ + if (0 == (mcgc & 0x08000000)) { + /* clk_per is clk_ref0 */ + *frequency = CLK_REF0 / 1000; + } else { + /* clk_per is clk_pllb_ppc */ + if (0 == (mcgs & 0x80000000) || + (0 == dco && + 0 != get_ppc_pll(&dco, &pllouta, &plloutb))) { + return -1; + } + + *frequency = plloutb; + } + break; + default: + return -1; + break; + } + + return 0; +} + +/* + ------------------------------------------------------------------------------- + acp_glock_get_emulation +*/ + +static int +acp_clock_get_emulation(int clock, unsigned long *frequency) +{ + *frequency = 0ULL; + + /* + Clocks are only available on the ASIC. + */ + switch (clock) { + case 0: /* PPC */ + *frequency = 12500; + break; + case 1: /* Peripheral */ + *frequency = 6500; + break; + default: + return -1; + break; + } + + return 0; +} + +/* + ------------------------------------------------------------------------------- + acp_glock_get_iss +*/ + +static int +acp_clock_get_iss(int clock, unsigned long *frequency) +{ + *frequency = 0ULL; + + /* + Clocks are only available on the ASIC. + */ + switch (clock) { + case 0: /* PPC */ + *frequency = 12500; + break; + case 1: /* Peripheral */ + *frequency = 6500; + break; + default: + return -1; + break; + } + + return 0; +} + +/* + =============================================================================== + =============================================================================== + Public Interface + =============================================================================== + =============================================================================== +*/ + +/* + ------------------------------------------------------------------------------- + acp_clock_get +*/ + +int +acp_clock_get(int clock, unsigned long *frequency) +{ +#ifdef CONFIG_ACPISS + return acp_clock_get_iss(clock, frequency); +#else + if (0 == is_asic()) { + return acp_clock_get_emulation(clock, frequency); + } else { + return acp_clock_get_asic(clock, frequency); + } + + return -1; +#endif +} +EXPORT_SYMBOL(acp_clock_get); diff --git a/drivers/lsi/acp/nand.c b/drivers/lsi/acp/nand.c new file mode 100644 index 0000000..7953e4f --- /dev/null +++ b/drivers/lsi/acp/nand.c @@ -0,0 +1,3666 @@ +/* + * drivers/lsi/acp/nand.c + * + * NAND Controller Driver for LSI's ACP + * + * Copyright (C) 2009 LSI Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* -- DEBUG --------------------------------------------------------- */ + +#undef DEBUG +/*#define DEBUG*/ +#if defined(DEBUG) +#define DEBUG_PRINT(format, args...) do { \ +printk(KERN_CRIT "appnic:%d - DEBUG - ", __LINE__); \ +printk(KERN_CRIT format, ##args); \ +} while (0); +#else +#define DEBUG_PRINT(format, args...) +#endif + +/* -- LOGIO --------------------------------------------------------- */ + +#undef LOGIO +#define LOGIO +#ifdef LOGIO +int enable_logio = 0; +static inline unsigned long _READL(const char *, int, unsigned long); +static inline unsigned long +_READL(const char *file, int line, unsigned long address) +{ + unsigned long value; + + value = readl(address); + + if (0 != enable_logio) + printk("%s:%d - Read 0x%08lx from 0x%08lx\n", + file, line, value, address); + + return value; +} +#define READL(address) _READL(__FILE__, __LINE__, (address)) +static inline void _WRITEL(const char *, int, unsigned long, unsigned long); +static inline void +_WRITEL(const char *file, int line, unsigned long value, unsigned long address) +{ + writel(value, address); + + if (0 != enable_logio) + printk( "%s:%d - Wrote 0x%08lx to 0x%08lx\n", + file, line, value, address); + + return; +} +#define WRITEL(value, address) _WRITEL(__FILE__, __LINE__, (value), (address)) +#else /* LOGIO */ +#define READL(address) readl((address)) +#define WRITEL(value, address) writel((value), (address)) +#endif /* LOGIO */ + +/* + ---------------------------------------------------------------------- +*/ + +#define NAND_DATA_REG 0x00000000 +#define NAND_CMD_REG 0x00008000 +#define NAND_INDEX_REG 0x00008004 +#define NAND_STATUS1_REG 0x00008008 +#define NAND_STATUS2_REG 0x0000800C +#define NAND_ID0_REG 0x00008010 +#define NAND_ID1_REG 0x00008014 +#define NAND_ID2_REG 0x00008018 +#define NAND_ID3_REG 0x0000801C +#define NAND_ID4_REG 0x00008020 +#define NAND_ID5_REG 0x00008024 +#define NAND_ID6_REG 0x00008028 +#define NAND_ID7_REG 0x0000802C +#define NAND_INTR_EN_REG 0x00008030 +#define NAND_INTR_STATUS_REG 0x00008034 +#define NAND_INTR_REG 0x00008038 +#define NAND_ECC_ADDR_LOG_REG 0x0000803C +#define NAND_ECC_VAL_REG 0x00008040 +#define NAND_ECC_INJECT_REG 0x00008044 +#define NAND_EXT_INDEX_REG 0x00008048 +#define NAND_TIMING1_REG 0x0000804C +#define NAND_TIMING2_REG 0x00008050 +#define NAND_CONFIG_REG 0x00008054 +#define NAND_PECC_REG 0x00008058 + +#define EP501_NAND_DATA_REG 0x0000 +#define EP501_NAND_CMD_REG 0x8000 +#define EP501_NAND_INDEX_REG 0x8004 +#define EP501_NAND_STATUS0_REG 0x8008 +#define EP501_NAND_STATUS1_REG 0x800C +#define EP501_NAND_ID0_REG 0x8010 +#define EP501_NAND_ID1_REG 0x8014 +#define EP501_NAND_ID2_REG 0x8018 +#define EP501_NAND_ID3_REG 0x801C +#define EP501_NAND_ID4_REG 0x8020 +#define EP501_NAND_ID5_REG 0x8024 +#define EP501_NAND_ID6_REG 0x8028 +#define EP501_NAND_ID7_REG 0x802C +#define EP501_NAND_INTR_EN_REG 0x8030 +#define EP501_NAND_INTR_STATUS_REG 0x8034 +#define EP501_NAND_INTR_REG 0x8038 +#define EP501_NAND_ECC_ADDR_LOG_REG 0x803C +#define EP501_NAND_ECC_VAL_REG 0x8040 +#define EP501_NAND_ECC_INJECT_REG 0x8044 +#define EP501_NAND_EXT_INDEX_REG 0x8048 +#define EP501_NAND_TIMING0_REG 0x804C +#define EP501_NAND_TIMING1_REG 0x8050 +#define EP501_NAND_CONFIG_REG 0x8054 +#define EP501_NAND_PECC_REG 0x8058 + +#define EP501G1_NAND_DATA_REG 0x0000 +#define EP501G1_NAND_CMD_REG 0x8000 +#define EP501G1_NAND_INDEX_REG 0x8004 +#define EP501G1_NAND_STATUS0_REG 0x8008 +#define EP501G1_NAND_ID0_REG 0x8010 +#define EP501G1_NAND_ID2_REG 0x8018 +#define EP501G1_NAND_ID4_REG 0x8020 +#define EP501G1_NAND_ID6_REG 0x8028 +#define EP501G1_NAND_INTR_EN_REG 0x8030 +#define EP501G1_NAND_INTR_STATUS_REG 0x8034 +#define EP501G1_NAND_INTR_REG 0x8038 +#define EP501G1_NAND_EXT_INDEX_REG 0x8048 +#define EP501G1_NAND_TIMING0_REG 0x804C +#define EP501G1_NAND_TIMING1_REG 0x8050 +#define EP501G1_NAND_CONFIG_REG 0x8054 +#define EP501G1_NAND_1BIT_ECC0_STATUS 0x8058 +#define EP501G1_NAND_1BIT_ECC1_STATUS 0x805c +#define EP501G1_NAND_1BIT_ECC2_STATUS 0x8060 +#define EP501G1_NAND_1BIT_ECC3_STATUS 0x8064 +#define EP501G1_NAND_1BIT_ECC4_STATUS 0x8068 +#define EP501G1_NAND_1BIT_ECC5_STATUS 0x806c +#define EP501G1_NAND_1BIT_ECC6_STATUS 0x8070 +#define EP501G1_NAND_1BIT_ECC7_STATUS 0x8074 +#define EP501G1_NAND_BCH_STATUS 0x807c +#define EP501G1_NAND_SYN_R12_S0 0x8080 +#define EP501G1_NAND_SYN_R34_S0 0x8084 +#define EP501G1_NAND_SYN_R56_S0 0x8088 +#define EP501G1_NAND_SYN_R78_S0 0x808c +#define EP501G1_NAND_SYN_R12_S1 0x8090 +#define EP501G1_NAND_SYN_R34_S1 0x8094 +#define EP501G1_NAND_SYN_R56_S1 0x8098 +#define EP501G1_NAND_SYN_R78_S1 0x809c +#define EP501G1_NAND_SYN_R12_S2 0x80a0 +#define EP501G1_NAND_SYN_R34_S2 0x80a4 +#define EP501G1_NAND_SYN_R56_S2 0x80a8 +#define EP501G1_NAND_SYN_R78_S2 0x80ac +#define EP501G1_NAND_SYN_R12_S3 0x80b0 +#define EP501G1_NAND_SYN_R34_S3 0x80b4 +#define EP501G1_NAND_SYN_R56_S3 0x80b8 +#define EP501G1_NAND_SYN_R78_S3 0x80bc +#define EP501G1_NAND_SYN_R12_S4 0x80c0 +#define EP501G1_NAND_SYN_R34_S4 0x80c4 +#define EP501G1_NAND_SYN_R56_S4 0x80c8 +#define EP501G1_NAND_SYN_R78_S4 0x80cc +#define EP501G1_NAND_SYN_R12_S5 0x80d0 +#define EP501G1_NAND_SYN_R34_S5 0x80d4 +#define EP501G1_NAND_SYN_R56_S5 0x80d8 +#define EP501G1_NAND_SYN_R78_S5 0x80dc +#define EP501G1_NAND_SYN_R12_S6 0x80e0 +#define EP501G1_NAND_SYN_R34_S6 0x80e4 +#define EP501G1_NAND_SYN_R56_S6 0x80e8 +#define EP501G1_NAND_SYN_R78_S6 0x80ec +#define EP501G1_NAND_SYN_R12_S7 0x80f0 +#define EP501G1_NAND_SYN_R34_S7 0x80f4 +#define EP501G1_NAND_SYN_R56_S7 0x80f8 +#define EP501G1_NAND_SYN_R78_S7 0x80fc + +#define EP501G3_NAND_DATA_REG 0x0000 +#define EP501G3_NAND_CMD_REG 0x8000 +#define EP501G3_NAND_INDEX_REG 0x8004 +#define EP501G3_NAND_STATUS0_REG 0x8008 +#define EP501G3_NAND_ID0_REG 0x8010 +#define EP501G3_NAND_ID2_REG 0x8018 +#define EP501G3_NAND_ID4_REG 0x8020 +#define EP501G3_NAND_ID6_REG 0x8028 +#define EP501G3_NAND_INTR_EN_REG 0x8030 +#define EP501G3_NAND_INTR_STATUS_REG 0x8034 +#define EP501G3_NAND_INTR_REG 0x8038 +#define EP501G3_NAND_EXT_INDEX_REG 0x8048 +#define EP501G3_NAND_TIMING0_REG 0x804C +#define EP501G3_NAND_TIMING1_REG 0x8050 +#define EP501G3_NAND_CONFIG_REG 0x8054 +#define EP501G3_NAND_TIMING2_REG 0x805c +#define EP501G3_NAND_BCH_STATUS 0x807c +#define EP501G3_NAND_SYN_R12_S0 0x8080 +#define EP501G3_NAND_SYN_R34_S0 0x8084 +#define EP501G3_NAND_SYN_R56_S0 0x8088 +#define EP501G3_NAND_SYN_R78_S0 0x808c +#define EP501G3_NAND_SYN_R12_S1 0x8090 +#define EP501G3_NAND_SYN_R34_S1 0x8094 +#define EP501G3_NAND_SYN_R56_S1 0x8098 +#define EP501G3_NAND_SYN_R78_S1 0x809c +#define EP501G3_NAND_SYN_R12_S2 0x80a0 +#define EP501G3_NAND_SYN_R34_S2 0x80a4 +#define EP501G3_NAND_SYN_R56_S2 0x80a8 +#define EP501G3_NAND_SYN_R78_S2 0x80ac +#define EP501G3_NAND_SYN_R12_S3 0x80b0 +#define EP501G3_NAND_SYN_R34_S3 0x80b4 +#define EP501G3_NAND_SYN_R56_S3 0x80b8 +#define EP501G3_NAND_SYN_R78_S3 0x80bc +#define EP501G3_NAND_SYN_R12_S4 0x80c0 +#define EP501G3_NAND_SYN_R34_S4 0x80c4 +#define EP501G3_NAND_SYN_R56_S4 0x80c8 +#define EP501G3_NAND_SYN_R78_S4 0x80cc +#define EP501G3_NAND_SYN_R12_S5 0x80d0 +#define EP501G3_NAND_SYN_R34_S5 0x80d4 +#define EP501G3_NAND_SYN_R56_S5 0x80d8 +#define EP501G3_NAND_SYN_R78_S5 0x80dc +#define EP501G3_NAND_SYN_R12_S6 0x80e0 +#define EP501G3_NAND_SYN_R34_S6 0x80e4 +#define EP501G3_NAND_SYN_R56_S6 0x80e8 +#define EP501G3_NAND_SYN_R78_S6 0x80ec +#define EP501G3_NAND_SYN_R12_S7 0x80f0 +#define EP501G3_NAND_SYN_R34_S7 0x80f4 +#define EP501G3_NAND_SYN_R56_S7 0x80f8 +#define EP501G3_NAND_SYN_R78_S7 0x80fc +#define EP501G3_NAND_SYN_R12_S8 0x8100 +#define EP501G3_NAND_SYN_R34_S8 0x8104 +#define EP501G3_NAND_SYN_R56_S8 0x8108 +#define EP501G3_NAND_SYN_R78_S8 0x810c +#define EP501G3_NAND_SYN_R12_S9 0x8110 +#define EP501G3_NAND_SYN_R34_S9 0x8114 +#define EP501G3_NAND_SYN_R56_S9 0x8118 +#define EP501G3_NAND_SYN_R78_S9 0x811c +#define EP501G3_NAND_SYN_R12_S10 0x8120 +#define EP501G3_NAND_SYN_R34_S10 0x8124 +#define EP501G3_NAND_SYN_R56_S10 0x8128 +#define EP501G3_NAND_SYN_R78_S10 0x812c +#define EP501G3_NAND_SYN_R12_S11 0x8130 +#define EP501G3_NAND_SYN_R34_S11 0x8134 +#define EP501G3_NAND_SYN_R56_S11 0x8138 +#define EP501G3_NAND_SYN_R78_S11 0x813c +#define EP501G3_NAND_SYN_R12_S12 0x8140 +#define EP501G3_NAND_SYN_R34_S12 0x8144 +#define EP501G3_NAND_SYN_R56_S12 0x8148 +#define EP501G3_NAND_SYN_R78_S12 0x814c +#define EP501G3_NAND_SYN_R12_S13 0x8150 +#define EP501G3_NAND_SYN_R34_S13 0x8154 +#define EP501G3_NAND_SYN_R56_S13 0x8158 +#define EP501G3_NAND_SYN_R78_S13 0x815c +#define EP501G3_NAND_SYN_R12_S14 0x8160 +#define EP501G3_NAND_SYN_R34_S14 0x8164 +#define EP501G3_NAND_SYN_R56_S14 0x8168 +#define EP501G3_NAND_SYN_R78_S14 0x816c +#define EP501G3_NAND_SYN_R12_S15 0x8170 +#define EP501G3_NAND_SYN_R34_S15 0x8174 +#define EP501G3_NAND_SYN_R56_S15 0x8178 +#define EP501G3_NAND_SYN_R78_S15 0x817c + +/* + ============================================================================== + ============================================================================== + Some Oddities... + + -1- + Reading EP501 registers while the device is calculating ECC will + hang the AHB. As the only way to know that an ECC calculation is in + progress is to read the "extra bits" added to the interrupt status + register, this can cause problems. To get around this, the + PECC_BUSY signal from the controller is also available in a general + purpose system register. 0x149.0.0xc/0x0020_0040_0000_c00c, bit 24. + So, before reading the interrupt status register (or any other + register for that matter) make sure the bit mentioned above is + clear. See BZ21212. + + -2- + Extra bits have been added to the interrupt status register. See + BZ21196. From that defect... + + == Bit 0 + This bit is set when un-correctable ECC is detected. This bit can be + cleared by writing "0" to this register. Writing "1" has no + effect. An interrupt is generated if this bit and the enable bit + (bit 0) in the Interrupt Enable Register are "1". This bit is not + set if ECC is disabled. + + == Bit 1 + This bit is set when correctable ECC is detected. This bit can be + cleared by writing "0" to this register. Writing "1" has no + effect. An interrupt is generated if this bit and the enable bit + (bit 1) in the Interrupt Enable Register are "1". This bit is not + set if ECC is disabled. + + == Bit 2 + This bit is set when a rising edge is detected on the non gated + READY/BUSY# input from the NAND Flash. This bit can be cleared by + writing a "0" to this register. Writing a "1" has no effect. An + interrupt is generated if this bit and the enable bit (bit 2) in the + Interrupt Enable Register are "1". + + == Bit 3 + This bit is set when a falling edge is detected on the non gated + READY/BUSY# input from the NAND Flash. This bit can be cleared by + writing a "0" to this register. Writing a "1" has no effect. An + interrupt is generated if this bit and the enable bit (bit 3) in the + Interrupt Enable Register are "1". + + == Bit 4 + This bit is set when a falling edge is detected on the PECC_BUSY + signal which indicates when the NAND controller has taken control of + the NAND Flash for ECC byte access. This bit can be cleared by + writing a "0" to this register. Writing a "1" has no effect. An + interrupt is generated if this bit and the enable bit (bit 4) in the + Interrupt Enable Register are "1". + + == Bit 5 + This bit is read only and is the synchronized level on the non gated + READY/BUSY# input from the NAND Flash. This bit can be used to poll + the status of this signal and is not used to generate an interrupt. + + == Bit 6 + This bit is read only and indicates the level on the PECC_BUSY + signal which indicates when the NAND controller has taken control of + the NAND Flash for ECC byte access. This bit can be used to poll the + level of this signal and is not used to generate an interrupt. + + ============================================================================== + ============================================================================== +*/ + +static void *gpreg_base; + +#define LSI_NAND_PECC_BUSY_REGISTER (gpreg_base + 0x00c) + +#ifdef CONFIG_ACP_X1V1 +#define LSI_NAND_PECC_BUSY_MASK (1 << 25) +#else +#define LSI_NAND_PECC_BUSY_MASK (1 << 28) +#endif + +/* + ---------------------------------------------------------------------- + MTD structures +*/ + +static struct mtd_info lsi_nand_mtd = { 0 }; +static struct nand_chip lsi_nand_chip = { 0 }; + +#define NAND_CMD_START_ECC_READ 0x23 + +#define NAND_CMD_CE_OFF_501 0xEE +#define NAND_CMD_CE_OFF_501G1 0xEE +#define NAND_CMD_CE_OFF_501G3 0xFE +static int nand_cmd_ce_off; + +typedef union { + unsigned long raw; + + struct { +#ifdef CONFIG_ACP + unsigned long th:8; + unsigned long trp:8; + unsigned long twp:8; + unsigned long ts:8; +#else + unsigned long ts:8; + unsigned long twp:8; + unsigned long trp:8; + unsigned long th:8; +#endif + } __attribute__ ((packed)) bits; +} nand_timing_control_register_0_t; + +typedef union { + unsigned long raw; + + struct { +#ifdef CONFIG_ACP + unsigned long twb:8; + unsigned long trr:8; + unsigned long trh:8; + unsigned long twh:8; +#else + unsigned long twh:8; + unsigned long trh:8; + unsigned long trr:8; + unsigned long twb:8; +#endif + } __attribute__ ((packed)) bits; +} __attribute__ ((packed)) nand_timing_control_register_1_t; + +typedef union { + unsigned long raw; + + struct { +#ifdef CONFIG_ACP + unsigned long : 8; + unsigned long trhw : 8; + unsigned long twhr : 8; + unsigned long tccs : 8; +#else + unsigned long tccs : 8; + unsigned long twhr : 8; + unsigned long trhw : 8; + unsigned long : 8; +#endif + } __attribute__ ( ( packed ) ) bits; +} __attribute__ ( ( packed ) ) nand_timing_control_register_2_t; + +typedef enum { + LSI_NAND_NONE, LSI_NAND_EP501, LSI_NAND_EP501G1, LSI_NAND_EP501G3 +} lsi_nand_type_t; + +static lsi_nand_type_t lsi_nand_type; + +typedef struct page_wise_ecc_status_st { + unsigned err_bit : 3; + unsigned column : 9; + unsigned status : 2; + unsigned rsvd : 18; +} page_wise_ecc_status_t; + +/* + =============================================================================== + =============================================================================== + Concerning ECC + + The EP501 only supports 1 bit ECC mode. The EP501G1 supports both 1 + bit and 4 bit modes. The EP501G3 supports 4 bit, 8 bit, and 12 bit. + The NAND part normally used on ACP boards has 2K pages (supported by + all three controllers) with 64 bytes of OOB. For a 2K page, 1 bit + ECC uses 12 bytes, 4 bit ECC uses 32 bytes, 8 bit ECC uses 64 bytes + and 12 bit ECC uses 80 bytes. In order to to keep the bad block + markers (first two bytes) and leave some OOB available for file + systems etc., this driver only supports 1 bit ECC or 4 bit ECC. + + For now, the EP501 version will use 1 bit ECC (only option), the + EP501G1 version will use 4 bit (for compabitility with the EP501G3) + and teh EP501G3 versions will use 4 bit (due to the amount of OOB + required and for compatibility with the EP501G1). + + EP501 + + The driver has not been tested with small page (512 byte) devices. + The only usable option is 2K. So, the OOB should be 64 bytes. The + first 2 bytes are reserved for marking bad blocks. The last 12 + bytes are reserved for ECC. All other bytes are free. See + lsi_ep501_2k_ecclayout below. + + EP501G1 + + This driver has been tested with 2K and 4K page sizes using 1 bit + and 4 bit ECC. + =============================================================================== + =============================================================================== +*/ + +static struct nand_ecclayout lsi_2k_1bit_ecclayout = { + .eccbytes = 12, + .eccpos = { + 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63}, + .oobfree = {{2, 50}} +}; + +static struct nand_ecclayout lsi_4k_1bit_ecclayout = { + .eccbytes = 24, + .eccpos = { + 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63}, + .oobfree = {{2, 50}} +}; + +static struct nand_ecclayout lsi_2k_4bit_ecclayout = { + .eccbytes = 32, + .eccpos = { + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = {{2, 30}} +}; + +static struct nand_ecclayout lsi_4k_4bit_ecclayout = { + .eccbytes = 64, + .eccpos = { + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127 + }, + .oobfree = {{2, 63}} +}; + +static struct nand_ecclayout lsi_8k_4bit_ecclayout = { + .eccbytes = 128, + .eccpos = { + 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 175, + 176, 177, 178, 179, 180, 181, 182, 183, + 184, 185, 186, 187, 188, 189, 190, 191, + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 222, 223, + 224, 225, 226, 227, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 237, 238, 239, + 240, 241, 242, 243, 244, 245, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255 + }, + .oobfree = {{2, 126}} +}; + +static struct mtd_partition *partition_info; +static const char *probes[] = { "cmdlinepart", NULL }; + +/* + ------------------------------------------------------------------------------- + lsi_nand_hwcontrol +*/ + +static void +lsi_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *chip = mtd->priv; + + if (cmd != NAND_CMD_NONE) { + WRITEL (cmd, (chip->IO_ADDR_W + NAND_CMD_REG)); + } + + return; +} + +/* + ------------------------------------------------------------------------------ + lsi_nand_device_ready + + The READ/BUSY# input from the NAND device(s) (ORed if there are more + than one) is availble as an extra bit in the interrupt status + register. Note that this register shouldn't be read unless the + controller is not in the middle of calculating ECC (see "Some + Oddities..." above). +*/ + +static int +lsi_nand_device_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + unsigned long interrupt_status; + + /* Get the status. */ + interrupt_status = READL(chip->IO_ADDR_R + NAND_INTR_STATUS_REG); + + return interrupt_status & NAND_STATUS_TRUE_READY; +} + +/** + * lsi_nand_command - [DEFAULT] Send command to NAND large page device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This is the version for the new large page + * devices We dont have the separate regions as we have in the small page + * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. + */ +static void +lsi_nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + register struct nand_chip *chip = mtd->priv; + unsigned int status = 0; + + DEBUG_PRINT("command=0x%x\n", command); + command &= 0xff; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* return if unhandled command is issued */ + if (command != NAND_CMD_READ0 && + command != NAND_CMD_SEQIN && + command != NAND_CMD_ERASE1 && + command != NAND_CMD_STATUS && + command != NAND_CMD_READID && + command != NAND_CMD_RESET && + command != NAND_CMD_START_ECC_READ && + command != NAND_CMD_PAGEPROG && + command != NAND_CMD_ERASE2) { + printk(KERN_ERR + "lsi_nand_command(): WARN: Unhandled command 0x%x " + "issued for page=0x%x, column=0x%x.\n", + command, page_addr, column); + return; + } + + /* Command latch cycle */ + chip->cmd_ctrl(mtd, command, + NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); + + if (column != -1 || page_addr != -1) { + unsigned long index = 0; + unsigned long extended_index = 0; + + /* column number */ + /* + Since the ACP uses 8 bit device access, only that + mode is supported. + */ + + if (LSI_NAND_EP501 == lsi_nand_type) { + /* column number */ + if (column != -1) + index = column & 0xfff; + + /* page and block number */ + if (page_addr != -1) + index += ((page_addr & 0x7ffff) << 12); + } else { + /* column number */ + if (-1 != column) { + switch (mtd->writesize) { + case 512: + index |= (column & 0x1ff); + break; + case 2048: + index |= (column & 0xfff); + break; + case 4096: + index |= (column & 0x1fff); + break; + default: + break; + } + } + + /* page_addr and block number */ + if (-1 != page_addr) { + switch (mtd->writesize) { + case 512: + index |= (page_addr & 0x7fffff) << 9; + break; + case 2048: + index |= (page_addr & 0xfffff) << 12; + extended_index |= (page_addr & 0xfff00000); + break; + case 4096: + index |= (page_addr & 0x7ffff) << 13; + extended_index |= (page_addr & 0xfff80000); + break; + default: + break; + } + } + } + + /* write index reg */ + WRITEL(index, chip->IO_ADDR_W + NAND_INDEX_REG); + + /* write ext index reg */ + WRITEL(extended_index, chip->IO_ADDR_W + NAND_EXT_INDEX_REG); + + mb(); + } + + /* for read command, send 0xe0 so data is populated */ + if (command == NAND_CMD_READ0) { + chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, + NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); + do { + udelay(chip->chip_delay); + status = READL((void *)LSI_NAND_PECC_BUSY_REGISTER); + } while (0 != (status & LSI_NAND_PECC_BUSY_MASK)); + + /* wait until CHIP_BUSY goes low */ + do { + udelay(chip->chip_delay); + status = chip->dev_ready(mtd); + } while (!status); + } else if (command == NAND_CMD_STATUS) { + udelay(chip->chip_delay); + } + + return; +} + +/** + * lsi_nand_read_buf - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 8bit buswith + */ +static void lsi_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i = 0; + struct nand_chip * chip = (struct nand_chip *) mtd->priv; + uint32_t * p = (uint32_t *)buf; + +#if defined(LOGIO) + if (0 != enable_logio) + printk("Reading NAND Buffer (len=%d)...\n", len); +#endif + + for (i = 0; i < (len >> 2); i++) { + p[i] = readl(chip->IO_ADDR_R); + } + + return; +} + +/** + * lsi_nand_write_buf - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 8bit buswith + */ +static void +lsi_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + int i = 0; + struct nand_chip *chip = mtd->priv; + uint32_t *p = (uint32_t *)buf; + +#if defined(LOGIO) + if (0 != enable_logio) + printk("Writing NAND Buffer (len=%d)...\n", len); +#endif + + for (i = 0; i < (len >> 2); i++) { + writel(p[i], chip->IO_ADDR_W); + } + + return; +} + +/** + * lsi_nand_verify_buf - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 8bit buswith + */ +static int lsi_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + uint32_t *p = (uint32_t *)buf; + + for (i = 0; i < (len >> 2); i++) { + udelay(chip->chip_delay); + if (p[i] != readl((uint32_t *)chip->IO_ADDR_R)) { + return -EFAULT; + } + } + + return 0; +} + +static int lsi_nand_read_status(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 0); + + return READL(chip->IO_ADDR_R + NAND_STATUS1_REG) & 0xff; +} + + +/** + * lsi_nand_wait - [DEFAULT] wait until the command is done + * @mtd: MTD device structure + * @chip: NAND chip structure + * + * Wait for command done. This applies to erase and program only + * Erase can take up to 400ms and program up to 20ms according to + * general NAND and SmartMedia specs + */ +static int lsi_nand_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + unsigned long status = 0; + loff_t offset = 0; + + /* + When reading or writing, wait for the + controller's PECC_BUSY signal to clear. + */ +#if 0 + if (FL_READING == chip->state || FL_WRITING == chip->state) { + for (;;) { + status = READL((void *)LSI_NAND_PECC_BUSY_REGISTER); + + if (0 == (status & LSI_NAND_PECC_BUSY_MASK)) + break; + + udelay(chip->chip_delay); + } + } +#else + for (;;) { + status = READL((void *)LSI_NAND_PECC_BUSY_REGISTER); + + if (0 == (status & LSI_NAND_PECC_BUSY_MASK)) + break; + + udelay(chip->chip_delay); + } +#endif + + /* + In all cases, wait for the NAND device to be "ready". + + N.B. The FL_READING case is handled in lsi_nand_command(). + */ + + if (FL_WRITING == chip->state || FL_ERASING == chip->state) { + for (;;) { + if (chip->dev_ready(mtd)) + break; + + udelay(chip->chip_delay); + } + } + + /* + Then get the status. + */ + + for (;;) { + status = lsi_nand_read_status(mtd); + + if (0 != (status & NAND_STATUS_READY)) + break; + + udelay(chip->chip_delay); + } + + if (status & NAND_STATUS_FAIL) { + offset = (READL(chip->IO_ADDR_R + NAND_INDEX_REG) / + mtd->writesize) * mtd->writesize; + printk(KERN_ERR + "lsi_nand_wait(): Action %d failed for " + "Offset: 0x%llx, status 0x%lx\n", + chip->state, offset, status); + } + + return status; +} + +/* + lsi_nand_ecc_hwctl +*/ + +void +lsi_nand_ecc_hwctl(struct mtd_info *mtd, int mode) +{ + /* nothing to do to enable ECC */ + return; +} + +/** + * lsi_nand_ecc_calculate + */ + +int +lsi_nand_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + struct nand_chip *chip = mtd->priv; + + /* start ECC calculation */ + if (chip->state == FL_READING) { + chip->cmdfunc(mtd, NAND_CMD_START_ECC_READ, -1, -1); + } else if (chip->state == FL_WRITING) { + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + } + + /* wait for PECC_BUSY to go down */ + return chip->waitfunc(mtd, chip); +} + +/** + * lsi_nand_ecc_correct + */ + +int +lsi_nand_ecc_correct(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, + uint8_t *calc_ecc) +{ + /* nothing to do to correct ECC */ + return 0; +} + +/* + ------------------------------------------------------------------------------ + report_ecc_errors_ep501 +*/ + +static int +report_ecc_errors_ep501(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buffer, int page) +{ + int rc = 0; + unsigned long ecc_status; + page_wise_ecc_status_t *ecc_status_reg = + (page_wise_ecc_status_t *)&ecc_status; + int column; + int i; + + for (i = 0; i < (mtd->writesize >> 9); i++) { + ecc_status = READL(chip->IO_ADDR_R + EP501_NAND_PECC_REG); + column = (i << 9) + ecc_status_reg->column; + + if (1 == ecc_status_reg->status) { + printk(KERN_NOTICE + "Single ECC Error: " + "Page=0x%x Column=0x%x Bit=0x%x\n", + page, column, ecc_status_reg->err_bit); + + if (column < mtd->writesize) { + buffer[column] ^= (1 << ecc_status_reg->err_bit); + ++mtd->ecc_stats.corrected; + } else { + printk(KERN_ERR + "Single ECC Error Not Corrected: " + "Column 0x%x not in " + "Page Size 0x%x\n", + column, mtd->writesize); + rc = -1; + } + } else if((ecc_status & 0x3000) == 2) { + printk(KERN_ERR + "Uncorrectable ECC Error: " + "Page=0x%x Column=0x%x\n", + page, column); + rc = -1; + } + } + + return rc; +} + +int i_to_a[8192] = { + -1, 0, 1, 7953, 2, 7715, 7954, 3551, 3, 3313, 7716, 5441, + 7955, 1529, 3552, 7477, 4, 7239, 3314, 1441, 7717, 7102, 5442, + 1291, 7956, 7545, 1530, 3075, 3553, 5203, 7478, 2784, 5, 2546, + 7240, 5080, 3315, 4596, 1442, 4965, 7718, 466, 7103, 7307, + 5443, 2837, 1292, 822, 7957, 801, 7546, 7001, 1531, 1203, + 3076, 4294, 3554, 1053, 5204, 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4717, 373, 746, 1492, 2984, 5968, 2831, 5662, + 2451, 4902, 995, 1990, 3980, 7960, 7071, 4753, 141, 282, 564, + 1128, 2256, 4512, 1775, 3550, 7100, 4823, 0 +}; + +static int err_loc_ply[100][100]; + +static int +fix_section(unsigned long offset, void *data, int *syndromes_in) +{ + int i, j, elp_sum; + int syndromes[9]; + int Matrix_a[11]; + int Matrix_b[11]; + int Matrix_c[12]; + int Element[7]; + int alpha; + int temp_index; + int data_location, rev_location; + int result_byte, result_bit; + int err_location[20]; + int err_count; + int d_flg; + int block_length, data_length; + + /* correct 4 bits in 512 bytes */ + data_length = 4096; + block_length = 8191; + + /* + If there are no errors, just return. + */ + + j = 0; + + for (i = 0; i < 8; ++i) { + if (0 != syndromes_in[i]) { + j = 1; + break; + } + } + + if (0 == j) + return 0; + + /* + Decode. + */ + + memcpy((void *)syndromes, (void *)syndromes_in, sizeof(int) * 9); + d_flg = 0; + + // initialise table entries + for (i = 0; i < 8; i++) + syndromes[i] = i_to_a[syndromes[i]]; + + Matrix_c[0] = 0; + Matrix_c[1] = syndromes[0]; + err_loc_ply[0][0] = 1; + err_loc_ply[1][0] = 1; + for (i = 1; i < 8; i++) { + err_loc_ply[0][i] = 0; + err_loc_ply[1][i] = 0; + } + Matrix_a[0] = 0; + Matrix_a[1] = 0; + Matrix_b[0] = -1; + Matrix_b[1] = 0; + alpha = -1; + + do { + // skip even loops + alpha += 2; + if (Matrix_c[alpha] != -1) { + temp_index = alpha - 2; + if (temp_index<0) temp_index=0; + while ((Matrix_c[temp_index] == -1) && (temp_index > 0)) + temp_index=temp_index-2; + if (temp_index < 0) temp_index = 0; + + if (temp_index > 0) { + j = temp_index; + do { + j=j-2; + if (j < 0) j = 0; + if ((Matrix_c[j] != -1) && (Matrix_b[temp_index] < Matrix_b[j])) + temp_index = j; + } while (j > 0); + } + + if (Matrix_a[alpha] > Matrix_a[temp_index] + alpha - temp_index) + Matrix_a[alpha + 2] = Matrix_a[alpha]; + else + Matrix_a[alpha + 2] = Matrix_a[temp_index] + alpha - temp_index; + + for (i = 0; i < 8; ++i) { + err_loc_ply[alpha + 2][i] = 0; + } + + for (i = 0; i <= Matrix_a[temp_index]; i++) { + if (err_loc_ply[temp_index][i] != 0) + err_loc_ply[alpha + 2][i + alpha - temp_index] = + a_to_i[(Matrix_c[alpha] + block_length - + Matrix_c[temp_index] + + i_to_a[err_loc_ply[temp_index][i]]) % + block_length]; + } + + for (i = 0; i <= Matrix_a[alpha]; i++) { + err_loc_ply[alpha + 2][i] ^= err_loc_ply[alpha][i]; + } + } else { + Matrix_a[alpha + 2] = Matrix_a[alpha]; + + for (i = 0; i <= Matrix_a[alpha]; i++) { + err_loc_ply[alpha + 2][i] = err_loc_ply[alpha][i]; + } + } + + Matrix_b[alpha + 2] = alpha+1 - Matrix_a[alpha + 2]; + + // Form (alpha+2)th discrepancy. + if (alpha < 8) { + if (syndromes[alpha + 1] != -1) { + Matrix_c[alpha + 2] = a_to_i[syndromes[alpha + 1]]; + } else { + Matrix_c[alpha + 2] = 0; + } + + for (i = 1; i <= Matrix_a[alpha + 2]; i++) { + if ((syndromes[alpha + 1 - i] != -1) && (err_loc_ply[alpha + 2][i] != 0)) + Matrix_c[alpha + 2] ^= a_to_i[(syndromes[alpha + 1 - i] + i_to_a[err_loc_ply[alpha + 2][i]]) % block_length]; + } + Matrix_c[alpha + 2] = i_to_a[Matrix_c[alpha + 2]]; + } + } while ((alpha < 7) && (Matrix_a[alpha + 2] <= 4)); + + alpha=alpha+2; + Matrix_a[7] = Matrix_a[alpha]; + if (Matrix_a[7] <= 4) { + + for (i = 1; i <= Matrix_a[7]; i++) { + Element[i] = i_to_a[err_loc_ply[alpha][i]]; + } + + err_count = 0 ; + for (i = 1; i <= block_length; i++) { + elp_sum = 1 ; + for (j = 1; j <= Matrix_a[7]; j++) + if (Element[j] != -1) { + Element[j] = (Element[j] + j) % block_length ; + elp_sum ^= a_to_i[Element[j]] ; + } + + if (!elp_sum) { + err_location[err_count] = block_length - i ; + err_count++ ; + } + } + + if (err_count == Matrix_a[7]) + d_flg = 1 ; + } + + if (d_flg == 0) { + return -1; + } + else { + for (i=0; i= 52) + data_location = err_location[i] - 52; + else + data_location = err_location[i] + data_length; + + if (data_location <= 4095) + { + rev_location = 4095 - data_location; + result_bit = rev_location%8; + result_byte = (rev_location - result_bit)/8; + + printk(KERN_NOTICE + "Corrected ECC Error: " + "offset 0x%lx byte 0x%x bit %d\n", + offset, result_byte, result_bit); + + result_byte = + (result_byte & 0xfffffffc) | + ((result_byte & 0x3) ^ 0x3); + *((unsigned char *)(data + + result_byte)) ^= + (1 << result_bit); + } else { + rev_location = 4147 - data_location; + result_bit = rev_location%8; + result_byte = (rev_location - result_bit)/8; + printk(KERN_ERR + "BCH byte = %d, bit = %d\n", + result_byte, result_bit); + } + } + + if (0 != err_count) + return 1; + else + return 0; + } +} + +/* + ------------------------------------------------------------------------------ + report_ecc_errors_ep501g1 +*/ + +static int +report_ecc_errors_ep501g1(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buffer, int page) +{ + unsigned long bch_status; + int rc = 0; + int i; + int is_blank = 1; + uint8_t *data = buffer; + int section; + int syndrome; + unsigned long syndromes[8][8]; + + /* If there are no errors, return. */ + bch_status = READL(chip->IO_ADDR_R + EP501G1_NAND_BCH_STATUS); + + if (0 == bch_status) + goto report_ecc_errors_ep501g1_end; + + switch (mtd->writesize) { + case 512: + bch_status &= 0x1; + break; + case 2048: + bch_status &= 0xf; + break; + case 4096: + bch_status &= 0xff; + break; + default: + printk(KERN_ERR "Unexpected Page Size!\n"); + rc = -1; + goto report_ecc_errors_ep501g1_end; + break; + } + + /* Ignore fully erased blocks. */ + if (NULL != data) { + for (i = 0; i < mtd->writesize; ++i) { + if (0xff != *data++) { + is_blank = 0; + break; + } + } + } + + if (0 != is_blank) + goto report_ecc_errors_ep501g1_end; + + /* Read the syndrome registers and split them into syndromes. */ + for (section = 0; section < 8; ++section) { + unsigned long address; + unsigned long value; + + address = EP501G1_NAND_SYN_R12_S0 + (section * 0x10); + + for (syndrome = 0; syndrome < 8; syndrome += 2) { + value = READL(chip->IO_ADDR_R + address + + (syndrome * 2)); + syndromes[section][syndrome] = + (value & 0x1fff); + syndromes[section][syndrome + 1] = + ((value & 0x1fff0000) >> 16); + } + } + + /* Debug output (BCH status register and syndromes). */ +#if 0 + printk("BCH Status Register: 0x%02lx\n", bch_status); + + for (section = 0; section < 8; ++section) { + printk("Syndromes, Section %d: ", section); + + for (syndrome = 0; syndrome < 8; ++syndrome) { + printk("0x%04lx ", syndromes[section][syndrome]); + } + + printk("\n"); + } +#endif + + for (i = 0; i < 4; ++i) { + if ((1 << i) == (bch_status & (1 << i))) { + rc = fix_section(((page * mtd->writesize) + (512 * i)), + (void *)(buffer + (512 * i)), + (int *)&syndromes[i]); + + if (-1 == rc) + printk(KERN_ERR + "Uncorrectable ECC Error: Page %d\n", + page); + } + } + + report_ecc_errors_ep501g1_end: + + return rc; +} + +/* + ------------------------------------------------------------------------------ + report_ecc_errors_ep501g3 +*/ + +static int +report_ecc_errors_ep501g3(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buffer, int page) +{ + unsigned long bch_status; + int rc = 0; + unsigned long value; + int i; + int is_blank = 1; + uint8_t *data = buffer; + int section; + int syndrome; + unsigned long syndromes[8][8]; + int num_sections; + + num_sections = (mtd->writesize / 512); + + /* Verify 4-bit mode in the EP501G3 case. */ + value = (READL(chip->IO_ADDR_R + EP501_NAND_CONFIG_REG) & 0x1800) >> 11; + + if (1 != value) { + printk("Only 4-Bit ECC is supported.\n"); + rc = -1; + goto report_ecc_errors_ep501g3_end; + } + + /* If there are no errors, return. */ + bch_status = READL(chip->IO_ADDR_R + EP501G1_NAND_BCH_STATUS); + + if (0 == bch_status) + goto report_ecc_errors_ep501g3_end; + + switch (mtd->writesize) { + case 512: + bch_status &= 0x1; + break; + case 2048: + bch_status &= 0xf; + break; + case 4096: + bch_status &= 0xff; + break; + default: + printk(KERN_ERR "Unexpected Page Size!\n"); + rc = -1; + goto report_ecc_errors_ep501g3_end; + break; + } + + /* Ignore fully erased blocks. */ + if (NULL != data) { + for (i = 0; i < mtd->writesize; ++i) { + if (0xff != *data++) { + is_blank = 0; + break; + } + } + } + + if (0 != is_blank) + goto report_ecc_errors_ep501g3_end; + + /* Read the syndrome registers and split them into syndromes. */ + for (section = 0; section < 8; ++section) { + unsigned long address; + unsigned long value; + + address = EP501G1_NAND_SYN_R12_S0 + (section * 0x10); + + for (syndrome = 0; syndrome < ((mtd->writesize / 512) * 2); + syndrome += 2, address += 4) { + value = READL(chip->IO_ADDR_R + address); + syndromes[section][syndrome] = + (value & 0x1fff); + syndromes[section][syndrome + 1] = + ((value & 0x1fff0000) >> 16); + } + } + + /* Debug output (BCH status register and syndromes). */ +#if 0 + printk("BCH Status Register: 0x%02lx\n", bch_status); + + for (section = 0; section < 8; ++section) { + printk("Syndromes, Section %d: ", section); + + for (syndrome = 0; syndrome < 8; ++syndrome) { + printk("0x%04lx ", syndromes[section][syndrome]); + } + + printk("\n"); + } +#endif + + for (i = 0; i < 4; ++i) { + if ((1 << i) == (bch_status & (1 << i))) { + rc = fix_section(((page * mtd->writesize) + (512 * i)), + (void *)(buffer + (512 * i)), + (int *)&syndromes[i]); + + if (-1 == rc) + printk(KERN_ERR + "Uncorrectable ECC Error: Page %d\n", + page); + } + } + + report_ecc_errors_ep501g3_end: + + return rc; +} + +/* + ------------------------------------------------------------------------------ + report_ecc_errors +*/ + +static int +report_ecc_errors(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buffer, int page) +{ + int rc = 0; + + switch (lsi_nand_type) { + case LSI_NAND_EP501: + rc = report_ecc_errors_ep501(mtd, chip, buffer, page); + break; + case LSI_NAND_EP501G1: + rc = report_ecc_errors_ep501g1(mtd, chip, buffer, page); + break; + case LSI_NAND_EP501G3: + rc = report_ecc_errors_ep501g3(mtd, chip, buffer, page); + break; + default: + rc = -1; + break; + } + + return rc; +} + + +/** + * nand_read_page_hwecc - hardware ecc based page read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * + * Not for syndrome calculating ecc controllers which need a special oob layout + */ + +static int +lsi_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + int rc; + /*int page = 0;*/ + + /* Read the current page number and save it. */ + /*page = READL(chip->IO_ADDR_R + NAND_INDEX_REG) >> 12;*/ + + /* read the page */ + chip->read_buf(mtd, buf, mtd->writesize); + + /* read oob data */ + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + /* start ECC calculations */ + chip->ecc.calculate(mtd, NULL, NULL); + + /* Read the ECC Status and see if there were any errors */ + rc = report_ecc_errors(mtd, chip, buf, page); + + /* cmd to controller to turn off CE */ + chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0); + return rc; +} + +/** + * lsi_nand_write_page_hwecc - hardware ecc based page write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + */ +static void +lsi_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + /* write the page data */ + chip->write_buf(mtd, buf, mtd->writesize); + + /* + * Write the oob data. Last 12 bytes are used by HW ECC. + * Do not touch them. + */ + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize - chip->ecc.bytes); + return; +} + +/** + * lsi_nand_write_page - [REPLACEABLE] write one page + * @mtd: MTD device structure + * @chip: NAND chip descriptor + * @buf: the data to write + * @page: page number to write + * @cached: cached programming + * @raw: use _raw version of write_page + */ + +static int +lsi_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int page, int cached, int raw) +{ + int status; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + + if (unlikely(raw)) + chip->ecc.write_page_raw(mtd, chip, buf); + else + chip->ecc.write_page(mtd, chip, buf); + + /* calculate ECC */ + status = chip->ecc.calculate(mtd, NULL, NULL); + + /* cmd to controller to turn off CE */ + chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0); + + /* + * See if operation failed and additional status checks are + * available + */ + if (status & NAND_STATUS_FAIL) { + printk(KERN_ERR "ERROR: Page write failed for page 0x%x\n", + page); + + if (chip->errstat) + status = chip->errstat(mtd, chip, FL_WRITING, status, + page); + + return -EIO; + } + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* Send command to read back the data */ + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + if (chip->verify_buf(mtd, buf, mtd->writesize)) { + return -EIO; + } +#endif + + return 0; +} + + +/** + * lsi_nand_read_oob_std - [REPLACABLE] the most common OOB data read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to read + * @sndcmd: flag whether to issue read command or not + */ + +static int +lsi_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int sndcmd) +{ + int rc; + + /* send command to read oob */ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + + /* read oob data */ + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + /* start ECC calculations */ + chip->ecc.calculate(mtd, NULL, NULL); + + /* Read the ECC Status and see if there were any errors */ + rc = report_ecc_errors(mtd, chip, NULL, page); + + /* cmd to controller to turn off CE */ + chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0); + + return sndcmd; +} + +/** + * lsi_nand_write_oob_std - [REPLACABLE] the most common OOB data write + * function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to write + */ + +static int +lsi_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page) +{ + /* start OOB write */ + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + + /* + * Write the oob data. Last 12 bytes are used by HW ECC. + * Do not touch them. + */ + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize - chip->ecc.bytes); + + /* calculate ECC */ + chip->ecc.calculate(mtd, NULL, NULL); + + /* cmd to controller to turn off CE */ + chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0); + + return (chip->dev_ready(mtd) & NAND_STATUS_FAIL) ? -EIO : 0; +} + +/* + ====================================================================== + ====================================================================== + Public + ====================================================================== + ====================================================================== +*/ + +/* + ------------------------------------------------------------------------------ + lsi_nand_set_config +*/ + +int +lsi_nand_set_config(struct mtd_info *mtd, struct nand_chip *chip) +{ + unsigned long config = 0; + unsigned long mbits; + + mbits = ((chip->chipsize >> 20) * 8); + + if (LSI_NAND_EP501 == lsi_nand_type) { + /* The EP501 only supports 512 and 2k page sizes. */ + if (512 != mtd->writesize && + 2048 != mtd->writesize) + return -1; + + while (64 < mbits) { + ++config; /* 0b000=64Mbit, 0b001=128Mbit, etc. */ + mbits >>= 1; + } + + if (512 < mtd->writesize) + config |= 0x100; /* large block */ + + config |= 0x200; /* not write protected */ + chip->ecc.layout = &lsi_2k_1bit_ecclayout; + chip->ecc.size = mtd->writesize; + chip->ecc.bytes = chip->ecc.layout->eccbytes; + } else if (LSI_NAND_EP501G1 == lsi_nand_type) { + /* The EP501G1 only supports 512, 2k, and 4k page sizes, */ + if (512 != mtd->writesize && + 2048 != mtd->writesize && + 4096 != mtd->writesize) + return -1; + + /* and device sizes as follows. */ + if (512 == mtd->writesize) { + switch (mbits) { + case 64: break; + case 128: config |= 1; break; + case 256: config |= 2; break; + case 512: config |= 3; break; + case 1024: config |= 4; break; + case 2048: config |= 5; break; + case 4096: config |= 6; break; + case 8192: config |= 7; break; + default: + return -1; + break; + } + } else { + switch (mbits) { + case 512: config |= 3; break; + case 1024: config |= 4; break; + case 2048: config |= 5; break; + case 4096: config |= 6; break; + case 8192: config |= 7; break; + case 16384: break; + case 32768: config |= 1; break; + case 65536: config |= 2; break; + default: + return -1; + break; + } + } + + switch (mtd->writesize) { + case 512: + break; + case 2048: + config |= 0x1 << 8; + chip->ecc.layout = &lsi_2k_4bit_ecclayout; + break; + case 4096: + config |= 0x2 << 8; + chip->ecc.layout = &lsi_4k_4bit_ecclayout; + break; + default: + return -1; + break; + } + + config |= 1 << 10; /* not write protected */ + + config |= 1 << 11; /* 4 bit ECC */ + + if (512 < mtd->writesize) + config |= 1 << 12; /* 3 cycle row address */ + + chip->ecc.size = mtd->writesize; + + if (mtd->oobsize == 224) { + chip->ecc.bytes = 224 - chip->ecc.layout->eccbytes; + } else { + chip->ecc.bytes = chip->ecc.layout->eccbytes; + } + } else if (LSI_NAND_EP501G3 == lsi_nand_type) { + /* The EP501G3 only supports 2k, 4k, and 8k page sizes, */ + if (2048 != mtd->writesize && + 4096 != mtd->writesize && + 8192 != mtd->writesize) + return -1; + + /* and device sizes as follows. */ + switch (mbits) { + case 512: config |= 3; break; + case 1024: config |= 4; break; + case 2048: config |= 5; break; + case 4096: config |= 6; break; + case 8192: config |= 7; break; + case 16384: break; + case 32768: config |= 1; break; + case 65536: config |= 2; break; + default: + printk("Invalid Device Size: 0x%lx\n", mbits); + return -1; + break; + } + + switch (mtd->writesize) { + case 2048: + config |= 0x1 << 8; + chip->ecc.layout = &lsi_2k_4bit_ecclayout; + break; + case 4096: + config |= 0x2 << 8; + chip->ecc.layout = &lsi_4k_4bit_ecclayout; + break; + case 8192: + config |= 0x3 << 8; + chip->ecc.layout = &lsi_8k_4bit_ecclayout; + break; + default: + return -1; + break; + } + + config |= 1 << 10; /* not write protected */ + config |= 1 << 13; /* 3 cycle row address */ + + /* + 2K/4bit - 32 bytes (8192) + 2K/8bit - 64 bytes (16384) + 2K/12bit - 80 bytes (24576) + ... + 8K/12bit - 320 bytes (98304) + */ + + if (mtd->oobsize < chip->ecc.layout->eccbytes) { + printk(KERN_ERR + "ECC requires %d bytes, only %d are available.\n", + chip->ecc.layout->eccbytes, mtd->oobsize); + return -1; + } + + config |= 1 << 11; /* 4 bit ECC */ + mtd->oobavail = mtd->oobsize - chip->ecc.layout->eccbytes; + mtd->oobavail -= (mtd->oobavail % 4); + config |= (chip->ecc.layout->eccbytes / 4) << 16; + chip->ecc.size = mtd->writesize; + chip->ecc.bytes = chip->ecc.layout->eccbytes; + } else { + return -1; + } + + printk("%s:%d - write/erase/oob=0x%x/0x%x/0x%x config=0x%x\n", + __FILE__, __LINE__, + mtd->writesize, mtd->erasesize, mtd->oobsize, config); /* ZZZ */ + WRITEL(config, chip->IO_ADDR_W + EP501_NAND_CONFIG_REG); + + return 0; +} + +/* + ---------------------------------------------------------------------- + lsi_nand_init +*/ + +#define NAND_BASE 0x002000440000ULL +#define NAND_SIZE 0x20000 +#define GPREG_BASE 0x002000400000ULL +#define GPREG_SIZE 0x1000 + +static int __init +lsi_nand_init(void) +{ + unsigned long nand_base; + struct device_node *np = NULL; + int ret; + + np = of_find_node_by_type(np, "nand"); + + while (np && !of_device_is_compatible(np, "acp-nand")) + np = of_find_node_by_type(np, "nand"); + + if (np) { + const u32 *reg; + int reglen; + u64 nand_address; + unsigned long nand_length; + u64 gpreg_address; + unsigned long gpreg_length; + int *enabled; + + enabled = of_get_property(np, "enabled", NULL); + + if (0 == *enabled) { + printk("ACP NAND Controller Isn't Enabled.\n"); + return -1; + } + + reg = of_get_property(np, "reg", ®len); + + if (reg && (16 == reglen)) { + nand_address = of_translate_address(np, reg); + nand_length = reg[1]; + reg += 2; + gpreg_address = of_translate_address(np, reg); + gpreg_length = reg[1]; + printk("nand_address=0x%08llx nand_length=0x%lx\n" + "gpreg_address=0x%08llx gpreg_length=0x%lx\n", + nand_address, nand_length, + gpreg_address, gpreg_length); + nand_base = (unsigned long) + ioremap(nand_address, nand_length); + gpreg_base = (unsigned long) + ioremap(gpreg_address, gpreg_length); + } else { + return -1; + } + } else { + printk("ACP NAND: Using Static Addresses.\n"); + nand_base = ioremap(0x002000440000ULL, 0x20000); + gpreg_base = ioremap(0x00200040c000ULL, 0x1000); + } + + /* + Determine the version of the controller. + + As there is not version register, see if bits 5:3 of the + configuration register are writable. There are in the EP501 + case and aren't in the EP501G1 case. + */ + + { + unsigned long cr; + unsigned long cr_save; + + cr = cr_save = READL((void *)(nand_base + NAND_CONFIG_REG)); + cr = 0x2038; + WRITEL(cr, (void *)(nand_base + EP501_NAND_CONFIG_REG)); + cr = READL((void *)nand_base + EP501_NAND_CONFIG_REG); + WRITEL(cr_save, (void *)(nand_base + EP501_NAND_CONFIG_REG)); + + if (0 == (cr & 0x2038)) { + lsi_nand_type = LSI_NAND_EP501G1; + } else if (0x38 == (cr & 0x2038)) { + lsi_nand_type = LSI_NAND_EP501; + } else if (0x2000 == (cr & 0x2038)) { + lsi_nand_type = LSI_NAND_EP501G3; + } else { + lsi_nand_type = LSI_NAND_NONE; + } + } + + switch (lsi_nand_type) { + case LSI_NAND_EP501: + printk("EP501 NAND Controller.\n"); + nand_cmd_ce_off = NAND_CMD_CE_OFF_501; + break; + case LSI_NAND_EP501G1: + printk("EP501G1 NAND Controller.\n"); + nand_cmd_ce_off = NAND_CMD_CE_OFF_501G1; + break; + case LSI_NAND_EP501G3: + printk("EP501G3 NAND Controller.\n"); + nand_cmd_ce_off = NAND_CMD_CE_OFF_501G3; + break; + default: + printk("Unknown NAND Controller!\n"); + return -1; + break; + } + + /* Initialize structures */ + memset(&lsi_nand_mtd, 0, sizeof(struct mtd_info)); + memset(&lsi_nand_chip, 0, sizeof(struct nand_chip)); + + /* Link the private data with the MTD structure */ + lsi_nand_mtd.priv = &lsi_nand_chip; + lsi_nand_mtd.owner = THIS_MODULE; + lsi_nand_mtd.name = "acp-nand"; + + /* init chip callbacks */ + lsi_nand_chip.IO_ADDR_R = (void *) nand_base; + lsi_nand_chip.IO_ADDR_W = (void *) nand_base; + lsi_nand_chip.write_buf = lsi_nand_write_buf; + lsi_nand_chip.read_buf = lsi_nand_read_buf; + lsi_nand_chip.verify_buf = lsi_nand_verify_buf; + lsi_nand_chip.write_page = lsi_nand_write_page; + lsi_nand_chip.cmd_ctrl = lsi_nand_hwcontrol; + lsi_nand_chip.dev_ready = lsi_nand_device_ready; + lsi_nand_chip.cmdfunc = lsi_nand_command; + lsi_nand_chip.waitfunc = lsi_nand_wait; + lsi_nand_chip.chip_delay = 10; + lsi_nand_chip.options = NAND_USE_FLASH_BBT; + + /* initialize ECC */ + lsi_nand_chip.ecc.mode = NAND_ECC_HW; + lsi_nand_chip.ecc.steps = 1; + lsi_nand_chip.ecc.total = 12; + lsi_nand_chip.ecc.hwctl = lsi_nand_ecc_hwctl; + lsi_nand_chip.ecc.calculate = lsi_nand_ecc_calculate; + lsi_nand_chip.ecc.correct = lsi_nand_ecc_correct; + lsi_nand_chip.ecc.read_page = lsi_nand_read_page_hwecc; + lsi_nand_chip.ecc.write_page = lsi_nand_write_page_hwecc; + lsi_nand_chip.ecc.read_page_raw = lsi_nand_read_page_hwecc; + lsi_nand_chip.ecc.write_page_raw = lsi_nand_write_page_hwecc; + lsi_nand_chip.ecc.read_oob = lsi_nand_read_oob; + lsi_nand_chip.ecc.write_oob = lsi_nand_write_oob; + + printk(KERN_ERR "Enabling NAND ECC...\n"); + /* clear any existing ECC status */ + WRITEL(0x0, lsi_nand_chip.IO_ADDR_W + NAND_INTR_STATUS_REG); + /* enable ECC */ + WRITEL(0x0, lsi_nand_chip.IO_ADDR_W + NAND_INTR_EN_REG); + + /* + ====================================================================== + Timing Control + + This may need to be changed, based on the devices used. Each field is + described below. + */ + + /* + TCR0 - NAND Timing Control Register 0 + */ + + { + nand_timing_control_register_0_t tcr0; + + /* TH [31:24] - CLE, CE & ALE hold Time */ + tcr0.bits.th = 0x08; + + /* TRP [23:16] - Read Pulse Width */ + tcr0.bits.trp = 0x0c; + + /* TWP [15:8] - Write Pulse Width */ + tcr0.bits.twp = 0x0c; + + /* TS [7:0] - Setup Time for CLE, CE & ALE */ + tcr0.bits.ts = 0x05; + + WRITEL(tcr0.raw, + (lsi_nand_chip.IO_ADDR_W + NAND_TIMING1_REG)); + } + + /* + TCR1 - NAND Timing Control Register 1 + */ + + { + nand_timing_control_register_1_t tcr1; + + /* TWB [31:24] - WE Rising Edge to RY/BY Falling Edge */ + tcr1.bits.twb = 0x1e; + + /* TRR [23:16] - RY/BY Rising Edge To Read Falling Edge */ + tcr1.bits.trr = 0x07; + + /* TRH [15:8] - Read Pulse High Time */ + tcr1.bits.trh = 0x03; + + /* TWH [7:0] - Write Pulse High Time */ + tcr1.bits.twh = 0x03; + + WRITEL(tcr1.raw, + (lsi_nand_chip.IO_ADDR_W + NAND_TIMING2_REG)); + } + + /* + TCR2 - NAND Timing Control Register 2 (EP501G3 Only) + */ + + { + nand_timing_control_register_2_t tcr2; + + tcr2.bits.tccs = 0x10; + tcr2.bits.twhr = 0x10; + tcr2.bits.trhw = 0x14; + WRITEL(tcr2.raw, + (lsi_nand_chip.IO_ADDR_W + EP501G3_NAND_TIMING2_REG)); + } + + printk(KERN_ERR "Searching for NAND flash...\n"); + /* Scan to find existence of the device */ + if (nand_scan(&lsi_nand_mtd, 1)) { + printk(KERN_ERR "nand_scan failure...\n"); + return -ENXIO; + } + + ret = parse_mtd_partitions(&lsi_nand_mtd, probes, + &partition_info, 0); + if (ret > 0) + mtd_device_register(&lsi_nand_mtd, partition_info, ret); + else + mtd_device_register(&lsi_nand_mtd, NULL, 0); + + /* Return happy */ + return 0; +} + +module_init(lsi_nand_init); + +/* + ---------------------------------------------------------------------- + lsi_nand_exit +*/ + +static void __exit +lsi_nand_exit(void) +{ + /* Release resources, unregister device */ + nand_release(&lsi_nand_mtd); +} + +module_exit(lsi_nand_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Jay Jayatheerthan "); +MODULE_DESCRIPTION("MTD map driver for LSI's ACP board"); diff --git a/drivers/lsi/acp/ncr.c b/drivers/lsi/acp/ncr.c new file mode 100644 index 0000000..595e3f4 --- /dev/null +++ b/drivers/lsi/acp/ncr.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2009 LSI Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include "ncr.h" + +#define NCA 0xf0120000 + +typedef union { + unsigned long raw; + struct { + unsigned long start_done:1; + unsigned long unused:6; + unsigned long local_bit:1; + unsigned long status:2; + unsigned long byte_swap_enable:1; + unsigned long cfg_cmpl_int_enable:1; + unsigned long cmd_type:4; + unsigned long dbs:16; + } __attribute__ ((packed)) bits; +} __attribute__ ((packed)) command_data_register_0_t; + +typedef union { + unsigned long raw; + struct { + unsigned long target_address:32; + } __attribute__ ((packed)) bits; +} __attribute__ ((packed)) command_data_register_1_t; + +typedef union { + unsigned long raw; + struct { + unsigned long unused:16; + unsigned long target_node_id:8; + unsigned long target_id_address_upper:8; + } __attribute__ ((packed)) bits; +} __attribute__ ((packed)) command_data_register_2_t; + +/* + ---------------------------------------------------------------------- + ncr_register_read +*/ + +static __inline__ unsigned long +ncr_register_read(unsigned *address) +{ + unsigned long value; + + value = in_be32((unsigned long) address); + + return value; +} + +/* + ---------------------------------------------------------------------- + ncr_register_write +*/ + +static __inline__ void +ncr_register_write(const unsigned value, unsigned *address) +{ + out_be32(address, value); +} + +/* + ====================================================================== + ====================================================================== + Public Interface + ====================================================================== + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + ncr_read +*/ + +int +ncr_read(unsigned long region, unsigned long address, int number, + void *buffer) +{ + command_data_register_0_t cdr0; + command_data_register_1_t cdr1; + command_data_register_2_t cdr2; + + /* + Set up the read command. + */ + + cdr2.raw = 0; + cdr2.bits.target_node_id = NCP_NODE_ID(region); + cdr2.bits.target_id_address_upper = NCP_TARGET_ID(region); + ncr_register_write(cdr2.raw, (unsigned *) (NCA + 0xf8)); + + cdr1.raw = 0; + cdr1.bits.target_address = (address >> 2); + ncr_register_write(cdr1.raw, (unsigned *) (NCA + 0xf4)); + + cdr0.raw = 0; + cdr0.bits.start_done = 1; + + if (0xff == cdr2.bits.target_id_address_upper) + cdr0.bits.local_bit = 1; + + cdr0.bits.cmd_type = 4; + /* TODO: Verify number... */ + cdr0.bits.dbs = (number - 1); + ncr_register_write(cdr0.raw, (unsigned *) (NCA + 0xf0)); + mb(); + + /* + Wait for completion. + */ + + /* TODO: Handle failure cases. */ +#if 0 + while (0x80000000 == + (ncr_register_read((unsigned *) (NCA + 0xf0)) & 0x80000000)) + ; +#else + { + volatile unsigned long value; + + do { + value = ncr_register_read((unsigned *) (NCA + 0xf0)); + } while (0x80000000 == (value & 0x80000000)); + } +#endif + + /* + Copy data words to the buffer. + */ + + address = (NCA + 0x1000); + while (4 <= number) { + *((unsigned long *) buffer) = + ncr_register_read((unsigned *) address); + address += 4; + number -= 4; + } + + if (0 < number) { + unsigned long temp = + ncr_register_read((unsigned *) address); + memcpy((void *) buffer, &temp, number); + } + + return 0; +} + +/* + ---------------------------------------------------------------------- + ncr_write +*/ + +int +ncr_write(unsigned long region, unsigned long address, int number, + void *buffer) +{ + command_data_register_0_t cdr0; + command_data_register_1_t cdr1; + command_data_register_2_t cdr2; + unsigned long data_word_base; + int dbs = (number - 1); + + /* + Set up the write. + */ + + cdr2.raw = 0; + cdr2.bits.target_node_id = NCP_NODE_ID(region); + cdr2.bits.target_id_address_upper = NCP_TARGET_ID(region); + ncr_register_write(cdr2.raw, (unsigned *) (NCA + 0xf8)); + + cdr1.raw = 0; + cdr1.bits.target_address = (address >> 2); + ncr_register_write(cdr1.raw, (unsigned *) (NCA + 0xf4)); + + /* + Copy from buffer to the data words. + */ + + data_word_base = (NCA + 0x1000); + + while (4 <= number) { + ncr_register_write(*((unsigned long *) buffer), + (unsigned *) data_word_base); + data_word_base += 4; + buffer += 4; + number -= 4; + } + + if (0 < number) { + unsigned long temp = 0; + + memcpy((void *) &temp, (void *) buffer, number); + ncr_register_write(temp, (unsigned *) data_word_base); + data_word_base += number; + buffer += number; + number = 0; + } + + cdr0.raw = 0; + cdr0.bits.start_done = 1; + + if (0xff == cdr2.bits.target_id_address_upper) { + cdr0.bits.local_bit = 1; + } + + cdr0.bits.cmd_type = 5; + /* TODO: Verify number... */ + cdr0.bits.dbs = dbs; + ncr_register_write(cdr0.raw, (unsigned *) (NCA + 0xf0)); + mb(); + + /* + Wait for completion. + */ + + /* TODO: Handle failure cases. */ + while (0x80000000 == + (ncr_register_read((unsigned *) (NCA + 0xf0)) & 0x80000000)) + ; + + return 0; +} + +/* + ---------------------------------------------------------------------- + ncr_init +*/ + +int +ncr_init( void ) +{ + /* We need this to be a module so that the functions can be exported + * as module symbols. + */ + return 0; +} + +module_init( ncr_init ); + +/* + ---------------------------------------------------------------------- + ncr_exit +*/ + +void __exit +ncr_exit( void ) +{ +} + +module_exit( ncr_exit ); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Register Ring access for LSI's ACP board"); + +EXPORT_SYMBOL(ncr_read); +EXPORT_SYMBOL(ncr_write); diff --git a/drivers/lsi/acp/ncr.h b/drivers/lsi/acp/ncr.h new file mode 100644 index 0000000..f102df5 --- /dev/null +++ b/drivers/lsi/acp/ncr.h @@ -0,0 +1,40 @@ +/* + * drivers/lsi/common/version.h + * + * Copyright (C) 2010 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __DRIVERS_LSI_ACP_NCR_H +#define __DRIVERS_LSI_ACP_NCR_H + +#ifndef NCP_REGION_ID +#define NCP_REGION_ID(node, target) \ +(unsigned long) ((((node) & 0xffff) << 16) | ((target) & 0xffff)) +#endif + +#ifndef NCP_NODE_ID +#define NCP_NODE_ID(region) (((region) >> 16) & 0xffff) +#endif + +#ifndef NCP_TARGET_ID +#define NCP_TARGET_ID(region) ((region) & 0xffff) +#endif + +int ncr_read(unsigned long, unsigned long, int, void *); +int ncr_write(unsigned long, unsigned long, int, void *); + +#endif /* __DRIVERS_LSI_ACP_NCR_H */ diff --git a/drivers/lsi/acp/net.c b/drivers/lsi/acp/net.c new file mode 100644 index 0000000..c96a4dd --- /dev/null +++ b/drivers/lsi/acp/net.c @@ -0,0 +1,4534 @@ +/* + * drivers/lsi/acp/net.c + * + * Copyright (C) 2009 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../common/version.h" + +extern int acp_mdio_read(unsigned long, unsigned long, unsigned short *); +extern int acp_mdio_write(unsigned long, unsigned long, unsigned short); + +/* Base Addresses of the RX, TX, and DMA Registers. */ +static unsigned long rx_base; +static unsigned long tx_base; +static unsigned long dma_base; + +/* + =============================================================================== + Debug counts (readable from the external host). + =============================================================================== +*/ + +#undef LSINET_COUNTS +#define LSINET_COUNTS + +#ifdef LSINET_COUNTS + +unsigned long lsinet_counts [ ] = { + 0, 0, 0, 0, /* ISR */ + 0, 0, 0, 0, 0, 0, /* HST */ + 0, 0, 0, 0, 0, 0, 0, /* RX */ + 0, 0, 0, 0 /* POL */ +}; + +EXPORT_SYMBOL( lsinet_counts ); + +#define LSINET_COUNTS_INC( index ) { ++ lsinet_counts [ ( index ) ]; } + +#else /* LSINET_DEBUG_COUNTS */ + +#define LSINET_COUNTS_INC( index ) + +#endif /* LSINET_DEBUG_COUNTS */ + +#define LSINET_COUNTS_ISR_START 0 +#define LSINET_COUNTS_ISR_TX 1 +#define LSINET_COUNTS_ISR_RX 2 +#define LSINET_COUNTS_ISR_DONE 3 +#define LSINET_COUNTS_HST_START 4 +#define LSINET_COUNTS_HST_RCLM 5 +#define LSINET_COUNTS_HST_SNDG 6 +#define LSINET_COUNTS_HST_SNT 7 +#define LSINET_COUNTS_HST_OOD 8 +#define LSINET_COUNTS_HST_DONE 9 +#define LSINET_COUNTS_RX_START 10 +#define LSINET_COUNTS_RX_PKT 11 +#define LSINET_COUNTS_RX_ERR 12 +#define LSINET_COUNTS_RX_GOOD 13 +#define LSINET_COUNTS_RX_SENT 14 +#define LSINET_COUNTS_RX_DRPD 15 +#define LSINET_COUNTS_RX_DONE 16 +#define LSINET_COUNTS_POL_START 17 +#define LSINET_COUNTS_POL_PKT 18 +#define LSINET_COUNTS_POL_RNBL 19 +#define LSINET_COUNTS_POL_DONE 20 + +/* + ====================================================================== + ====================================================================== + ====================================================================== + Profile/Trace/Debug/Warn/Error Macros + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +/* -- Profile ------------------------------------------------------- */ + +/*#define __APPNIC_C_PROFILE__*/ +#ifdef __APPNIC_C_PROFILE__ +#include +unsigned long time_in_rx_max_ = 0; +unsigned long time_in_rx_min_ = 0xffffffff; +unsigned long long total_rx_time_ = 0; +unsigned long max_rx_packets_handled_ = 0; +unsigned long total_rx_packets_handled_ = 0; +unsigned long total_rx_interrupts_ = 0; +unsigned long rx_packet_size_max_ = 0; +unsigned long rx_packet_size_min_ = 0xffffffff; +unsigned long total_rx_bytes_ = 0; +unsigned long time_in_tx_max_ = 0; +unsigned long time_in_tx_min_ = 0xffffffff; +unsigned long long total_tx_time_ = 0; +unsigned long total_tx_packets_ = 1; +unsigned long jiffies_changed_ = 0; +unsigned long total_polls_ = 0; + +unsigned long recv_t1_min_ = 0xffffffff; +unsigned long recv_t2_min_ = 0xffffffff; +unsigned long recv_t3_min_ = 0xffffffff; +unsigned long recv_t1_max_ = 0; +unsigned long recv_t2_max_ = 0; +unsigned long recv_t3_max_ = 0; +unsigned long long recv_t1_tot_ = 0; +unsigned long long recv_t2_tot_ = 0; +unsigned long long recv_t3_tot_ = 0; +unsigned long total_rx_packets_sent_up_ = 1; + + +#define app3xx_profile_time_calc(_beg_t_, _end_t_, _min_t_, _max_t_, _tot_t_) \ + do { \ + unsigned long _this_t_; \ + if( _end_t_ > _beg_t_ ) { \ + _this_t_ = _end_t_ - _beg_t_; \ + } else { \ + _this_t_ = _end_t_ + ( 0xffffffff - _beg_t_ ) + 1; \ + } \ + _tot_t_ += _this_t_; \ + if( _this_t_ > _max_t_ ) { _max_t_ = _this_t_; } \ + if( _this_t_ < _min_t_ ) { _min_t_ = _this_t_; } \ + } while (0) ; + +#define profile_time_fmt(t,d) ((1000*t)/d) +#define profile_avg_fmt(t,c,d) ((1000*(t/c))/d) +#endif /* __APPNIC_C_PROFILE__ */ + +/* -- TRACE --------------------------------------------------------- */ + +#undef TRACE +/*#define TRACE*/ +#define TRACE_PRINTK +#ifdef TRACE +#ifdef TRACE_PRINTK +#define TRACE_BEGINNING( ) \ +printk( "nic:%d:%s:Beginning\n", smp_processor_id( ), __FUNCTION__ ) +#define TRACE_ENDING( ) \ +printk( "nic:%d:%s:Ending\n", smp_processor_id( ), __FUNCTION__ ) +#else +#define TRACE_BEGINNING( ) TRACER_POST( "Beginning" ); +#define TRACE_ENDING( ) TRACER_POST( "Ending" ); +#endif +#else +#define TRACE_BEGINNING( format, args... ) +#define TRACE_ENDING( format, args... ) +#endif + +/* -- DEBUG --------------------------------------------------------- */ + +#undef DEBUG +/*#define DEBUG*/ +#if defined( DEBUG ) +#define DEBUG_PRINT( format, args... ) do { \ +printk( "appnic:%d - DEBUG - ", __LINE__ ); \ +printk( format, ##args ); \ +} while( 0 ); +#else +#define DEBUG_PRINT( format, args... ) +#endif + +#undef PHY_DEBUG +/*#define PHY_DEBUG*/ +#if defined( PHY_DEBUG ) +#define PHY_DEBUG_PRINT( format, args... ) do { \ +printk( "net:%d - PHY_DEBUG - ", __LINE__ ); \ +printk( format, ##args ); \ +} while( 0 ); +#else +#define PHY_DEBUG_PRINT( format, args... ) +#endif + +/* -- WARN ----------------------------------------------------------- */ + +#undef WARN +#define WARN +#if defined( WARN ) +#define WARN_PRINT( format, args... ) do { \ +printk( "appnic:%d - WARN - ", __LINE__ ); \ +printk( format, ##args ); \ +} while( 0 ); +#else +#define WARN_PRINT( format, args... ) +#endif + +/* -- ERROR --------------------------------------------------------- */ + +#define ERROR_PRINT( format, args... ) do { \ +printk( "%s:%s:%d - ERROR - ", __FILE__, __FUNCTION__, __LINE__ ); \ +printk( format, ##args ); \ +} while( 0 ); + +/* + ====================================================================== + ====================================================================== + Optimizations + ====================================================================== + ====================================================================== +*/ + +#define DISABLE_TX_INTERRUPTS +/*#define PRELOAD_RX_BUFFERS*/ + +#undef DMA_CACHABLE +/*#define DMA_CACHABLE*/ + +/* + =============================================================================== + NAPI Support (new and newer)... + =============================================================================== +*/ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) + +#define LSINET_NAPI +#define LSINET_NAPI_WEIGHT 64 + +#endif + +/* + ====================================================================== + ====================================================================== + ====================================================================== + Access and Access Logging + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +/*#define LOG_MAC_ACCESS*/ +/*#define LOG_PHY_ACCESS*/ + +/* + ====================================================================== + ====================================================================== + ====================================================================== + PHY + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +#undef PHYLESS +/*#define PHYLESS*/ + +#ifndef PHYLESS + +/* -- control -- */ + +#define PHY_CONTROL 0x00 + +typedef union { + unsigned short raw; + + struct { +#if 1 + unsigned short soft_reset : 1; + unsigned short loop_back : 1; + unsigned short force100 : 1; /* speedBit0 */ + unsigned short autoneg_enable : 1; + unsigned short power_down : 1; + unsigned short isolate : 1; + unsigned short restart_autoneg : 1; + unsigned short full_duplex : 1; /* duplex */ + unsigned short collision_test : 1; + unsigned short unused : 7; +#else /* __BIG_ENDIAN */ + unsigned short : 7; + unsigned short collision_test : 1; + unsigned short full_duplex : 1; /* duplex */ + unsigned short restart_autoneg : 1; + unsigned short isolate : 1; + unsigned short power_down : 1; + unsigned short autoneg_enable : 1; + unsigned short force100 : 1; /* speedBit0 */ + unsigned short loop_back : 1; + unsigned short soft_reset : 1; +#endif /* __BIG_ENDIAN */ + } __attribute__ ( ( packed ) ) bits; +} __attribute__ ( ( packed ) ) phy_control_t; + +/* -- status -- */ + +#define PHY_STATUS 0x01 + +typedef union { + unsigned short raw; + + struct { +#if 1 + unsigned short t4_capable : 1; + unsigned short tx_fdx_capable : 1; + unsigned short tx_capable : 1; + unsigned short bt_fdx_capable : 1; + unsigned short tenbt_capable : 1; + unsigned short unused : 4; + unsigned short mf_pream_suppress : 1; + unsigned short autoneg_comp : 1; /* autoNegDone */ + unsigned short remote_fault : 1; /* remoutFault */ + unsigned short autoneg_capable : 1; + unsigned short link_status : 1; /* linkStatus */ + unsigned short jabber_detect : 1; + unsigned short extd_reg_capable : 1; +#else + unsigned short extd_reg_capable : 1; + unsigned short jabber_detect : 1; + unsigned short link_status : 1; /* linkStatus */ + unsigned short autoneg_capable : 1; + unsigned short remote_fault : 1; /* remoutFault */ + unsigned short autoneg_comp : 1; /* autoNegDone */ + unsigned short mf_pream_suppress : 1; + unsigned short : 4; + unsigned short tenbt_capable : 1; + unsigned short bt_fdx_capable : 1; + unsigned short tx_capable : 1; + unsigned short tx_fdx_capable : 1; + unsigned short t4_capable : 1; +#endif /* __BIG_ENDIAN */ + } __attribute__ ( ( packed ) ) bits; +} __attribute__ ( ( packed ) ) phy_status_t; + +/* -- id_high -- */ + +#define PHY_ID_HIGH 0x02 + +typedef union { + unsigned short raw; + + struct { + unsigned short id : 16; + } __attribute__ ( ( packed ) ) bits; +} __attribute__ ( ( packed ) ) phy_id_high_t; + +/* -- id_low -- */ + +#define PHY_ID_LOW 0x03 + +typedef union { + unsigned short raw; + + struct { +#if 1 + unsigned short id : 6; + unsigned short model : 6; + unsigned short revision : 4; +#else /* __BIG_ENDIAN */ + unsigned short revision : 4; + unsigned short model : 6; + unsigned short id : 6; +#endif /* __BIG_ENDIAN */ + } __attribute__ ( ( packed ) ) bits; +} __attribute__ ( ( packed ) ) phy_id_low_t; + +/* -- autoneg_advertise -- */ + +#define PHY_AUTONEG_ADVERTISE 0x04 + +/* -- link_partner_ability -- */ + +#define PHY_LINK_PARTNER_ABILITY 0x05 + +/* -- -- */ + +#define MICREL_PHY_AUXILIARY_CONTROL_STATUS 0x1f + +typedef union { + unsigned short raw; + + struct { + unsigned short : 3; + unsigned short energy : 1; + unsigned short force_link : 1; + unsigned short power_saving : 1; + unsigned short interrupt_level : 1; + unsigned short jabber_enable : 1; + unsigned short autoneg_indication : 1; + unsigned short enable_pause : 1; + unsigned short isolate : 1; + unsigned short op_mode_indication : 3; + unsigned short : 2; + } bits; +} micrel_phy_auxiliary_control_status_t; + +/* + Auto-negotiation Advertisement Values. +*/ + +#define PHY_AUTONEG_ADVERTISE_100FULL 0x101 +#define PHY_AUTONEG_ADVERTISE_100 0x081 +#define PHY_AUTONEG_ADVERTISE_10FULL 0x041 +#define PHY_AUTONEG_ADVERTISE_10 0x021 + +#define PHY_ADDRESS_ 0x1e +static int phy_address_ = PHY_ADDRESS_; + +#define UNKNOWN_PHY_ 0x0 +#define BCM5221_PHY_ 0x1 +#define MICREL_PHY_ 0x2 + +static int phy_type_ = UNKNOWN_PHY_; + +static int phy_read_( int, int, unsigned short * ); +static int phy_write_( int, int, unsigned short ); +static int phy_link_( int ); +static int phy_speed_( int ); +static int phy_duplex_( int ); +static int phy_scan_( void ); +static int phy_reset_( int ); +static int phy_renegotiate_( int ); +static int phy_enable_( int ); + +#endif /* PHYLESS */ + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + NIC Interface + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +static int enable_( struct net_device * ); + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Device Data Structures + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +typedef struct { + +#ifdef CONFIG_ACP + + /* Word 0 */ + unsigned long : 24; + /* big endian to little endian */ + unsigned long byte_swapping_on : 1; + unsigned long error : 1; + unsigned long interrupt_on_completion : 1; + unsigned long end_of_packet : 1; + unsigned long start_of_packet : 1; + unsigned long write : 1; + /* 00=Fill|01=Block|10=Scatter */ + unsigned long transfer_type : 2; + + /* Word 1 */ + unsigned long pdu_length : 16; + unsigned long data_transfer_length : 16; + + /* Word 2 */ + unsigned long target_memory_address; + + /* Word 3 */ + unsigned long host_data_memory_pointer; + +#else + + /* Word 0 */ + /* 00=Fill|01=Block|10=Scatter */ + unsigned long transfer_type : 2; + unsigned long write : 1; + unsigned long start_of_packet : 1; + unsigned long end_of_packet : 1; + unsigned long interrupt_on_completion : 1; + unsigned long error : 1; + /* big endian to little endian */ + unsigned long byte_swapping_on : 1; + unsigned long : 24; + + /* Word 1 */ + unsigned long data_transfer_length : 16; + unsigned long pdu_length : 16; + + /* Word 2 */ + unsigned long target_memory_address; + + /* Word 3 */ + unsigned long host_data_memory_pointer; + +#endif + +} __attribute__ ( ( packed ) ) appnic_dma_descriptor_t; + +typedef union { + + unsigned long raw; + + struct { +#ifdef CONFIG_ACP + unsigned long : 11; + unsigned long generation_bit : 1; + unsigned long offset : 20; +#else + unsigned long offset : 20; + unsigned long generation_bit : 1; + unsigned long : 11; +#endif + } __attribute__ ( ( packed ) ) bits; + +} __attribute__ ( ( packed ) ) appnic_queue_pointer_t; + +/* + =============================================================================== + The Device Struction + =============================================================================== +*/ + +typedef struct { + + /* net_device */ + struct net_device * device; + + /* Addresses, Interrupt, and PHY stuff. */ + unsigned long rx_base; + unsigned long tx_base; + unsigned long dma_base; + unsigned long interrupt; + unsigned long mdio_clock; + unsigned long phy_address; + unsigned long ad_value; + unsigned char mac_addr[6]; + +#ifdef LSINET_NAPI + /* napi */ + struct napi_struct napi; +#endif /* LSINET_ENABLE_NAPI */ + + /* statistics */ + struct net_device_stats stats; + + /* + DMA-able memory. + */ + + /* */ + int dma_alloc_size; + void * dma_alloc; + dma_addr_t dma_alloc_dma; + int dma_alloc_offset; + + /* tail pointers */ + volatile appnic_queue_pointer_t * rx_tail; + dma_addr_t rx_tail_dma; + volatile appnic_queue_pointer_t * tx_tail; + dma_addr_t tx_tail_dma; + + /* descriptors */ + appnic_dma_descriptor_t * rx_desc; + dma_addr_t rx_desc_dma; + unsigned rx_num_desc; + appnic_dma_descriptor_t * tx_desc; + dma_addr_t tx_desc_dma; + unsigned tx_num_desc; + + /* buffers */ + unsigned rx_buf_sz; + unsigned rx_buf_per_desc; + void * rx_buf; + dma_addr_t rx_buf_dma; + unsigned tx_buf_sz; + unsigned tx_buf_per_desc; + void * tx_buf; + dma_addr_t tx_buf_dma; + + /* + The local pointers + */ + + appnic_queue_pointer_t rx_tail_copy; + appnic_queue_pointer_t rx_head; + + appnic_queue_pointer_t tx_tail_copy; + appnic_queue_pointer_t tx_head; + + /* + Polling Mode? + */ + + int polling; + + /* + Spin Lock + */ + + spinlock_t lock; + spinlock_t extra_lock; + + /* + * TEMP: semaphores for locking Tx/Rx operations + */ + + struct semaphore tx_sem; + struct semaphore rx_sem; + struct semaphore poll_sem; + +} appnic_device_t; + +#define DESCRIPTOR_GRANULARITY 64 +#define BUFFER_ALIGNMENT 64 + +#define ALIGN64B( address ) \ +( ( ( ( unsigned long ) ( address ) + ( 64UL - 1UL ) ) & ~ ( 64UL - 1UL ) ) ) + +#define ALIGN64B_OFFSET( address ) \ +( ALIGN64B( address ) - ( unsigned long ) ( address ) ) + +#define APPNIC_NAME "appnic" + +/* + Overview + -------- + + Register offset decoding is as follows: + + Bit(s) Description + + 16:15 define the Channel. There is only one; therefore, 00. + 14:12 define the MAC within the channel. Only one so 000. + 11:10 define the register "space" as follows: + 00 = fast ethernet MAC + 10 = global + 11 = interrupt + 9: 2 register + 1: 0 always 00, 32 bit registers only. + + Receive registers start at the base address. Transmit registers start + at 0x20000 above the base address. DMA start at a completely different + base address (in this case 0x8000000 above the base). + +*/ + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Registers. + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +/* SMII Status ------------------------------------------------------ */ + +#define APPNIC_RX_SMII_STATUS ( rx_base + 0x10 ) +#define APPNIC_RX_SMII_STATUS_SPEED 0x01 +#define APPNIC_RX_SMII_STATUS_DUPLEX 0x02 +#define APPNIC_RX_SMII_STATUS_LINK 0x04 +#define APPNIC_RX_SMII_STATUS_JABBER 0x08 +#define APPNIC_RX_SMII_STATUS_FCD 0x10 /* False Carrier Detect */ + +#define SMII_SPEED_100( smii_status_ ) \ +( 0 != ( smii_status_ & APPNIC_RX_SMII_STATUS_SPEED ) ) +#define SMII_DUPLEX( smii_status_ ) \ +( 0 != ( smii_status_ & APPNIC_RX_SMII_STATUS_DUPLEX ) ) +#define SMII_LINK( smii_status_ ) \ +( 0 != ( smii_status_ & APPNIC_RX_SMII_STATUS_LINK ) ) +#define SMII_JABBER( smii_status_ ) \ +( 0 != ( smii_status_ & APPNIC_RX_SMII_STATUS_JABBER ) ) + +/* Receive Configuration -------------------------------------------- */ + +#define APPNIC_RX_CONF ( rx_base + 0x004c ) +#define APPNIC_RX_CONF_ENABLE 0x0001 +/* Pass Any Packet */ +#define APPNIC_RX_CONF_PAP 0x0002 +#define APPNIC_RX_CONF_JUMBO9K 0x0008 +#define APPNIC_RX_CONF_STRIPCRC 0x0010 +/* Accept All MAC Types */ +#define APPNIC_RX_CONF_AMT 0x0020 +/* Accept Flow Control */ +#define APPNIC_RX_CONF_AFC 0x0040 +/* Enable VLAN */ +#define APPNIC_RX_CONF_VLAN 0x0200 +/* RX MAC Speed, 1=100MBS */ +#define APPNIC_RX_CONF_SPEED 0x0800 +/* 1=Duplex Mode */ +#define APPNIC_RX_CONF_DUPLEX 0x1000 +/* 1=Enable */ +#define APPNIC_RX_CONF_LINK 0x2000 +/* Determines the action taken when the FE MAC + receives an FC packet in FD mode.*/ +#define APPNIC_RX_CONF_RXFCE 0x4000 +/* Controls the insertion of FC packets + by the MAC transmitter. */ +#define APPNIC_RX_CONF_TXFCE 0x8000 + +/* Receive Stat Overflow -------------------------------------------- */ + +#define APPNIC_RX_STAT_OVERFLOW ( rx_base + 0x278 ) + +/* Receive Stat Undersize ------------------------------------------- */ + +#define APPNIC_RX_STAT_UNDERSIZE ( rx_base + 0x280 ) + +/* Receive Stat Oversize -------------------------------------------- */ + +#define APPNIC_RX_STAT_OVERSIZE ( rx_base + 0x2b8 ) + +/* Receive Stat Multicast ------------------------------------------- */ + +#define APPNIC_RX_STAT_MULTICAST ( rx_base + 0x2d0 ) + +/* Receive Stat Packet OK ------------------------------------------- */ + +#define APPNIC_RX_STAT_PACKET_OK ( rx_base + 0x2c0 ) + +/* Receive Stat CRC Error ------------------------------------------- */ + +#define APPNIC_RX_STAT_CRC_ERROR ( rx_base + 0x2c8 ) + +/* Receive Stat Align Error ----------------------------------------- */ + +#define APPNIC_RX_STAT_ALIGN_ERROR ( rx_base + 0x2e8 ) + +/* Receive Ethernet Mode -------------------------------------------- */ + +#define APPNIC_RX_MODE ( rx_base + 0x0800 ) +#define APPNIC_RX_MODE_ETHERNET_MODE_ENABLE 0x00001 + +/* Receive Soft Reset ----------------------------------------------- */ + +#define APPNIC_RX_SOFT_RESET ( rx_base + 0x0808 ) +#define APPNIC_RX_SOFT_RESET_MAC_0 0x00001 + +/* Receive Internal Interrupt Control ------------------------------- */ + +#define APPNIC_RX_INTERNAL_INTERRUPT_CONTROL ( rx_base + 0xc00 ) +#define APPNIC_RX_INTERNAL_INTERRUPT_CONTROL_MAC_0 0x1 + +/* Receive External Interrupt Control ------------------------------- */ + +#define APPNIC_RX_EXTERNAL_INTERRUPT_CONTROL ( rx_base + 0xc04 ) +#define APPNIC_RX_EXTERNAL_INTERRUPT_CONTROL_MAC_0_HIGH_LOW 0x10 +#define APPNIC_RX_EXTERNAL_INTERRUPT_CONTROL_MAC_0 0x1 + +/* Receive Interrupt Status ----------------------------------------- */ + +#define APPNIC_RX_INTERRUPT_STATUS ( rx_base + 0xc20 ) +#define APPNIC_RX_INTERRUPT_EXTERNAL_STATUS_MAC_0 0x10 +#define APPNIC_RX_INTERRUPT_INTERNAL_STATUS_MAC_0 0x1 + +/* Transmit Watermark ----------------------------------------------- */ + +#define APPNIC_TX_WATERMARK (tx_base + 0x18 ) +#define APPNIC_TX_WATERMARK_TXCONFIG_DTPA_ASSERT 0x8000 +#define APPNIC_TX_WATERMARK_TXCONFIG_DTPA_DISABLE 0x4000 +#define APPNIC_TX_WATERMARK_TXCONFIG_DTPA_WATER_MARK_HIGH 0x3f00 +#define APPNIC_TX_WATERMARK_TXCONFIG_DTPA_WATER_MARK_LOW 0x3f + +/* Swap Source Address Registers ------------------------------------ */ + +#define APPNIC_SWAP_SOURCE_ADDRESS_2 ( tx_base + 0x20 ) +#define APPNIC_SWAP_SOURCE_ADDRESS_1 ( tx_base + 0x24 ) +#define APPNIC_SWAP_SOURCE_ADDRESS_0 ( tx_base + 0x28 ) + +/* Transmit Extended Configuration ---------------------------------- */ + +#define APPNIC_TX_EXTENDED_CONF ( tx_base + 0x30 ) +#define APPNIC_TX_EXTENDED_CONF_TRANSMIT_COLLISION_WATERMARK_LEVEL 0xf000 +#define APPNIC_TX_EXTENDED_CONF_EXCESSIVE_DEFFERED_PACKET_DROP 0x200 +#define APPNIC_TX_EXTENDED_CONF_JUMBO9K 0x100 +#define APPNIC_TX_EXTENDED_CONF_LATE_COLLISION_WINDOW_COUNT 0xff + +/* Transmit Half Duplex Configuration ------------------------------- */ + +#define APPNIC_TX_HALF_DUPLEX_CONF ( tx_base + 0x34 ) +#define APPNIC_TX_HALF_DUPLEX_CONF_RANDOM_SEED_VALUE 0xff + +/* Transmit Configuration ------------------------------------------- */ + +#define APPNIC_TX_CONF ( tx_base + 0x0050 ) +#define APPNIC_TX_CONF_ENABLE_SWAP_SA 0x8000 +#define APPNIC_TX_CONF_LINK 0x2000 +#define APPNIC_TX_CONF_DUPLEX 0x1000 +#define APPNIC_TX_CONF_SPEED 0x0800 +#define APPNIC_TX_CONF_XBK_RST_RX_NTX 0x0600 +#define APPNIC_TX_CONF_IFG 0x01f0 +#define APPNIC_TX_CONF_APP_CRC_ENABLE 0x0004 +#define APPNIC_TX_CONF_PAD_ENABLE 0x0002 +#define APPNIC_TX_CONF_ENABLE 0x0001 + +#define TX_CONF_SET_IFG( tx_configuration_, ifg_ ) do { \ +( tx_configuration_ ) &= ~ APPNIC_TX_CONF_IFG; \ +( tx_configuration_ ) |= ( ( ifg_ & 0x1f ) << 4 ); \ +} while( 0 ); + +/* Transmit Time Value Configuration -------------------------------- */ + +#define APPNIC_TX_TIME_VALUE_CONF ( tx_base + 0x5c ) +#define APPNIC_TX_TIME_VALUE_CONF_PAUSE_VALUE 0xffff + +/* Transmit Stat Underrun ------------------------------------------- */ + +#define APPNIC_TX_STAT_UNDERRUN ( tx_base + 0x300 ) + +/* Transmit Stat Packet OK ------------------------------------------ */ + +#define APPNIC_TX_STAT_PACKET_OK ( tx_base + 0x318 ) + +/* Transmit Stat Undersize ------------------------------------------ */ + +#define APPNIC_TX_STAT_UNDERSIZE ( tx_base + 0x350 ) + +/* Transmit Status Late Collision ----------------------------------- */ + +#define APPNIC_TX_STATUS_LATE_COLLISION ( tx_base + 0x368 ) + +/* Transmit Status Excessive Collision ------------------------------ */ + +#define APPNIC_TX_STATUS_EXCESSIVE_COLLISION ( tx_base + 0x370 ) + +/* Transmit Stat Collision Above Watermark -------------------------- */ + +#define APPNIC_TX_STAT_COLLISION_ABOVE_WATERMARK ( tx_base + 0x380 ) + +/* Transmit Mode ---------------------------------------------------- */ + +#define APPNIC_TX_MODE ( tx_base + 0x800 ) +#define APPNIC_TX_MODE_ETHERNET_MODE_ENABLE 0x1 + +/* Transmit Soft Reset ---------------------------------------------- */ + +#define APPNIC_TX_SOFT_RESET ( tx_base + 0x808 ) +#define APPNIC_TX_SOFT_RESET_MAC_0 0x1 + +/* Transmit Interrupt Control --------------------------------------- */ + +#define APPNIC_TX_INTERRUPT_CONTROL ( tx_base + 0xc00 ) +#define APPNIC_TX_INTERRUPT_CONTROL_MAC_0 0x1 + +/* Transmit Interrupt Status ---------------------------------------- */ + +#define APPNIC_TX_INTERRUPT_STATUS ( tx_base + 0xc20 ) +#define APPNIC_TX_INTERRUPT_STATUS_MAC_0 0x1 + +/* */ + +#define APPNIC_DMA_PCI_CONTROL ( dma_base + 0x00 ) + +/* */ + +#define APPNIC_DMA_CONTROL ( dma_base + 0x08 ) + +/* DMA Interrupt Status --------------------------------------------- */ + +#define APPNIC_DMA_INTERRUPT_STATUS ( dma_base + 0x18 ) +#define APPNIC_DMA_INTERRUPT_STATUS_RX 0x2 +#define APPNIC_DMA_INTERRUPT_STATUS_TX 0x1 + +#define RX_INTERRUPT( dma_interrupt_status_ ) \ +( 0 != ( dma_interrupt_status_ & APPNIC_DMA_INTERRUPT_STATUS_RX ) ) +#define TX_INTERRUPT( dma_interrupt_status_ ) \ +( 0 != ( dma_interrupt_status_ & APPNIC_DMA_INTERRUPT_STATUS_TX ) ) + +/* DMA Interrupt Enable --------------------------------------------- */ + +#define APPNIC_DMA_INTERRUPT_ENABLE ( dma_base + 0x1c ) +#define APPNIC_DMA_INTERRUPT_ENABLE_RECEIVE 0x2 +#define APPNIC_DMA_INTERRUPT_ENABLE_TRANSMIT 0x1 + +/* DMA Receive Queue Base Address ----------------------------------- */ + +#define APPNIC_DMA_RX_QUEUE_BASE_ADDRESS ( dma_base + 0x30 ) + +/* DMA Receive Queue Size ------------------------------------------- */ + +#define APPNIC_DMA_RX_QUEUE_SIZE ( dma_base + 0x34 ) + +/* DMA Transmit Queue Base Address ---------------------------------- */ + +#define APPNIC_DMA_TX_QUEUE_BASE_ADDRESS ( dma_base + 0x38 ) + +/* DMA Transmit Queue Size ------------------------------------------ */ + +#define APPNIC_DMA_TX_QUEUE_SIZE ( dma_base + 0x3c ) + +/* DMA Recevie Tail Pointer Address --------------------------------- */ + +#define APPNIC_DMA_RX_TAIL_POINTER_ADDRESS ( dma_base + 0x48 ) + +/* DMA Transmit Tail Pointer Address -------------------------------- */ + +#define APPNIC_DMA_TX_TAIL_POINTER_ADDRESS ( dma_base + 0x4c ) + +/* DMA Receive Head Pointer ----------------------------------------- */ + +#define APPNIC_DMA_RX_HEAD_POINTER ( dma_base + 0x50 ) +#define APPNIC_DMA_RX_HEAD_POINTER_GB 0x100000 +#define APPNIC_DMA_RX_HEAD_POINTER_POINTER 0x0fffff + +/* DMA Receive Tail Pointer Local Copy ------------------------------ */ + +#define APPNIC_DMA_RX_TAIL_POINTER_LOCAL_COPY ( dma_base + 0x54 ) +#define APPNIC_DMA_RX_TAIL_POINTER_LOCAL_COPY_GB 0x100000 +#define APPNIC_DMA_RX_TAIL_POINTER_LOCAL_COPY_POINTER 0x0fffff + +/* DMA Transmit Head Pointer ---------------------------------------- */ + +#define APPNIC_DMA_TX_HEAD_POINTER ( dma_base + 0x58 ) +#define APPNIC_DMA_TX_HEAD_POINTER_GB 0x100000 +#define APPNIC_DMA_TX_HEAD_POINTER_POINTER 0x0fffff + +/* DMA Transmit Tail Pointer Local Copy ----------------------------- */ + +#define APPNIC_DMA_TX_TAIL_POINTER_LOCAL_COPY ( dma_base + 0x5c ) +#define APPNIC_DMA_TX_TAIL_POINTER_LOCAL_COPY_GB 0x100000 +#define APPNIC_DMA_TX_TAIL_POINTER_LOCAL_COPY_POINTER 0x0fffff + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Access + + N.B. On the APP, DMA transfers from the NIC MUST USE THE MEMORY + ALIAS AT 0x60000000! + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +#ifdef CONFIG_ACP + +#define readio( address ) in_le32( ( u32 * ) ( address ) ) + +#define writeio( value, address ) out_le32( ( u32 * ) ( address ), ( value ) ); + +static inline void +readdescriptor( unsigned long address, appnic_dma_descriptor_t * descriptor ) +{ + unsigned long * from = ( unsigned long * ) address; + unsigned long * to = ( unsigned long * ) descriptor; + * to ++ = swab32( * from ++ ); + * to ++ = swab32( * from ++ ); + * to ++ = swab32( * from ++ ); + * to ++ = swab32( * from ++ ); + return; +} + +static inline void +writedescriptor( unsigned long address, + const appnic_dma_descriptor_t * descriptor ) +{ + unsigned long * to = ( unsigned long * ) address; + unsigned long * from = ( unsigned long * ) descriptor; + * to ++ = swab32( * from ++ ); + * to ++ = swab32( * from ++ ); + * to ++ = swab32( * from ++ ); + * to ++ = swab32( * from ++ ); + return; +} + +static inline appnic_queue_pointer_t +swab_queue_pointer( const appnic_queue_pointer_t * old_queue ) +{ + appnic_queue_pointer_t new_queue; + new_queue.raw = swab32( old_queue->raw ); + return new_queue; +} + +#define SWAB_QUEUE_POINTER( pointer ) \ +swab_queue_pointer( ( const appnic_queue_pointer_t * ) ( pointer ) ) + +#else + +#define readio( address ) readl( ( address ) ) + +#define writeio( value, address ) writel( ( value ), ( address ) ) + +static inline void +readdescriptor( unsigned long address, appnic_dma_descriptor_t * descriptor ) +{ + memcpy( descriptor, ( void * ) address, sizeof( appnic_dma_descriptor_t ) ); + return; +} + +static inline void +writedescriptor( unsigned long address, + const appnic_dma_descriptor_t * descriptor ) +{ + memcpy( ( void * ) address, descriptor, sizeof( appnic_dma_descriptor_t ) ); + return; +} + +static inline unsigned long +swab_queue_pointer( unsigned long old_queue ) +{ + return old_queue; +} + +#endif + +#ifdef LOG_MAC_ACCESS + +static unsigned long read_mac_( unsigned int address ) { + + unsigned long value_ = readio( address ); + + switch( address & 0xfffff000 ) { + + case rx_base: + printk( "-MAC- RX + 0x%04x => 0x%08lx\n", ( address & 0x1fff ), value_ ); + break; + + case tx_base: + printk( "-MAC- TX + 0x%04x => 0x%08lx\n", ( address & 0x1fff ), value_ ); + break; + + case dma_base: + printk( "-MAC- DMA + 0x%04x => 0x%08lx\n", ( address & 0x1fff ), value_ ); + break; + + default: + ERROR_PRINT( "ARGHHHHH!!!\n" ); + break; + + } + + return value_; + +} + +static void write_mac_( unsigned long value, unsigned int address ) { + + switch( address & 0xfffff000 ) { + + case rx_base: + printk( "-MAC- RX + 0x%04x <= 0x%08lx\n", ( address & 0x1fff ), value ); + break; + + case tx_base: + printk( "-MAC- TX + 0x%04x <= 0x%08lx\n", ( address & 0x1fff ), value ); + break; + + case dma_base: + printk( "-MAC- DMA + 0x%04x <= 0x%08lx\n", ( address & 0x1fff ), value ); + break; + + default: + ERROR_PRINT( "ARGHHHHH!!!\n" ); + break; + + } + + writeio( value, address ); + return; + +} + +#else /* ! LOG_MAC_ACCESS */ + +#define read_mac_( address ) readio( ( address ) ) +#define write_mac_( value, address ) writeio( ( value ), ( address ) ) + +#endif + +#ifndef PHYLESS +#ifdef LOG_PHY_ACCESS + +static unsigned long read_phy_( unsigned int address ) { + + unsigned long value_ = readl( address ); + printk( "-PHY- HOST + 0x%04x => 0x%08lx\n", ( address & 0xff ), value_ ); + return value_; + +} + +static void write_phy_( unsigned long value, unsigned int address ) { + + printk( "-PHY- HOST + 0x%04x <= 0x%08lx\n", ( address & 0xff ), value ); + writel( value, address ); + return; + +} + +#else /* ! LOG_PHY_ACCESS */ + +#define read_phy_( address ) readl( ( address ) ) +#define write_phy_( value, address ) writel( value, address ) + +#endif +#endif /* PHYLESS */ + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Module Information + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +MODULE_AUTHOR( "John Jacques" ); +MODULE_DESCRIPTION( "Agere APP3xx ethernet driver" ); +MODULE_LICENSE( "GPL" ); + +/* + ----- Note On Buffer Space ----- + + Minimum number of descriptors is 64 for the receiver and 64 for the + transmitter; therefore, 2048 bytes (16 bytes each). + This driver uses the following parameters, + all of which may be set on the command line if this drivers is used + as a module. + + - rx_num_desc : Number of receive descriptors. This must be a multiple of + 64. + - tx_num_desc : Number of transmit descriptors. This must be a multiple of + 64. + + The scheme used will be as follows: + + - num_[rt]x_desc will be adjusted to be a multiple of 64 (if necessary). + - An skb (with the data area 64 byte aligned) will be allocated for each rx + descriptor. +*/ + +/* + Receiver +*/ + +int rx_num_desc = ( CONFIG_LSI_NET_NUM_RX_DESC * DESCRIPTOR_GRANULARITY ); +module_param( rx_num_desc, int, 0 ); +MODULE_PARM_DESC( rx_num_desc, "appnic : Number of receive descriptors" ); + +int rx_buf_sz = CONFIG_LSI_NET_RX_BUF_SZ; +module_param( rx_buf_sz, int, 0 ); +MODULE_PARM_DESC( rx_buf_sz, "appnic : Receive buffer size" ); + +/* + Transmitter +*/ + +int tx_num_desc = ( CONFIG_LSI_NET_NUM_TX_DESC * DESCRIPTOR_GRANULARITY ); +module_param( tx_num_desc, int, 0 ); +MODULE_PARM_DESC( tx_num_desc, "appnic : Number of receive descriptors" ); + +int tx_buf_sz = CONFIG_LSI_NET_TX_BUF_SZ; +module_param( tx_buf_sz, int, 0 ); +MODULE_PARM_DESC( tx_buf_sz, "Appnic : Receive buffer size" ); + +/* + Timeout, if a transmit takes longer than this + value in jiffies it has timed out. +*/ + +#define DEFAULT_TX_TIMEOUT 10 + +int tx_timeout = DEFAULT_TX_TIMEOUT; +module_param( tx_timeout, int, 0 ); +MODULE_PARM_DESC( tx_timeout, "appnic : Transmit timeout (in jiffies)" ); + +/* + Only 1 device is possible... +*/ + +struct net_device *this_net_device; + +static unsigned long dropped_by_stack_ = 0; +static unsigned long out_of_tx_descriptors_ = 0; +static unsigned long transmit_interrupts_ = 0; +#ifdef LSINET_NAPI +static unsigned long receive_interrupts_ = 0; +#endif + +#define APPNIC_TIMER_PERIOD 5 +#ifndef PHYLESS +static void appnic_timer_handler_( unsigned long ); +static struct timer_list appnic_timer_; +#endif /* PHYLESS */ + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Locking... + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +#ifdef CONFIG_SMP +/* + * On SMP we have the following problem: + * + * A = smc_hard_start_xmit() + * B = smc_interrupt() + * + * A and B can never be executed simultaneously. However, at least on UP, + * it is possible (and even desirable) for C to interrupt execution of + * A or B in order to have better RX reliability and avoid overruns. + * C, just like A and B, must have exclusive access to the chip and + * each of them must lock against any other concurrent access. + * Unfortunately this is not possible to have C suspend execution of A or + * B taking place on another CPU. On UP this is no an issue since A and B + * are run from softirq context and C from hard IRQ context, and there is + * no other CPU where concurrent access can happen. + * If ever there is a way to force at least B and C to always be executed + * on the same CPU then we could use read/write locks to protect against + * any other concurrent access and C would always interrupt B. But life + * isn't that easy in a SMP world... + */ + +#define appnic_special_trylock(lock) \ + ({ \ + int __ret; \ + local_irq_disable(); \ + __ret = spin_trylock(lock); \ + if (!__ret) \ + local_irq_enable(); \ + __ret; \ + }) +#define appnic_special_lock(lock) spin_lock_irq(lock) +#define appnic_special_unlock(lock) spin_unlock_irq(lock) +#else +#define appnic_special_trylock(lock) (1) +#define appnic_special_lock(lock) do { } while (0) +#define appnic_special_unlock(lock) do { } while (0) +#endif + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Utility Functions + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + clear_statistics_ +*/ + +static void clear_statistics_( appnic_device_t * device ) { + + int waste_; + + /* + Clear memory. + */ + + memset( ( void * ) & ( device->stats ), 0, + sizeof( struct net_device_stats ) ); + + /* + Clear counters. + */ + + waste_ = read_mac_( APPNIC_RX_STAT_PACKET_OK ); /* rx_packets */ + waste_ = read_mac_( APPNIC_TX_STAT_PACKET_OK ); /* tx_packets */ + /* rx_bytes kept by driver. */ + /* tx_bytes kept by driver. */ + /* rx_errors will be the sum of the rx errors available. */ + /* tx_errors will be the sum of the tx errors available. */ + /* rx_dropped (unable to allocate skb) will be maintained by the driver */ + /* tx_dropped (unable to allocate skb) will be maintained by the driver */ + /* multicast */ + waste_ = read_mac_( APPNIC_RX_STAT_MULTICAST ); + /* collisions will be the sum of the three following. */ + waste_ = read_mac_( APPNIC_TX_STATUS_LATE_COLLISION ); + waste_ = read_mac_( APPNIC_TX_STATUS_EXCESSIVE_COLLISION ); + waste_ = read_mac_( APPNIC_TX_STAT_COLLISION_ABOVE_WATERMARK ); + /* rx_length_errors will be the sum of the two following. */ + waste_ = read_mac_( APPNIC_RX_STAT_UNDERSIZE ); + waste_ = read_mac_( APPNIC_RX_STAT_OVERSIZE ); + /* rx_over_errors (out of descriptors?) maintained by the driver. */ + /* rx_crc_errors */ + waste_ = read_mac_( APPNIC_RX_STAT_CRC_ERROR ); + /* rx_frame_errors */ + waste_ = read_mac_( APPNIC_RX_STAT_ALIGN_ERROR ); + /* rx_fifo_errors */ + waste_ = read_mac_( APPNIC_RX_STAT_OVERFLOW ); + /* rx_missed will not be maintained. */ + /* tx_aborted_errors will be maintained by the driver. */ + /* tx_carrier_errors will not be maintained. */ + /* tx_fifo_errors */ + waste_ = read_mac_( APPNIC_TX_STAT_UNDERRUN ); + /* tx_heartbeat_errors */ + /* tx_window_errors */ + + /* rx_compressed will not be maintained. */ + /* tx_compressed will not be maintained. */ + + /* + That's all. + */ + + return; + +} + +/* + ---------------------------------------------------------------------- + get_hw_statistics_ + + -- NOTES -- + + 1) The hardware clears the statistics registers after a read. +*/ + +static void get_hw_statistics_( appnic_device_t * device ) { + + /* tx_packets */ + device->stats.tx_packets += read_mac_( APPNIC_TX_STAT_PACKET_OK ); + /* multicast */ + device->stats.multicast += read_mac_( APPNIC_RX_STAT_MULTICAST ); + /* collision */ + device->stats.collisions += read_mac_( APPNIC_TX_STATUS_LATE_COLLISION ); + device->stats.collisions += + read_mac_( APPNIC_TX_STATUS_EXCESSIVE_COLLISION ); + device->stats.collisions += + read_mac_( APPNIC_TX_STAT_COLLISION_ABOVE_WATERMARK ); + /* rx_length_errors */ + device->stats.rx_length_errors += read_mac_( APPNIC_RX_STAT_UNDERSIZE ); + device->stats.rx_length_errors += read_mac_( APPNIC_RX_STAT_OVERSIZE ); + /* tx_fifo_errors */ + device->stats.tx_fifo_errors += read_mac_( APPNIC_TX_STAT_UNDERRUN ); + + /* + Lock this section out so the statistics maintained by the driver + don't get clobbered. + */ + + { + + unsigned long flags_; + + spin_lock_irqsave( & device->lock, flags_ ); + + device->stats.rx_errors += + ( device->stats.rx_length_errors + + device->stats.rx_crc_errors + + device->stats.rx_frame_errors + + device->stats.rx_fifo_errors + + device->stats.rx_dropped + + device->stats.rx_over_errors ); + device->stats.rx_dropped = 0; + device->stats.rx_over_errors = 0; + + device->stats.tx_errors += + ( device->stats.tx_fifo_errors + + device->stats.tx_aborted_errors ); + device->stats.tx_aborted_errors = 0; + + spin_unlock_irqrestore( & device->lock, flags_ ); + + } + + /* + That's all. + */ + + return; + +} + +/* + ---------------------------------------------------------------------- + queue_initialized_ + + Returns the number of descriptors that are ready to receive packets + or are waiting to transmit packets. (from tail to head). +*/ + +static int queue_initialized_( appnic_queue_pointer_t head, + appnic_queue_pointer_t tail, + int size ) { + int initialized; + + /* Calculate the number of descriptors currently initialized. */ + + if( head.bits.generation_bit == tail.bits.generation_bit ) { + + /* same generation */ + initialized = ( head.bits.offset - tail.bits.offset ); + + } else { + + /* different generation */ + initialized = head.bits.offset + + ( size * sizeof( appnic_dma_descriptor_t ) - tail.bits.offset ); + + } + + /* number of descriptors is offset / sizeof( a descriptor ) */ + initialized /= sizeof( appnic_dma_descriptor_t ); + + return initialized; +} + +/* + ---------------------------------------------------------------------- + queue_uninitialzed_ + + Returns the number of unused/uninitialized descriptors. (from head to tail). +*/ + +static int queue_uninitialized_( appnic_queue_pointer_t head, + appnic_queue_pointer_t tail, + int size ) { + + int allocated_; + + /* calculate the number of descriptors currently unused/uninitialized */ + + if( head.bits.generation_bit == tail.bits.generation_bit ) { + + /* same generation. */ + allocated_ = + ( ( size * sizeof( appnic_dma_descriptor_t ) ) - head.bits.offset ) + + tail.bits.offset; + + } else { + + /* different generation. */ + allocated_ = tail.bits.offset - head.bits.offset; + + } + + /* number of descriptors is offset / sizeof( a descriptor ). */ + allocated_ /= sizeof( appnic_dma_descriptor_t ); + + /* that's all */ + return allocated_; + +} + +/* + ---------------------------------------------------------------------- + queue_increment_ +*/ + +static void queue_increment_( appnic_queue_pointer_t * queue, + int number_of_descriptors ) { + + queue->bits.offset += sizeof( appnic_dma_descriptor_t ); + + if( ( number_of_descriptors * sizeof( appnic_dma_descriptor_t ) ) == + queue->bits.offset ) { + + queue->bits.offset = 0; + queue->bits.generation_bit = ( 0 == queue->bits.generation_bit ) ? 1 : 0; + + } + + return; + +} + +/* + ---------------------------------------------------------------------- + queue_decrement_ +*/ + +static void queue_decrement_( appnic_queue_pointer_t * queue, + int number_of_descriptors ) { + + if( 0 == queue->bits.offset ) { + + queue->bits.offset = + ( ( number_of_descriptors - 1 ) * sizeof( appnic_dma_descriptor_t ) ); + queue->bits.generation_bit = ( 0 == queue->bits.generation_bit ) ? 1 : 0; + + } else { + + queue->bits.offset -= sizeof( appnic_dma_descriptor_t ); + + } + + return; + +} + +/* + ---------------------------------------------------------------------- + dump_packet_ +*/ + +#if 0 +static void dump_packet_( const char * title, const void * data, int length ) { + + int data_index_ = 0; + + printk( "\n--appnic--dump_packet_( %s, 0x%p, %d)\n", title, data, length ); + + while( data_index_ < ( length / 2 ) ) { + + int output_index_; + unsigned short * data_ = + & ( ( ( unsigned short * ) data ) [ data_index_ ] ); + + for( output_index_ = 0; + ( output_index_ < 8 ) && + ( ( output_index_ + data_index_ ) < length ); + ++ output_index_, ++ data_index_ ) { + + printk( "%04x ", + htons( ( ( unsigned short * ) data_ ) [ output_index_ ] ) ); + + } + + printk( "\n" ); + + } + +} +#endif + +/* + ---------------------------------------------------------------------- + dump_descriptor_ +*/ + +#if 0 +static void dump_descriptor_( const char * title, + appnic_dma_descriptor_t * descriptor ) { + + printk( "--appnic--dump_descriptor_( %s, 0x%p)\n", title, descriptor ); + printk( " byte_swapping_on=%d\n" \ + " interrupt_on_completion=%d\n" \ + " end_of_packet=%d\n" \ + " start_of_packet=%d\n" \ + " write=%d\n" \ + " transfer_type=0x%x\n" \ + " pdu_length=0x%x\n" \ + " data_transfer_length=0x%x\n" \ + " target_memory_address=0x%x\n" \ + "host_data_memory_pointer=0x%x\n", + ( unsigned int ) ( descriptor->byte_swapping_on ), + ( unsigned int ) ( descriptor->interrupt_on_completion ), + ( unsigned int ) ( descriptor->end_of_packet ), + ( unsigned int ) ( descriptor->start_of_packet ), + ( unsigned int ) ( descriptor->write ), + ( unsigned int ) ( descriptor->transfer_type ), + ( unsigned int ) ( descriptor->pdu_length ), + ( unsigned int ) ( descriptor->data_transfer_length ), + ( unsigned int ) ( descriptor->target_memory_address ), + ( unsigned int ) ( descriptor->host_data_memory_pointer ) ); + +} +#endif + +/* + ---------------------------------------------------------------------- + appnic_timer_handler_ +*/ + +#ifndef PHYLESS + +static void appnic_timer_handler_( unsigned long __opaque ) { + + struct net_device * device_ = ( struct net_device * ) __opaque; + + PHY_DEBUG_PRINT( "Handling Timer Expiration.\n" ); + enable_( device_ ); + appnic_timer_.expires = jiffies + ( APPNIC_TIMER_PERIOD * HZ ); + add_timer( & appnic_timer_ ); + +} + +#endif + +/* + ---------------------------------------------------------------------- + enable_ + + -- NOTES -- + + 1) Does not change the default values in the extended and + half-duplex configuration registers. +*/ + +static int enable_( struct net_device * device ) { + +#ifndef PHYLESS + + int return_code_ = 1; + int carrier_state_ = 0; + unsigned long rx_configuration_; + unsigned long tx_configuration_ = 0; + phy_status_t phy_status_; + + rx_configuration_ = + ( APPNIC_RX_CONF_STRIPCRC | + APPNIC_RX_CONF_RXFCE | + APPNIC_RX_CONF_TXFCE ); + tx_configuration_ = + ( APPNIC_TX_CONF_ENABLE_SWAP_SA | + APPNIC_TX_CONF_APP_CRC_ENABLE | + APPNIC_TX_CONF_PAD_ENABLE ); + TX_CONF_SET_IFG( tx_configuration_, 0xf ); + + DEBUG_PRINT( "Enabling the interface.\n" ); + + /* + Setup the receive and transmit configuration registers (using smii + status to set speed/duplex and check the link status). + */ + + if( ( 0 == phy_read_( phy_address_, PHY_STATUS, & phy_status_.raw ) ) && + ( 0 == phy_read_( phy_address_, PHY_STATUS, & phy_status_.raw ) ) ) { + + PHY_DEBUG_PRINT( "phy_status_.raw=0x%x\n", phy_status_.raw ); + + if( 1 == phy_status_.bits.autoneg_comp ) { + + if( 1 == phy_status_.bits.link_status ) { + + if( 1 == phy_speed_( phy_address_ ) ) { + + rx_configuration_ |= APPNIC_RX_CONF_SPEED; + tx_configuration_ |= APPNIC_TX_CONF_SPEED; + + } + + if( 1 == phy_duplex_( phy_address_ ) ) { + + rx_configuration_ |= APPNIC_RX_CONF_DUPLEX; + tx_configuration_ |= APPNIC_TX_CONF_DUPLEX; + + } + + rx_configuration_ |= + ( APPNIC_RX_CONF_ENABLE | APPNIC_RX_CONF_LINK ); + tx_configuration_ |= + ( APPNIC_TX_CONF_LINK | APPNIC_TX_CONF_ENABLE ); + return_code_ = 0; + carrier_state_ = 1; + + } else { + + netif_carrier_off( device ); + + } + + } else { + + netif_carrier_off( device ); + + } + + } else { + + ERROR_PRINT( "phy_read_( ) failed!\n" ); + + } + +#else /* PHYLESS */ + + int return_code_ = 1; + int carrier_state_ = 0; + unsigned long rx_configuration_; + unsigned long tx_configuration_ = 0; + + rx_configuration_ = APPNIC_RX_CONF_STRIPCRC; + tx_configuration_ = + ( APPNIC_TX_CONF_ENABLE_SWAP_SA | + APPNIC_TX_CONF_APP_CRC_ENABLE | + APPNIC_TX_CONF_PAD_ENABLE ); + TX_CONF_SET_IFG( tx_configuration_, 0xf ); + + /* + 100/Full + */ +#if 0 + rx_configuration_ |= + ( APPNIC_RX_CONF_ENABLE | APPNIC_RX_CONF_LINK | + APPNIC_RX_CONF_DUPLEX | APPNIC_RX_CONF_SPEED ); + tx_configuration_ |= + ( APPNIC_TX_CONF_ENABLE | APPNIC_TX_CONF_LINK | + APPNIC_TX_CONF_DUPLEX | APPNIC_TX_CONF_SPEED ); +#endif + + /* + 100/Half + */ +#if 1 + rx_configuration_ |= + ( APPNIC_RX_CONF_ENABLE | APPNIC_RX_CONF_LINK | + APPNIC_RX_CONF_SPEED ); + tx_configuration_ |= + ( APPNIC_TX_CONF_ENABLE | APPNIC_TX_CONF_LINK | + APPNIC_TX_CONF_SPEED ); +#endif + + /* + 10/Full + */ +#if 0 + rx_configuration_ |= + ( APPNIC_RX_CONF_ENABLE | APPNIC_RX_CONF_LINK | + APPNIC_RX_CONF_DUPLEX ); + tx_configuration_ |= + ( APPNIC_TX_CONF_ENABLE | APPNIC_TX_CONF_LINK | + APPNIC_TX_CONF_DUPLEX ); +#endif + + /* + 10/Half + */ +#if 0 + rx_configuration_ |= + ( APPNIC_RX_CONF_ENABLE | APPNIC_RX_CONF_LINK ); + tx_configuration_ |= + ( APPNIC_TX_CONF_ENABLE | APPNIC_TX_CONF_LINK ); +#endif + + return_code_ = 0; + carrier_state_ = 1; + +#endif /* PHYLESS */ + + if( rx_configuration_ != read_mac_( APPNIC_RX_CONF ) ) { + + write_mac_( rx_configuration_, APPNIC_RX_CONF ); + + } + + if( tx_configuration_ != read_mac_( APPNIC_TX_CONF ) ) { + + write_mac_( tx_configuration_, APPNIC_TX_CONF ); + + } + + if( 0 != carrier_state_ ) { + + netif_carrier_on( device ); + + } else { + + netif_carrier_off( device ); + + } + + return return_code_; + +} + +/* + ---------------------------------------------------------------------- + disable_ +*/ + +static void disable_( void ) { + + unsigned long tx_configuration_; + unsigned long rx_configuration_; + + DEBUG_PRINT( "Disabling the interface.\n" ); + + rx_configuration_ = read_mac_( APPNIC_RX_CONF ); + rx_configuration_ &= ~ APPNIC_RX_CONF_ENABLE; + write_mac_( rx_configuration_, APPNIC_RX_CONF ); + + tx_configuration_ = read_mac_( APPNIC_TX_CONF ); + tx_configuration_ &= ~ APPNIC_TX_CONF_ENABLE; + write_mac_( tx_configuration_, APPNIC_TX_CONF ); + + /* that's all. */ + return; + +} + +void disable_nic_( void ) { + + disable_( ); + +} + +/* + ====================================================================== + ====================================================================== + ====================================================================== + PHY interface (BCM5221) + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +#ifndef PHYLESS + +/* + ---------------------------------------------------------------------- + phy_read_ + + Returns -1 if unsuccessful, the (short) value otherwise. +*/ + +static int +phy_read_( int phy, int reg, unsigned short * value ) +{ + return acp_mdio_read(phy, reg, value); +} + +/* + ---------------------------------------------------------------------- + phy_write_ +*/ + +static int +phy_write_( int phy, int reg, unsigned short value ) +{ + return acp_mdio_write(phy, reg, value); +} + +/* + ---------------------------------------------------------------------- + phy_link_ + + Returns the link status (1=link up, 0=link down) or an error (-1). +*/ + +static int +phy_link_( int phy ) +{ + phy_status_t status; + + phy_read_( phy, PHY_STATUS, & status.raw ); + phy_read_( phy, PHY_STATUS, & status.raw ); + + return status.bits.link_status; +} + +/* + ---------------------------------------------------------------------- + phy_speed_ + + Returns the speed (1=100, 0=10) or an error (-1). +*/ + +static int +phy_speed_( int phy ) +{ + micrel_phy_auxiliary_control_status_t aux; + + phy_read_( phy, MICREL_PHY_AUXILIARY_CONTROL_STATUS, & aux.raw ); + switch( ( aux.bits.op_mode_indication & 3 ) ) { + case 2: return 1; break; + case 1: return 0; break; + default: break; + } + + return -1; +} + +/* + ---------------------------------------------------------------------- + phy_duplex_ + + Returns duplex status (1=full duplex, 0=half duplex) or an error (-1). +*/ + +static int +phy_duplex_( int phy ) +{ + micrel_phy_auxiliary_control_status_t aux; + + phy_read_( phy, MICREL_PHY_AUXILIARY_CONTROL_STATUS, & aux.raw ); + + return ( ( aux.bits.op_mode_indication >> 2 ) & 0x1 ); +} + +/* + ---------------------------------------------------------------------- + phy_reset_ +*/ + +static int +phy_reset_( int phy ) +{ + phy_control_t control; + int retries = 10; + + phy_read_( phy, PHY_CONTROL, & control.raw ); + control.bits.soft_reset = 1; + phy_write_( phy, PHY_CONTROL, control.raw ); + + do { + phy_read_( phy, PHY_CONTROL, & control.raw ); + -- retries; + } while( ( 0 < retries ) && ( 0 != control.bits.soft_reset ) ); + + if( 0 != control.bits.soft_reset ) { + printk( "phy_reset( %d ) failed.\n", phy ); + return -1; + } + + return 0; +} + +/* + ---------------------------------------------------------------------- + phy_renegotiate_ +*/ + +static int +phy_renegotiate_( int phy ) +{ + phy_control_t control; + phy_status_t status; + int autoneg_retries = 4; + int autoneg_complete_retries = 8; + + printk( "Initiating Auto Negotiation" ); + phy_write_( phy, PHY_AUTONEG_ADVERTISE, 0x61 ); + + do { + phy_read_( phy, PHY_CONTROL, & control.raw ); + control.bits.restart_autoneg = 1; + phy_write_( phy, PHY_CONTROL, control.raw ); + + do { + udelay( 500000 ); + phy_read_( phy, PHY_STATUS, & status.raw ); + } while( ( 0 < -- autoneg_complete_retries ) && + ( 0 == status.bits.autoneg_comp ) ); + + if( 0 != status.bits.autoneg_comp ) { + break; + } + + printk( "." ); + } while( 0 < -- autoneg_retries ); + + printk( "\n" ); + + if( 0 == status.bits.autoneg_comp ) { + printk( "Auto Negotiation Failed\n" ); + return -1; + } + + printk( "Auto Negotiation Succeeded\n" ); + return 0; +} + +/* + ---------------------------------------------------------------------- + phy_enable_ +*/ + +extern int ubootenv_get( const char *, char * ); + +static int phy_enable_( int phy ) { + +#ifdef CONFIG_ACP + phy_address_ = 0x1e; + phy_renegotiate_( phy_address_ ); +#else + /* + Set up the MDIO clock. + */ + + { + + char mdio_clock_speed_string_ [ 256 ]; + unsigned long mdio_clock_speed_; + unsigned long mdio_divisor_; + + if( 0 != ubootenv_get( "mdio_clock", mdio_clock_speed_string_ ) ) { + + mdio_clock_speed_ = 1250000; + + } else { + + mdio_clock_speed_ = simple_strtoul( mdio_clock_speed_string_, NULL, 0 ); + + } + +#ifdef CONFIG_ARCH_APP3K + mdio_divisor_ = + ( ( get_core_speed( ) / 2 ) / mdio_clock_speed_ ); +#else + mdio_divisor_ = ( get_core_speed( ) / mdio_clock_speed_ ); +#endif + + printk( "Setting the MDIO clock to %lu Hz (divisor=%lu)\n", + mdio_clock_speed_, mdio_divisor_ ); + writel( mdio_divisor_, MDIO_CLK_ ); + + } + + /* + Get the PHY address. + */ + + { + + char phy_address_string_ [ 256 ]; + + if( 0 != ubootenv_get( "phy_address", phy_address_string_ ) ) { + + phy_address_ = phy_scan_( ); + + } else { + + phy_address_ = simple_strtoul( phy_address_string_, NULL, 0 ); + + } + + if( 31 < phy_address_ || 0 > phy_address_ ) { + + ERROR_PRINT( "Unable to get valid PHY address!\n" ); + return -EBUSY; + + } + + } + + /* + Get PHY type. + */ + + { + + phy_id_high_t phy_id_high_; + phy_id_low_t phy_id_low_; + + if( 0 != phy_read_( phy_address_, PHY_ID_HIGH_, & phy_id_high_.raw ) ) { + + TRACE_ENDING( ); + return -1; + + } + + if( 0 != phy_read_( phy_address_, PHY_ID_LOW_, & phy_id_low_.raw ) ) { + + TRACE_ENDING( ); + return -1; + + } + + if( ( PHY_ID_HIGH_ID == phy_id_high_.bits.id ) && + ( BC_PHY_ID_LOW_ID_ == phy_id_low_.bits.id ) && + ( BC_PHY_ID_LOW_MODEL_ == phy_id_low_.bits.model ) ) { + + phy_type_ = BCM5221_PHY_; + printk( "Broadcomm 5221 PHY at 0x%x\n", phy_address_ ); + + } else if( ( M_PHY_ID_HIGH_ID_ == phy_id_high_.bits.id ) && + ( M_PHY_ID_LOW_ID_ == phy_id_low_.bits.id ) ) { + + phy_type_ = MICREL_PHY_; + printk( "Micrel PHY at 0x%x, Model 0x%x\n", + phy_address_, phy_id_low_.bits.model ); + + } else { + + phy_type_ = UNKNOWN_PHY_; + printk( "Unknown PHY at 0x%x. 0x%x 0x%x 0x%x\n", + phy_address_, phy_id_high_.bits.id, phy_id_low_.bits.id, + phy_id_low_.bits.model ); + + } + + } + + if( -1 != phy_address_ ) { + + int link_status_retries_ = 10; + phy_status_t phy_status_; + char ad_value_string_ [ 40 ]; + unsigned short ad_value_; + + DEBUG_PRINT( "Initializing PHY at 0x%x\n", phy_address_ ); + + if( 0 != phy_reset_( phy_address_ ) ) { + + return -1; + + } + + /* + 0x1e1 - 10/100 half/full + 0xe1 - 100 half, 10 half/full + 0x61 - 10 half/full + 0x41 - 10 half + */ + + if( 0 != ubootenv_get( "ad_value", ad_value_string_ ) ) { + + if( ( is_asic ) && + ( 0 == ( APP3XX_REVISION_REGISTER & 0x1f ) ) ) { + + /* 10M does not work on ASIC v1.0 */ + ad_value_ = 0x0181; + + } else { + + /* For FGPA loads and any ASIC after v1.0, default to 10 full/half */ + ad_value_ = 0x061; + + } + + WARN_PRINT( "ad_value not set, using 0x%x\n", ad_value_ ); + + } else { + + ad_value_ = simple_strtoul( ad_value_string_, NULL, 0 ); + + } + + if( 0 != phy_write_( phy_address_, PHY_AUTONEG_ADVERTISE_, + ad_value_ ) ) { + + TRACE_ENDING( ); + return -1; + + } + + if( 0 != phy_renegotiate_( phy_address_ ) ) { + + WARN_PRINT( "PHY: Auto Negotiation Failed.\n" ); + + } + + do { + + if( 0 != phy_read_( phy_address_, PHY_STATUS, & phy_status_.raw ) ) { + + return -1; + + } + + mdelay( 10 ); + -- link_status_retries_; + + } while( ( 0 == phy_status_.bits.link_status ) && + ( 0 < link_status_retries_ ) ); + + if( 0 == phy_status_.bits.link_status ) { + + WARN_PRINT( "PHY: link down\n" ); + + } else { + + printk( "PHY: link=%s speed=%d Mbs duplex=%s\n", + ( 1 == phy_link_( phy_address_ ) ) ? "up" : "down", + ( 1 == phy_speed_( phy_address_ ) ) ? 100 : 10, + ( 1 == phy_duplex_( phy_address_ ) ) ? "full" : "half" ); + + } + + } + +#endif + + /* + That's all + */ + + return 0; + +} + +#endif /* PHYLESS */ + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Linux Network Driver Interface + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + handle_transmit_interrupt_ +*/ + +static void handle_transmit_interrupt_( struct net_device * device ) { + + appnic_device_t * dev_ = netdev_priv( device ); + + TRACE_BEGINNING( ); + DEBUG_PRINT( "tail=0x%lx tail_copy=0x%lx head=0x%lx\n", + dev_->tx_tail->raw, dev_->tx_tail_copy.raw, + dev_->tx_head.raw ); + + /* + The hardware's tail pointer should be one descriptor (or more) + ahead of software's copy. + */ + + while( 0 < queue_initialized_( SWAB_QUEUE_POINTER( dev_->tx_tail ), + dev_->tx_tail_copy, dev_->tx_num_desc ) ) { + queue_increment_( & dev_->tx_tail_copy, dev_->tx_num_desc ); + } + + DEBUG_PRINT( "tail=0x%lx tail_copy=0x%lx head=0x%lx\n", + dev_->tx_tail->raw, dev_->tx_tail_copy.raw, + dev_->tx_head.raw ); + TRACE_ENDING( ); + + return; + +} + +static DEFINE_MUTEX( rpm ); + +/* + ---------------------------------------------------------------------- + lsinet_rx_packet +*/ + +static void +lsinet_rx_packet( struct net_device * device ) +{ + appnic_device_t * adapter = netdev_priv( device ); + appnic_dma_descriptor_t descriptor; + struct sk_buff * sk_buff_; + +#ifdef __APPNIC_C_PROFILE__ + unsigned long ts0_ = 0; + unsigned long ts1_ = 0; + unsigned long ts2_ = 0; + unsigned long ts3_ = 0; + int sent_up = 0; + ts0_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); +#endif /* __APPNIC_C_PROFILE__ */ + + /* TEMP HACK: + * should use down_interruptible + */ + spin_lock( & adapter->extra_lock ); + TRACE_BEGINNING( ); + DEBUG_PRINT( "head=0x%lx tail=0x%lx tail_copy=0x%lx\n", + adapter->rx_head.raw, adapter->rx_tail->raw, + adapter->rx_tail_copy.raw ); + readdescriptor( ( ( unsigned long ) adapter->rx_desc + + adapter->rx_tail_copy.bits.offset ), & descriptor ); + + if( ( struct sk_buff * ) 0 != ( sk_buff_ = dev_alloc_skb( 1600 ) ) ) { + unsigned bytes_copied_ = 0; + unsigned error_ = 0; + int return_code_; + unsigned long ok_, overflow_, crc_, align_; + +#ifdef __APPNIC_C_PROFILE__ + ts1_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); +#endif /* __APPNIC_C_PROFILE__ */ + + ok_ = read_mac_( APPNIC_RX_STAT_PACKET_OK ); + overflow_ = read_mac_( APPNIC_RX_STAT_OVERFLOW ); + crc_ = read_mac_( APPNIC_RX_STAT_CRC_ERROR ); + align_ = read_mac_( APPNIC_RX_STAT_ALIGN_ERROR ); + + /* + Copy the received packet into the skb. + */ + + while( 0 < queue_initialized_( SWAB_QUEUE_POINTER( adapter->rx_tail ), + adapter->rx_tail_copy, adapter->rx_num_desc ) ) { + /*TRACER_POST( "tail_copy=0x%x", adapter->rx_tail_copy.raw );*/ +#ifdef PRELOAD_RX_BUFFERS + { + unsigned char * buffer_; + buffer_ = skb_put( sk_buff_, descriptor.pdu_length ); + memcmp( buffer_, buffer_, descriptor.pdu_length ); + memcpy( ( void * ) buffer_, + ( void * ) ( descriptor.host_data_memory_pointer + + adapter->dma_alloc_offset ), + descriptor.pdu_length ); + } +#else /* PRELOAD_RX_BUFFERS */ + memcpy( ( void * ) skb_put( sk_buff_, descriptor.pdu_length ), + ( void * ) ( descriptor.host_data_memory_pointer + + adapter->dma_alloc_offset ), + descriptor.pdu_length ); +#endif /* PRELOAD_RX_BUFFERS */ + bytes_copied_ += descriptor.pdu_length; + descriptor.data_transfer_length = adapter->rx_buf_per_desc; + writedescriptor( ( ( unsigned long ) adapter->rx_desc + + adapter->rx_tail_copy.bits.offset ), & descriptor ); + if( 0 != descriptor.error ) { error_ = 1; } + queue_increment_( & adapter->rx_tail_copy, adapter->rx_num_desc ); + if( 0 != descriptor.end_of_packet ) { break; } + readdescriptor( ( ( unsigned long ) adapter->rx_desc + + adapter->rx_tail_copy.bits.offset ), & descriptor ); + } + + if( 0 == descriptor.end_of_packet ) { + + ERROR_PRINT( "No end of packet! %lu/%lu/%lu/%lu\n", + ok_, overflow_, crc_, align_ ); + BUG( ); + dev_kfree_skb( sk_buff_ ); + + } else { + + if( 0 == error_ ) { + + struct ethhdr * ethhdr_ = ( struct ethhdr * ) sk_buff_->data; + unsigned char broadcast_ [ ] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + unsigned char multicast_ [ ] = { 0x01, 0x00 }; + + LSINET_COUNTS_INC( LSINET_COUNTS_RX_GOOD ); + + if( ( 0 == memcmp( ( const void * ) & ( ethhdr_->h_dest [ 0 ] ), + ( const void * ) & ( device->dev_addr [ 0 ] ), + sizeof( ethhdr_->h_dest ) ) ) || + ( 0 == memcmp( ( const void * ) & ( ethhdr_->h_dest [ 0 ] ), + ( const void * ) & ( broadcast_ [ 0 ] ), + sizeof( ethhdr_->h_dest ) ) ) || + ( 0 == memcmp( ( const void * ) & (ethhdr_->h_dest [ 0 ] ), + ( const void * ) & ( multicast_ [ 0 ] ), + sizeof( multicast_ ) ) ) ) { + +#ifdef __APPNIC_C_PROFILE__ + if( bytes_copied_ > rx_packet_size_max_ ) { + rx_packet_size_max_ = bytes_copied_; + } else if( bytes_copied_ < rx_packet_size_min_ ) { + rx_packet_size_min_ = bytes_copied_; + } + total_rx_bytes_ += bytes_copied_; + + total_rx_packets_sent_up_++; + sent_up = 1; + + ts2_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); +#endif /* __APPNIC_C_PROFILE__ */ + + adapter->stats.rx_bytes += bytes_copied_; + ++ adapter->stats.rx_packets; + sk_buff_->dev = device; + sk_buff_->protocol = eth_type_trans( sk_buff_, device ); +#ifdef LSINET_NAPI + LSINET_COUNTS_INC( LSINET_COUNTS_RX_SENT ); + return_code_ = netif_receive_skb( sk_buff_ ); +#else + LSINET_COUNTS_INC( LSINET_COUNTS_RX_SENT ); + return_code_ = netif_rx( sk_buff_ ); +#endif + + if( NET_RX_DROP == return_code_ ) { + + ++ dropped_by_stack_; + LSINET_COUNTS_INC( LSINET_COUNTS_RX_DRPD ); +#if 0 + ERROR_PRINT( "Packet dropped by stack: 0x%x!\n", return_code_ ); + { + unsigned long * packet = ( unsigned long * ) sk_buff_->data; + int data_index_ = 0; + static int bug = 10; + + printk( "\n---------- Dropped Packet\n" ); + printk( "Head:0x%lx Tail:0x%lx Tail Copy:0x%x\n", + adapter->rx_head.raw, adapter->rx_tail->raw, + read_mac_( APPNIC_DMA_RX_TAIL_POINTER_LOCAL_COPY ) ); + printk( "Address:0x%lx Length:0x%x\n", + ( unsigned long ) packet, bytes_copied_ ); + + while( data_index_ < ( bytes_copied_ / 2 ) ) { + + int output_index_; + unsigned short * data_ = + & ( ( ( unsigned short * ) packet ) [ data_index_ ] ); + + for( output_index_ = 0; + ( output_index_ < 8 ) && ( data_index_ < bytes_copied_ ); + ++ output_index_, ++ data_index_ ) { + + printk( "%04x ", htons( data_ [ output_index_ ] ) ); + + } + + printk( "\n" ); + + } + + if( 0 == -- bug ) BUG( ); + + } +#endif + } + + } else { + + dev_kfree_skb( sk_buff_ ); + + } + + } else { + + LSINET_COUNTS_INC( LSINET_COUNTS_RX_ERR ); + + dev_kfree_skb( sk_buff_ ); + + if( 0 != overflow_ ) { + + ++ adapter->stats.rx_fifo_errors; + + } else if( 0 != crc_ ) { + + ++ adapter->stats.rx_crc_errors; + + } else if( 0 != align_ ) { + + ++ adapter->stats.rx_frame_errors; + + } + + } + + } + + } else { + + ERROR_PRINT( "dev_alloc_skb( ) failed! Dropping packet.\n" ); + + } + + DEBUG_PRINT( "head=0x%lx tail=0x%lx tail_copy=0x%lx\n", + adapter->rx_head.raw, adapter->rx_tail->raw, + adapter->rx_tail_copy.raw ); + TRACE_ENDING( ); + +#ifdef __APPNIC_C_PROFILE__ + + app3xx_profile_time_calc(ts0_, ts1_, + recv_t1_min_, recv_t1_max_, recv_t1_tot_); + /* + * only calculate stats for packets that were sent up to the stack + */ + if (sent_up) { + ts3_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); + + app3xx_profile_time_calc(ts1_, ts2_, + recv_t2_min_, recv_t2_max_, recv_t2_tot_); + app3xx_profile_time_calc(ts2_, ts3_, + recv_t3_min_, recv_t3_max_, recv_t3_tot_); + } + +#endif /* __APPNIC_C_PROFILE__ */ + + /* TEMP */ + spin_unlock( & adapter->extra_lock ); + /* that's all */ + return; + +} + +/* + =============================================================================== + lsinet_rx_packets +*/ + +static int +lsinet_rx_packets( struct net_device * device, int max ) +{ + appnic_device_t * adapter = netdev_priv( device ); + appnic_queue_pointer_t queue; + int updated_head_pointer = 0; + int packets = 0; + + queue.raw = adapter->rx_tail_copy.raw; + + /* Receive Packets */ + + while( 0 < queue_initialized_( SWAB_QUEUE_POINTER( adapter->rx_tail ), + queue, adapter->rx_num_desc ) ) { + appnic_dma_descriptor_t descriptor; + + readdescriptor( ( ( unsigned long ) adapter->rx_desc + + queue.bits.offset ), + & descriptor ); + + if( 0 != descriptor.end_of_packet ) { +#ifdef __APPNIC_C_PROFILE__ + ++ packets_handled_; +#endif /* __APPNIC_C_PROFILE__ */ + LSINET_COUNTS_INC( LSINET_COUNTS_RX_PKT ); + lsinet_rx_packet( device ); + ++ packets; + queue.raw = adapter->rx_tail_copy.raw; + + if( -1 != max ) { + if( packets == max ) { + break; + } + } + } else { + queue_increment_( & queue, adapter->rx_num_desc ); + } + } + + /* Update the Head Pointer */ + + while( 1 < queue_uninitialized_( adapter->rx_head, adapter->rx_tail_copy, + adapter->rx_num_desc ) ) { + + appnic_dma_descriptor_t descriptor; + + readdescriptor( ( ( unsigned long ) adapter->rx_desc + + adapter->rx_head.bits.offset ), & descriptor ); + descriptor.data_transfer_length = adapter->rx_buf_per_desc; + descriptor.write = 1; + descriptor.pdu_length = 0; + descriptor.start_of_packet = 0; + descriptor.end_of_packet = 0; + descriptor.interrupt_on_completion = 1; + writedescriptor( ( ( unsigned long ) adapter->rx_desc + + adapter->rx_head.bits.offset ), + & descriptor ); + queue_increment_( & adapter->rx_head, adapter->rx_num_desc ); + updated_head_pointer = 1; + } + + if( 0 != updated_head_pointer ) { + write_mac_( adapter->rx_head.raw, APPNIC_DMA_RX_HEAD_POINTER ); + } + + return packets; +} + +#ifdef LSINET_NAPI + +/* + =============================================================================== + lsinet_poll +*/ + +static int +lsinet_poll( struct napi_struct * napi, int budget ) +{ + appnic_device_t * adapter = container_of( napi, appnic_device_t, napi ); + struct net_device * device = adapter->device; + appnic_queue_pointer_t queue_; + + int cur_budget = budget; + int done; + unsigned long dma_interrupt_status_; +#ifdef __APPNIC_C_PROFILE__ + unsigned long packets_handled_ = 0; + unsigned long beginning_; + unsigned long end_; + + beginning_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); +#endif /* __APPNIC_C_PROFILE__ */ + + LSINET_COUNTS_INC( LSINET_COUNTS_POL_START ); + /* TEMP DEBUG: should be interruptible */ + /*down( & adapter->poll_sem);*/ + + TRACE_BEGINNING( ); + DEBUG_PRINT( "head=0x%x tail=0x%x tail_copy=0x%x\n", + adapter->rx_head.raw, adapter->rx_tail->raw, + adapter->rx_tail_copy.raw ); + queue_.raw = adapter->rx_tail_copy.raw; + +#if 0 + if (cur_budget > device->quota) { + cur_budget = device->quota; + } +#endif + + done = 1; + + do { + + /* Acknowledge the RX interrupt. */ + write_mac_( ~APPNIC_DMA_INTERRUPT_ENABLE_RECEIVE , + APPNIC_DMA_INTERRUPT_STATUS ); + + if( 0 == ( cur_budget -= lsinet_rx_packets( device, cur_budget ) ) ) { + break; + } + + dma_interrupt_status_ = read_mac_( APPNIC_DMA_INTERRUPT_STATUS ); + + } while ( (RX_INTERRUPT (dma_interrupt_status_)) && cur_budget ); + + +#if 0 + device->quota -= packets_handled_; +#endif + + if (done) { + LSINET_COUNTS_INC( LSINET_COUNTS_POL_RNBL ); + napi_complete( napi ); + /* re-enable receive interrupts */ + write_mac_( ( APPNIC_DMA_INTERRUPT_ENABLE_RECEIVE | + APPNIC_DMA_INTERRUPT_ENABLE_TRANSMIT ), + APPNIC_DMA_INTERRUPT_ENABLE ); + } + + DEBUG_PRINT( "head=0x%x tail=0x%x tail_copy=0x%x\n", + adapter->rx_head.raw, adapter->rx_tail->raw, + adapter->rx_tail_copy.raw ); + TRACE_ENDING( ); + +#ifdef __APPNIC_C_PROFILE__ + end_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); + app3xx_profile_time_calc(beginning_, end_, + time_in_rx_min_, time_in_rx_max_, total_rx_time_); + + + total_rx_packets_handled_ += packets_handled_; + if( packets_handled_ > max_rx_packets_handled_ ) { + max_rx_packets_handled_ = packets_handled_; + } + ++ total_polls_; +#endif /* __APPNIC_C_PROFILE__ */ + + /* TEMP */ + /*up( & adapter->poll_sem);*/ + LSINET_COUNTS_INC( LSINET_COUNTS_POL_DONE ); + return (done ? 0 : 1); + +} + +#else /* Not using NAPI, define the Rx interrupt handler instead */ + +/* + ---------------------------------------------------------------------- + handle_receive_interrupt_ +*/ + +static void handle_receive_interrupt_( struct net_device * device ) { + + appnic_device_t * dev_ = netdev_priv( device ); + appnic_queue_pointer_t queue_; + +#ifdef __APPNIC_C_PROFILE__ + unsigned long beginning_; + unsigned long end_; + unsigned long packets_handled_ = 0; + + beginning_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); +#endif /* __APPNIC_C_PROFILE__ */ + + LSINET_COUNTS_INC( LSINET_COUNTS_RX_START ); + TRACE_BEGINNING( ); + DEBUG_PRINT( "head=0x%lx tail=0x%lx tail_copy=0x%lx\n", + dev_->rx_head.raw, dev_->rx_tail->raw, + dev_->rx_tail_copy.raw ); + queue_.raw = dev_->rx_tail_copy.raw; + lsinet_rx_packets( device, -1 ); + DEBUG_PRINT( "head=0x%lx tail=0x%lx tail_copy=0x%lx\n", + dev_->rx_head.raw, dev_->rx_tail->raw, + dev_->rx_tail_copy.raw ); + TRACE_ENDING( ); + LSINET_COUNTS_INC( LSINET_COUNTS_RX_DONE ); +#ifdef __APPNIC_C_PROFILE__ + end_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); + app3xx_profile_time_calc(beginning_, end_, + time_in_rx_min_, time_in_rx_max_, total_rx_time_); + + + total_rx_packets_handled_ += packets_handled_; + if( packets_handled_ > max_rx_packets_handled_ ) { + max_rx_packets_handled_ = packets_handled_; + } + ++ total_rx_interrupts_; +#endif /* __APPNIC_C_PROFILE__ */ + + return; + +} +#endif /* else not NAPI */ + +/* + ---------------------------------------------------------------------- + appnic_isr_ +*/ + +static irqreturn_t appnic_isr_( int irq, void * device_id ) { + + struct net_device * device_ = ( struct net_device * ) device_id; + appnic_device_t * dev_ = netdev_priv( device_ ); + unsigned long dma_interrupt_status_; + unsigned long flags; + +#ifdef __APPNIC_C_PROFILE__ + unsigned beginning_jiffies_ = jiffies; +#endif /* __APPNIC_C_PROFILE__ */ + + TRACE_BEGINNING( ); + LSINET_COUNTS_INC( LSINET_COUNTS_ISR_START ); + + /* acquire the lock */ + spin_lock_irqsave( & dev_->lock, flags ); + +#if ! defined( PHYLESS ) && ! defined( CONFIG_ACP ) + if( INT_MAC_RX == irq ) { + + PHY_DEBUG_PRINT( "Handling PHY interrupt.\n" ); + + if( BCM5221_PHY_ == phy_type_ ) { + + bc_phy_interrupt_t bc_phy_interrupt_; + + ( void ) phy_read_( phy_address_, + BC_PHY_INTERRUPT_, & bc_phy_interrupt_.raw ); + bc_phy_interrupt_.raw = 0; + bc_phy_interrupt_.bits.enable = 1; + ( void ) phy_write_( phy_address_, + BC_PHY_INTERRUPT_, bc_phy_interrupt_.raw ); + + } else if( MICREL_PHY_ == phy_type_ ) { + + m_phy_interrupt_t m_phy_interrupt_; + + ( void ) phy_read_( phy_address_, + M_PHY_INTERRUPT_, & m_phy_interrupt_.raw ); + ( void ) phy_write_( phy_address_, + M_PHY_INTERRUPT_, m_phy_interrupt_.raw ); + + } + + write_mac_( 0, APPNIC_RX_INTERRUPT_STATUS ); + enable_( device_ ); + + } else { +#endif /* PHYLESS */ + /* get the status */ + dma_interrupt_status_ = read_mac_( APPNIC_DMA_INTERRUPT_STATUS ); +#ifdef LSINET_NAPI + /* NAPI - don't ack RX interrupt */ + write_mac_( APPNIC_DMA_INTERRUPT_ENABLE_RECEIVE, APPNIC_DMA_INTERRUPT_STATUS ); +#else + write_mac_( 0, APPNIC_DMA_INTERRUPT_STATUS ); +#endif + + /*TRACER_POST( "dma_interrupt_status_=0x%x", dma_interrupt_status_ );*/ + + /* handle interrupts */ + + if( TX_INTERRUPT( dma_interrupt_status_ ) ) { + LSINET_COUNTS_INC( LSINET_COUNTS_ISR_TX ); + /* transmition complete */ + ++ transmit_interrupts_; + handle_transmit_interrupt_( device_ ); + } + + if( RX_INTERRUPT( dma_interrupt_status_ ) ) { + LSINET_COUNTS_INC( LSINET_COUNTS_ISR_RX ); +#ifdef LSINET_NAPI + ++ receive_interrupts_; + if (napi_schedule_prep(&dev_->napi)) { + /* disable RX interrupts and tell the system we've got work */ + write_mac_( APPNIC_DMA_INTERRUPT_ENABLE_TRANSMIT , + APPNIC_DMA_INTERRUPT_ENABLE ); + __napi_schedule(&dev_->napi); + } else { + ERROR_PRINT( "NAPI bug! interrupt while in poll\n"); + write_mac_( APPNIC_DMA_INTERRUPT_ENABLE_TRANSMIT , + APPNIC_DMA_INTERRUPT_ENABLE ); + } +#else + /* receive complete */ + handle_receive_interrupt_( device_ ); +#endif + } +#if ! defined( PHYLESS ) && ! defined( CONFIG_ACP ) + } +#endif /* PHYLESS */ + + /* release the lock */ + spin_unlock_irqrestore( & dev_->lock, flags ); + + LSINET_COUNTS_INC( LSINET_COUNTS_ISR_DONE ); + TRACE_ENDING( ); + +#ifdef __APPNIC_C_PROFILE__ + if( jiffies != beginning_jiffies_ ) { + ++ jiffies_changed_; + } +#endif /* __APPNIC_C_PROFILE__ */ + + return IRQ_HANDLED; + +} + +/* + ---------------------------------------------------------------------- + appnic_open + + Opens the interface. The interface is opened whenever ifconfig + activates it. The open method should register any system resource + it needs (I/O ports, IRQ, DMA, etc.) turn on the hardware, and + increment the module usage count. +*/ + +int appnic_open( struct net_device * device ) { + + int return_code_ = 0; +#if defined( CONFIG_ARCH_APP3 ) + unsigned long gpio_mux_ = readl( APP3XX_HB_CONF_BASE + 0x18 ); +#elif defined( CONFIG_ARCH_APP3K ) + /*unsigned long gpio_mux_ = readl( APP_AEI_BASE + 0x18 );*/ +#endif + + /* enable the receiver and transmitter */ + if( 0 != enable_( device ) ) { + + ERROR_PRINT( "Unable to enable the interface.\n" ); + disable_( ); + return -EBUSY; + + } + +#ifdef LSINET_NAPI + { + appnic_device_t * adapter = netdev_priv( device ); + napi_enable( & adapter->napi ); + } +#endif /* LSINET_NAPI */ + + /* install the interrupt handlers */ + if( 0 != ( return_code_ = request_irq( device->irq, appnic_isr_, IRQF_DISABLED, + APPNIC_NAME, device ) ) ) { + + ERROR_PRINT( "request_irq( ) failed, returned 0x%x/%d\n", + return_code_, return_code_ ); + return return_code_; + + } + + /* enable interrupts */ + write_mac_( ( APPNIC_DMA_INTERRUPT_ENABLE_RECEIVE | + APPNIC_DMA_INTERRUPT_ENABLE_TRANSMIT ), + APPNIC_DMA_INTERRUPT_ENABLE ); + + { + +#ifndef PHYLESS + char phy_string_ [ 256 ]; + int use_interrupts_ = 1; + appnic_device_t * dev_ = netdev_priv( device ); +#endif + +#ifdef CONFIG_ARCH_APP3 + + PHY_DEBUG_PRINT( "phy_type_=0x%x gpio_mux_=0x%x\n", phy_type_, gpio_mux_ ); + + if( ( BCM5221_PHY_ != phy_type_ ) || + ( 0x04000000 != ( gpio_mux_ & 0x04000000 ) ) ) { + + use_interrupts_ = 0; + + } + +#endif + +#ifndef PHYLESS + +#ifndef CONFIG_ACP + + if( ( 0 != ubootenv_get( "phy_mode", phy_string_ ) ) || + ( 0 == strncmp( phy_string_, "poll", strlen( "poll" ) ) ) ) { + + use_interrupts_ = 0; + + } + + PHY_DEBUG_PRINT( "use_interrupts_=%d\n", use_interrupts_ ); + + if( 1 == use_interrupts_ ) { + + if( BCM5221_PHY_ == phy_type_ ) { + + bc_phy_interrupt_t bc_phy_interrupt_; + + bc_phy_interrupt_.raw = 0; + bc_phy_interrupt_.bits.enable = 1; + + if( 0 != phy_write_( phy_address_, BC_PHY_INTERRUPT_, + bc_phy_interrupt_.raw ) ) { + + return -EBUSY; + + } + + if( 0 != phy_read_( phy_address_, BC_PHY_INTERRUPT_, + & bc_phy_interrupt_.raw ) ) { + + return -EBUSY; + + } + + } else if( MICREL_PHY_ == phy_type_ ) { + + m_phy_interrupt_t m_phy_interrupt_; + + m_phy_interrupt_.raw = 0; + m_phy_interrupt_.bits.enable_link_up = 1; + + if( 0 != phy_write_( phy_address_, M_PHY_INTERRUPT_, + m_phy_interrupt_.raw ) ) { + + return -EBUSY; + + } + + } + + if( 0 != ( return_code_ = + request_irq( INT_MAC_RX, appnic_isr_, 0, + APPNIC_NAME "(phy)", device ) ) ) { + + ERROR_PRINT( "request_irq( ) failed, returned 0x%x/%d\n", + return_code_, return_code_ ); + return return_code_; + + } + + write_mac_( ( APPNIC_RX_EXTERNAL_INTERRUPT_CONTROL_MAC_0 ), + APPNIC_RX_EXTERNAL_INTERRUPT_CONTROL ); + dev_->polling = 0; + + } else { + +#endif + +#ifndef CONFIG_ACP + WARN_PRINT( "PHY is in polling mode.\n" ); +#endif + init_timer( & appnic_timer_ ); + appnic_timer_.expires = jiffies + ( APPNIC_TIMER_PERIOD * HZ ); + appnic_timer_.data = ( unsigned long ) device; + appnic_timer_.function = appnic_timer_handler_; + add_timer( & appnic_timer_ ); + dev_->polling = 1; + +#ifndef CONFIG_ACP + + } + +#endif + +#endif /* PHYLESS */ + + } + + /* let the OS know we are ready to send packets */ + netif_start_queue( device ); + + /* that's all */ + return 0; + +} + +/* + ---------------------------------------------------------------------- + appnic_stop + + Stops the interface. The interface is stopped when it is broughht + down; operations performed at open time should be reversed. +*/ + +int appnic_stop( struct net_device * device ) { + + int return_code_ = 0; + + DEBUG_PRINT( "Stopping the interface.\n" ); + + /* + Indicate to the OS that no more packets should be sent. + */ + + netif_stop_queue( device ); + + /* + Stop the receiver and transmitter. + */ + + disable_( ); + + /* Disable NAPI. */ +#ifdef LSINET_NAPI + { + appnic_device_t * adapter = netdev_priv( device ); + napi_disable( & adapter->napi ); + } +#endif + + /* + Free the interrupts. + */ + + free_irq( device->irq, device ); + +#ifndef PHYLESS + + { +#ifndef CONFIG_ACP + appnic_device_t * dev_ = netdev_priv( device ); + if( 0 != dev_->polling ) { del_timer( & appnic_timer_ ); } + else { free_irq( INT_MAC_RX, device ); } +#else + del_timer( & appnic_timer_ ); +#endif + } + +#endif /* PHYLESS */ + + /* + That's all. + */ + + return return_code_; + +} + +/* + ---------------------------------------------------------------------- + appnic_hard_start_xmit + + The method initiates the transmission of a packet. The full packet + (protocol headers and all) is contained in a socket buffer (sk_buff) + structure. + + ----- NOTES ----- + + 1) This will not get called again by the kernel until it returns. +*/ + +int +appnic_hard_start_xmit( struct sk_buff * skb, + struct net_device * device ) +{ + appnic_device_t * adapter = netdev_priv( device ); + int length_; + int buf_per_desc_; + +#ifdef __APPNIC_C_PROFILE__ + unsigned long beginning_; + unsigned long end_; + unsigned long this_time_; + + beginning_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); + ++ total_tx_packets_; +#endif /* __APPNIC_C_PROFILE__ */ + + LSINET_COUNTS_INC( LSINET_COUNTS_HST_START ); + appnic_special_lock( & adapter->lock ); + length_ = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + buf_per_desc_ = adapter->tx_buf_sz / adapter->tx_num_desc; + + /* + If enough transmit descriptors are available, copy and transmit. + */ + + DEBUG_PRINT( "length_=%d buf_per_desc_=%d tx_tail=0x%x\n", + length_, buf_per_desc_, swab32( adapter->tx_tail->raw ) ); + +#if 0 + if( ( ( length_ / buf_per_desc_ ) + 1 ) >= + queue_uninitialized_( adapter->tx_head, SWAB_QUEUE_POINTER( adapter->tx_tail ), + adapter->tx_num_desc ) ) { + LSINET_COUNTS_INC( LSINET_COUNTS_HST_RCLM ); + handle_transmit_interrupt_( device ); + } +#else + /*ZZZ*/ + while( ( ( length_ / buf_per_desc_ ) + 1 ) >= + queue_uninitialized_( adapter->tx_head, + SWAB_QUEUE_POINTER( adapter->tx_tail ), + adapter->tx_num_desc ) ) { + udelay( 1000 ); + LSINET_COUNTS_INC( LSINET_COUNTS_HST_RCLM ); + handle_transmit_interrupt_( device ); + } +#endif + + if( ( ( length_ / buf_per_desc_ ) + 1 ) < + queue_uninitialized_( adapter->tx_head, SWAB_QUEUE_POINTER( adapter->tx_tail ), + adapter->tx_num_desc ) ) { + int bytes_copied_ = 0; + appnic_dma_descriptor_t descriptor; + + LSINET_COUNTS_INC( LSINET_COUNTS_HST_SNDG ); + readdescriptor( ( ( unsigned long ) adapter->tx_desc + + adapter->tx_head.bits.offset ), & descriptor ); + descriptor.start_of_packet = 1; + + while( bytes_copied_ < length_ ) { + descriptor.write = 1; + descriptor.pdu_length = length_; + + if( ( length_ - bytes_copied_ ) > buf_per_desc_ ) { + memcpy( ( void * ) ( descriptor.host_data_memory_pointer + + adapter->dma_alloc_offset ), + ( void * ) ( ( unsigned long ) skb->data + bytes_copied_ ), + buf_per_desc_ ); + descriptor.data_transfer_length = buf_per_desc_; + descriptor.end_of_packet = 0; + descriptor.interrupt_on_completion = 0; + bytes_copied_ += buf_per_desc_; + } else { + memcpy( ( void * ) ( descriptor.host_data_memory_pointer + + adapter->dma_alloc_offset ), + ( void * ) ( ( unsigned long ) skb->data + bytes_copied_ ), + ( length_ - bytes_copied_ ) ); + descriptor.data_transfer_length = ( length_ - bytes_copied_ ); + descriptor.end_of_packet = 1; +#ifdef DISABLE_TX_INTERRUPTS + descriptor.interrupt_on_completion = 0; +#else /* DISABLE_TX_INTERRUPTS */ + descriptor.interrupt_on_completion = 1; +#endif /* DISABLE_TX_INTERRUPTS */ + bytes_copied_ = length_; + } + + adapter->stats.tx_bytes += bytes_copied_; + writedescriptor( ( ( unsigned long ) adapter->tx_desc + + adapter->tx_head.bits.offset ), & descriptor ); + queue_increment_( & adapter->tx_head, adapter->tx_num_desc ); + readdescriptor( ( ( unsigned long ) adapter->tx_desc + + adapter->tx_head.bits.offset ), & descriptor ); + descriptor.start_of_packet = 0; + } + + write_mac_( adapter->tx_head.raw, APPNIC_DMA_TX_HEAD_POINTER ); + device->trans_start = jiffies; + LSINET_COUNTS_INC( LSINET_COUNTS_HST_SNT ); + } else { + ++ out_of_tx_descriptors_; + LSINET_COUNTS_INC( LSINET_COUNTS_HST_OOD ); + ERROR_PRINT( "No transmit descriptors available!\n" ); + } + + /* free the socket buffer */ + dev_kfree_skb( skb ); + appnic_special_unlock( & adapter->lock ); + +#ifdef __APPNIC_C_PROFILE__ + end_ = ( 0xffffffff - readl( ( TIMER7_BASE + TIMER_n_VALUE ) ) ); + if( end_ > beginning_ ) { + this_time_ = end_ - beginning_; + } else { + this_time_ = end_ + ( 0xffffffff - beginning_ ) + 1; + } + total_tx_time_ += this_time_; + if( this_time_ > time_in_tx_max_ ) { time_in_tx_max_ = this_time_; } + if( this_time_ < time_in_tx_min_ ) { time_in_tx_min_ = this_time_; } +#endif /* __APPNIC_C_PROFILE__ */ + + LSINET_COUNTS_INC( LSINET_COUNTS_HST_DONE ); + return 0; + +} + +/* + ---------------------------------------------------------------------- + appnic_tx_timeout + + This method is called when a packet transmission fails to complete + within a resonable period, on the assumption that an interrupt has + been missed or the interface has locked up. It should handle the + problem and resume packet transmission. +*/ + +void appnic_tx_timeout( struct net_device * device ) { + + appnic_device_t * adapter = netdev_priv( device ); + + WARN_PRINT( "Transmission timed out!\n" ); + + if( 0 == queue_initialized_( SWAB_QUEUE_POINTER( adapter->tx_tail ), + adapter->tx_tail_copy, adapter->tx_num_desc ) ) { + /* + If tx_tail is still the same as tx_tail_copy + then restart the transmission. + */ + + write_mac_( adapter->tx_head.raw, APPNIC_DMA_TX_HEAD_POINTER ); + } else { + /* If tx_tail has moved on, just increment tx_tail_copy. */ + appnic_dma_descriptor_t descriptor; + + readdescriptor( ( ( unsigned long ) adapter->tx_desc + + adapter->tx_tail_copy.bits.offset ), & descriptor ); + adapter->stats.tx_bytes += descriptor.pdu_length; + kfree( ( void * ) descriptor.host_data_memory_pointer ); + queue_increment_( & adapter->tx_tail_copy, adapter->tx_num_desc ); + } + + return; + +} + +/* + ---------------------------------------------------------------------- + appnic_net_device_stats + + Whenever an application needs to get statistics for the interface, + this method is called. This happens, for example, when ifconfig or + nstat -i is run. +*/ + +struct net_device_stats * +appnic_get_stats( struct net_device * device ) +{ + + appnic_device_t * device_ = netdev_priv( device ); + + /* + Update the statistics structure. + */ + + get_hw_statistics_( device_ ); + + /* + That's all. + */ + + return & device_->stats; + +} + +/* + ---------------------------------------------------------------------- + appnic_do_ioctl +*/ + +#if 0 + +static int +appnic_do_ioctl( struct net_device * device, struct ifreq * request, + int command ) +{ + + int return_code_ = 0; +#ifndef PHYLESS + u16 * data_ = ( u16 * ) & ( request->ifr_data ); +#endif + + switch( command ) { + /* Get the speed. */ + case 0x8946: + break; +#ifndef PHYLESS + /* Get the PHY (defined in 2.5.x kernels) */ + case 0x89f0: + data_ [ 0 ] = phy_address_; + break; + /* Read PHY (defined in 2.5.x kernels) */ + case 0x89f1: + if( 0 != phy_read_( data_ [ 0 ], data_ [ 1 ], + & ( data_ [ 3 ] ) ) ) { + return_code_ = -EIO; + } + break; + /* Write PHY (defined in 2.5.x kernels) */ + case 0x89f2: + if( 0 != phy_write_( data_ [ 0 ], data_ [ 1 ], data_ [ 2 ] ) ) { + return_code_ = -EIO; + } + break; +#endif + default: + ERROR_PRINT( "Unknown Command: 0x%x\n", command ); + break; + } + + return return_code_; + +} + +#endif + +/* + ---------------------------------------------------------------------- + appnic_set_mac_address +*/ + +static int +appnic_set_mac_address(struct net_device *device, void *data) { + struct sockaddr *address_ = data; + unsigned long swap_source_address_; + + if (netif_running(device)) + return -EBUSY; + + DEBUG_PRINT("Setting MAC to %02x:%02x:%02x:%02x:%02x:%02x\n", + address_->sa_data [0], address_->sa_data [1], + address_->sa_data [2], address_->sa_data [3], + address_->sa_data [4], address_->sa_data [5]); + memcpy(device->dev_addr, address_->sa_data, 6); + memcpy(device->perm_addr, address_->sa_data, 6); + + swap_source_address_ = + ((address_->sa_data[4]) << 8) | address_->sa_data[5]; + write_mac_(swap_source_address_, APPNIC_SWAP_SOURCE_ADDRESS_2); + swap_source_address_ = + ((address_->sa_data[2]) << 8) | address_->sa_data[3]; + write_mac_(swap_source_address_, APPNIC_SWAP_SOURCE_ADDRESS_1); + swap_source_address_ = + ((address_->sa_data[0]) << 8) | address_->sa_data[1]; + write_mac_(swap_source_address_, APPNIC_SWAP_SOURCE_ADDRESS_0); + memcpy(device->dev_addr, address_->sa_data, device->addr_len); + + return 0; +} + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + ETHTOOL Operations + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + appnic_get_settings +*/ + +static int +appnic_get_settings( struct net_device * device, struct ethtool_cmd * command ) +{ + appnic_device_t * appnic_device_ = netdev_priv( device ); + + memset( command, 0, sizeof( struct ethtool_cmd ) ); + + /* What the hardware supports. */ + command->supported = + ( SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full ); + + /* Acquire the device lock. */ + appnic_special_lock( & appnic_device_->lock ); + +#ifndef PHYLESS + + /* What is currently advertised. */ + + { + + unsigned short ad_value_; + + if( 0 != phy_read_( phy_address_, PHY_AUTONEG_ADVERTISE, & ad_value_ ) ) { + + ERROR_PRINT( "PHY read failed!" ); + appnic_special_unlock( & appnic_device_->lock ); + return -EIO; + + } + + switch( ad_value_ ) { + + case 0x1e1: + command->advertising = + ( ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half | + ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half ); + break; + + case 0xe1: + command->advertising = + ( ADVERTISED_100baseT_Half | + ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half ); + break; + + case 0x61: + command->advertising = + ( ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half ); + break; + + case 0x41: + command->advertising = + ( ADVERTISED_10baseT_Half ); + break; + + default: + break; + + } + + } + + /* The current speed. */ + + { + + int speed_; + + if( -1 == ( speed_ = phy_speed_( phy_address_ ) ) ) { + + ERROR_PRINT( "PHY read failed!" ); + appnic_special_unlock( & appnic_device_->lock ); + return -EIO; + + } + + if( 1 == speed_ ) { + + command->speed = SPEED_100; + + } else { + + command->speed = SPEED_10; + + } + + } + + /* Is the current link duplex? */ + + { + + int duplex_; + + if( -1 == ( duplex_ = phy_duplex_( phy_address_ ) ) ) { + + ERROR_PRINT( "PHY read failed!" ); + appnic_special_unlock( & appnic_device_->lock ); + return -EIO; + + } + + if( 1 == duplex_ ) { + + command->duplex = DUPLEX_FULL; + + } else { + + command->duplex = DUPLEX_HALF; + + } + + } + +#endif /* PHYLESS */ + + /* Is autoneg enabled? */ + command->autoneg = AUTONEG_ENABLE; + + /* Unlock and return success. */ + appnic_special_unlock( & appnic_device_->lock ); + + return 0; + +} + +/* + Fill in the struture... +*/ + +static const struct ethtool_ops appnic_ethtool_ops = { + .get_settings = appnic_get_settings +}; + + +/* + ====================================================================== + ====================================================================== + ====================================================================== + + Linux Module Interface. + + ====================================================================== + ====================================================================== + ====================================================================== +*/ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29) +static const struct net_device_ops appnic_netdev_ops = { + .ndo_open = appnic_open, + .ndo_stop = appnic_stop, + .ndo_get_stats = appnic_get_stats, + .ndo_set_mac_address = appnic_set_mac_address, + .ndo_start_xmit = appnic_hard_start_xmit, +}; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29) */ + +/* + ---------------------------------------------------------------------- + appnic_init +*/ + +int +appnic_init( struct net_device * device ) +{ + + appnic_device_t * adapter = netdev_priv( device ); + + TRACE_BEGINNING( ); + + /* + Reset the MAC + */ + + write_mac_( 0x80000000, APPNIC_DMA_PCI_CONTROL ); + + /* + -- WORKAROUND -- WORKAROUND -- WORKAROUND -- WORKAROUND -- WORKAROUND -- + This is the software work around for defect 15129. Use 64 byte + buffers for receive descriptors for all dma. + -- WORKAROUND -- WORKAROUND -- WORKAROUND -- WORKAROUND -- WORKAROUND -- + */ +#ifndef CONFIG_ACP + if( 1 >= ( APP3XX_REVISION_REGISTER & 0x1f ) ) { + + printk( "++ Using work around for defect 15129\n" ); + rx_num_desc = ( 8 * DESCRIPTOR_GRANULARITY ); + rx_buf_sz = 32768; + + } +#endif + + /* + Allocate memory and initialize the descriptors + */ + + { + + void * dma_offset_; + + /* + fixup num_[rt]x_desc + */ + + if( 0 != ( rx_num_desc % DESCRIPTOR_GRANULARITY ) ) { + + WARN_PRINT( "rx_num_desc was not a multiple of %d.\n", + DESCRIPTOR_GRANULARITY ); + rx_num_desc += + DESCRIPTOR_GRANULARITY - ( rx_num_desc % DESCRIPTOR_GRANULARITY ); + + } + + adapter->rx_num_desc = rx_num_desc; + + if( 0 != ( tx_num_desc % DESCRIPTOR_GRANULARITY ) ) { + + WARN_PRINT( "tx_num_desc was not a multiple of %d.\n", + DESCRIPTOR_GRANULARITY ); + tx_num_desc += + DESCRIPTOR_GRANULARITY - ( tx_num_desc % DESCRIPTOR_GRANULARITY ); + + } + + adapter->tx_num_desc = tx_num_desc; + + DEBUG_PRINT( "rx_num_desc=%d tx_num_desc=%d\n", rx_num_desc, tx_num_desc ); + + /* + Fix up [rt]x_buf_sz. Must be some multiple of 64 bytes per descriptor. + */ + + if( 0 != ( rx_buf_sz % ( BUFFER_ALIGNMENT * + rx_num_desc ) ) ) { + + WARN_PRINT( "rx_buf_sz was not a multiple of %d.\n", + ( BUFFER_ALIGNMENT * rx_num_desc ) ); + rx_buf_sz += + ( BUFFER_ALIGNMENT * rx_num_desc ) - + ( rx_buf_sz % ( BUFFER_ALIGNMENT * + rx_num_desc ) ); + + } + + adapter->rx_buf_sz = rx_buf_sz; + + if( 0 != ( tx_buf_sz % ( BUFFER_ALIGNMENT * + tx_num_desc ) ) ) { + + WARN_PRINT( "tx_buf_sz was not a multiple of %d.\n", + ( BUFFER_ALIGNMENT * tx_num_desc ) ); + tx_buf_sz += + ( BUFFER_ALIGNMENT * tx_num_desc ) - + ( tx_buf_sz % ( BUFFER_ALIGNMENT * + tx_num_desc ) ); + + } + + adapter->tx_buf_sz = tx_buf_sz; + + DEBUG_PRINT( "rx_buf_sz=%d tx_buf_sz=%d\n", + rx_buf_sz, tx_buf_sz ); + + /* + Allocate dma-able memory + */ + + adapter->dma_alloc_size = + /* The tail pointers (rx and tx) */ + ( sizeof( appnic_queue_pointer_t ) * 2 ) + + /* The RX descriptor ring (and padding to allow + 64 byte alignment) */ + ( sizeof( appnic_dma_descriptor_t ) * + adapter->rx_num_desc ) + + ( DESCRIPTOR_GRANULARITY ) + + /* The TX descriptor ring (and padding...) */ + ( sizeof( appnic_dma_descriptor_t ) * + adapter->tx_num_desc ) + + ( DESCRIPTOR_GRANULARITY ) + + /* The RX buffer (and padding...) */ + ( adapter->rx_buf_sz ) + ( BUFFER_ALIGNMENT ) + + /* The TX buffer (and padding...) */ + ( adapter->tx_buf_sz ) + ( BUFFER_ALIGNMENT ); + +#ifdef DMA_CACHABLE + + if( ( void * ) 0 == + ( adapter->dma_alloc = ( void * ) + kmalloc( adapter->dma_alloc_size, GFP_KERNEL ) ) ) { + + ERROR_PRINT( "Could not allocate %d bytes of " + "DMA-able memory!\n", + adapter->dma_alloc_size ); + kfree( adapter ); + TRACE_ENDING( ); + return -ENOMEM; + + } + + adapter->dma_alloc_dma = virt_to_phys( adapter->dma_alloc ); + +#else + + /* This needs to be set to something sane for dma_alloc_coherent() */ + device->dev.archdata.dma_ops = &dma_direct_ops; + + if( ( void * ) 0 == + ( adapter->dma_alloc = ( void * ) + dma_direct_alloc_coherent( &device->dev, adapter->dma_alloc_size, + & adapter->dma_alloc_dma, + GFP_KERNEL ) ) ) { + + ERROR_PRINT( "Could not allocate %d bytes of " + "DMA-able memory!\n", + adapter->dma_alloc_size ); + kfree( adapter ); + TRACE_ENDING( ); + return -ENOMEM; + + } + +#endif + + adapter->dma_alloc_offset = + ( int ) adapter->dma_alloc - ( int ) adapter->dma_alloc_dma; + dma_offset_ = adapter->dma_alloc; + DEBUG_PRINT( "Allocated %d bytes at 0x%08lx(0x%08lx), " + "offset=0x%x.\n", + adapter->dma_alloc_size, + ( unsigned long ) adapter->dma_alloc, + ( unsigned long ) adapter->dma_alloc_dma, + adapter->dma_alloc_offset ); + printk( "Allocated %d bytes at 0x%08lx(0x%08lx), " + "offset=0x%x.\n", + adapter->dma_alloc_size, + ( unsigned long ) adapter->dma_alloc, + ( unsigned long ) adapter->dma_alloc_dma, + adapter->dma_alloc_offset ); + + /* + Initialize the tail pointers + */ + + adapter->rx_tail = ( appnic_queue_pointer_t * ) dma_offset_; + adapter->rx_tail_dma = + ( int ) adapter->rx_tail - ( int ) adapter->dma_alloc_offset; + dma_offset_ += sizeof( appnic_queue_pointer_t ); + memset( ( void * ) adapter->rx_tail, 0, + sizeof( appnic_queue_pointer_t ) ); + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + + adapter->tx_tail = ( appnic_queue_pointer_t * ) dma_offset_; + adapter->tx_tail_dma = + ( int ) adapter->tx_tail - ( int ) adapter->dma_alloc_offset; + dma_offset_ += sizeof( appnic_queue_pointer_t ); + memset( ( void * ) adapter->tx_tail, 0, + sizeof( appnic_queue_pointer_t ) ); + DEBUG_PRINT( "tx_tail=0x%08lx\n", + ( unsigned long ) adapter->tx_tail ); + + /* + Initialize the descriptor pointers + */ + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + adapter->rx_desc = ( appnic_dma_descriptor_t * ) + ALIGN64B( dma_offset_ ); + DEBUG_PRINT( "rx_desc=0x%08lx\n", + ( unsigned long ) adapter->rx_desc ); + adapter->rx_desc_dma = + ( int ) adapter->rx_desc - ( int ) adapter->dma_alloc_offset; + dma_offset_ += ( sizeof( appnic_dma_descriptor_t ) * + adapter->rx_num_desc ) + + ( DESCRIPTOR_GRANULARITY ); + memset( ( void * ) adapter->rx_desc, 0, + ( sizeof( appnic_dma_descriptor_t ) * + adapter->rx_num_desc ) ); + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + adapter->tx_desc = ( appnic_dma_descriptor_t * ) + ALIGN64B( dma_offset_ ); + DEBUG_PRINT( "tx_desc=0x%08lx\n", + ( unsigned long ) adapter->tx_desc ); + adapter->tx_desc_dma = + ( int ) adapter->tx_desc - ( int ) adapter->dma_alloc_offset; + dma_offset_ += ( sizeof( appnic_dma_descriptor_t ) * + adapter->tx_num_desc ) + + ( DESCRIPTOR_GRANULARITY ); + memset( ( void * ) adapter->tx_desc, 0, + ( sizeof( appnic_dma_descriptor_t ) * + adapter->tx_num_desc ) ); + + /* + Initialize the buffer pointers + */ + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + DEBUG_PRINT( "Initializing the RX buffer pointers, dma_offset=0x%lx/0x%lx\n", + ( unsigned long ) dma_offset_, + ( unsigned long ) ALIGN64B( dma_offset_ ) ); + adapter->rx_buf = ( void * ) ALIGN64B( dma_offset_ ); + adapter->rx_buf_dma = + ( int ) adapter->rx_buf - ( int ) adapter->dma_alloc_offset; + adapter->rx_buf_per_desc = adapter->rx_buf_sz / adapter->rx_num_desc; + + dma_offset_ += ( adapter->rx_buf_sz ) + ( BUFFER_ALIGNMENT ); + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + DEBUG_PRINT( "Initializing the TX buffer pointers, dma_offset=0x%lx/0x%lx\n", + ( unsigned long ) dma_offset_, + ( unsigned long ) ALIGN64B( dma_offset_ ) ); + adapter->tx_buf = ( void * ) ALIGN64B( dma_offset_ ); + adapter->tx_buf_dma = + ( int ) adapter->tx_buf - ( int ) adapter->dma_alloc_offset; + adapter->tx_buf_per_desc = adapter->tx_buf_sz / adapter->tx_num_desc; + dma_offset_ += ( adapter->tx_buf_sz ) + ( BUFFER_ALIGNMENT ); + + /* + Initialize the descriptors + */ + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + { + + int index_; + unsigned long buf_ = + ( unsigned long ) adapter->rx_buf_dma; + appnic_dma_descriptor_t descriptor; + + DEBUG_PRINT( "Initializing the RX descriptors at 0x%lx\n", buf_ ); + + for( index_ = 0; index_ < adapter->rx_num_desc; ++ index_ ) { + memset( ( void * ) & descriptor, 0, sizeof( appnic_dma_descriptor_t ) ); + descriptor.write = 1; + descriptor.interrupt_on_completion = 1; + descriptor.host_data_memory_pointer = buf_; + descriptor.data_transfer_length = adapter->rx_buf_per_desc; + writedescriptor( ( ( unsigned long ) adapter->rx_desc + + ( index_ * sizeof( appnic_dma_descriptor_t ) ) ), + & descriptor ); + buf_ += adapter->rx_buf_per_desc; + } + + buf_ = ( unsigned long ) adapter->tx_buf_dma; + DEBUG_PRINT( "Initializing the RX descriptors at 0x%lx\n", buf_ ); + + for( index_ = 0; + index_ < adapter->tx_num_desc; ++ index_ ) { + memset( ( void * ) & descriptor, 0, sizeof( appnic_dma_descriptor_t ) ); + descriptor.write = 1; + descriptor.interrupt_on_completion = 1; + descriptor.host_data_memory_pointer = buf_; + writedescriptor( ( ( unsigned long ) adapter->tx_desc + + ( index_ * sizeof( appnic_dma_descriptor_t ) ) ), + & descriptor ); + buf_ += adapter->tx_buf_per_desc; + } + } + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + DEBUG_PRINT( "Initializing spin locks and semaphores.\n" ); + + /* + Initialize the spin lock. + */ + + spin_lock_init( & adapter->lock ); + spin_lock_init( & adapter->extra_lock ); + + /* + * TEMP: Initialize the semaphores + */ + mutex_init( & adapter->rx_sem); + mutex_init( & adapter->tx_sem); + mutex_init( & adapter->poll_sem); + + } + + /* + Take MAC out of reset + */ + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + DEBUG_PRINT( "Enabling the MAC" ); + write_mac_( 0x0, APPNIC_RX_SOFT_RESET ); + write_mac_( 0x1, APPNIC_RX_MODE ); + write_mac_( 0x0, APPNIC_TX_SOFT_RESET ); + write_mac_( 0x1, APPNIC_TX_MODE ); + if( is_asic( ) ) { + write_mac_( 0x300a, APPNIC_TX_WATERMARK ); + } else { + write_mac_( 0xc00096, APPNIC_TX_WATERMARK ); + } + write_mac_( 0x1, APPNIC_TX_HALF_DUPLEX_CONF ); + write_mac_( 0xffff, APPNIC_TX_TIME_VALUE_CONF ); + write_mac_( 0x1, APPNIC_TX_INTERRUPT_CONTROL ); + write_mac_( 0x5275, APPNIC_TX_EXTENDED_CONF ); + write_mac_( 0x1, APPNIC_RX_INTERNAL_INTERRUPT_CONTROL ); + write_mac_( 0x1, APPNIC_RX_EXTERNAL_INTERRUPT_CONTROL ); + write_mac_( 0x40010000, APPNIC_DMA_PCI_CONTROL ); + write_mac_( 0x30000, APPNIC_DMA_CONTROL ); + writeio( 0x280044, dma_base + 0x60 ); + writeio( 0xc0, dma_base + 0x64 ); + + /* + Set the MAC address. + */ + + { + struct sockaddr address; + + memcpy(&(address.sa_data[0]), device->dev_addr, 6); + appnic_set_mac_address(device, &address); + } + + /* + Initialize the queue pointers. + */ + + DEBUG_PRINT( "rx_tail=0x%08lx\n", + ( unsigned long ) adapter->rx_tail ); + { + + /* + Receiver + */ + + memset( ( void * ) & adapter->rx_tail_copy, + 0, sizeof( appnic_queue_pointer_t ) ); + memset( ( void * ) & adapter->rx_head, + 0, sizeof( appnic_queue_pointer_t ) ); + + write_mac_( adapter->rx_desc_dma, + APPNIC_DMA_RX_QUEUE_BASE_ADDRESS ); + write_mac_( ( adapter->rx_num_desc * + sizeof( appnic_dma_descriptor_t ) ) / 1024, + APPNIC_DMA_RX_QUEUE_SIZE ); + /* indicate that all of the receive descriptors are ready */ + adapter->rx_head.bits.offset = + ( adapter->rx_num_desc - 1 ) * + sizeof( appnic_dma_descriptor_t ); + write_mac_( adapter->rx_tail_dma, + APPNIC_DMA_RX_TAIL_POINTER_ADDRESS ); + + /* + N.B. + + The boot loader may have used the NIC. If so, the + tail pointer must be read and the head pointer (and + local copy of the tail) based on it. + */ + + DEBUG_PRINT( "Initializing the RX tail: adapter=0x%lx\n", + ( unsigned long ) adapter ); + DEBUG_PRINT( "Initializing the RX tail: adapter->rx_tail=0x%lx\n", + ( unsigned long ) adapter->rx_tail ); + DEBUG_PRINT( "Initializing the RX tail: adapter->rx_tail->raw=0x%lx\n", + ( unsigned long ) adapter->rx_tail->raw ); + adapter->rx_tail->raw = + read_mac_( APPNIC_DMA_RX_TAIL_POINTER_LOCAL_COPY ); + adapter->rx_tail_copy.raw = adapter->rx_tail->raw; + adapter->rx_head.raw = adapter->rx_tail->raw; + queue_decrement_( & adapter->rx_head, adapter->rx_num_desc ); + adapter->rx_head.bits.generation_bit = + ( 0 == adapter->rx_head.bits.generation_bit ) ? 1 : 0; + write_mac_( adapter->rx_head.raw, APPNIC_DMA_RX_HEAD_POINTER ); + + /* + Transmitter + */ + + memset( ( void * ) & adapter->tx_tail_copy, + 0, sizeof( appnic_queue_pointer_t ) ); + memset( ( void * ) & adapter->tx_head, + 0, sizeof( appnic_queue_pointer_t ) ); + + write_mac_( adapter->tx_desc_dma, + APPNIC_DMA_TX_QUEUE_BASE_ADDRESS ); + write_mac_( ( adapter->tx_num_desc * + sizeof( appnic_dma_descriptor_t ) ) / 1024, + APPNIC_DMA_TX_QUEUE_SIZE ); + DEBUG_PRINT( "Writing 0x%lx to APPNIC_DMA_TX_TAIL_POINTER_ADDRESS\n", + ( unsigned long ) adapter->tx_tail_dma ); + write_mac_( adapter->tx_tail_dma, + APPNIC_DMA_TX_TAIL_POINTER_ADDRESS ); + + /* + N.B. + + The boot loader may have used the NIC. If so, the + tail pointer must be read and the head pointer (and + local copy of the tail) based on it. + */ + + DEBUG_PRINT( "Initializing the TX tail pointer at 0x%lx/0x%lx.\n", + ( unsigned long ) adapter->tx_tail, + ( unsigned long ) adapter->tx_tail->raw ); + adapter->tx_tail->raw = + read_mac_( APPNIC_DMA_TX_TAIL_POINTER_LOCAL_COPY ); + adapter->tx_tail_copy.raw = adapter->tx_tail->raw; + adapter->tx_head.raw = adapter->tx_tail->raw; + write_mac_( adapter->tx_head.raw, APPNIC_DMA_TX_HEAD_POINTER ); + + } + + /* clear statistics */ + + { + + appnic_device_t * device_ = netdev_priv( device ); + clear_statistics_( device_ ); + + } + + /* initialize the PHY */ + +#ifndef PHYLESS + + if( 0 != phy_enable_( phy_address_ ) ) { + + WARN_PRINT( "Failed to initialize the PHY!\n" ); + + } + +#endif /* PHYLESS */ + + /* fill in the net_device structure */ + + DEBUG_PRINT( "Filling in the device structure.\n" ); + ether_setup( device ); + +#ifdef CONFIG_ACP + if( NO_IRQ == + ( device->irq = irq_create_mapping( NULL, adapter->interrupt ) ) ) { + ERROR_PRINT( "irq_create_mapping( ) failed\n" ); + return -EBUSY; + } + + if( 0 != irq_set_irq_type( device->irq, IRQ_TYPE_LEVEL_HIGH ) ) { + ERROR_PRINT( "set_irq_type( ) failed\n" ); + return -EBUSY; + } +#else + device->irq = INT_MAC_DMA; +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) + device->open = appnic_open; + device->stop = appnic_stop; + device->hard_start_xmit = appnic_hard_start_xmit; + device->tx_timeout = appnic_tx_timeout; + device->get_stats = appnic_get_stats; + device->do_ioctl = appnic_do_ioctl; + device->watchdog_timeo = tx_timeout; + device->set_mac_address = appnic_set_mac_address; +#else + device->netdev_ops = & appnic_netdev_ops; +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) */ + SET_ETHTOOL_OPS( device, & appnic_ethtool_ops ); +#ifdef LSINET_NAPI + memset( ( void * ) & adapter->napi, 0, sizeof( struct napi_struct ) ); + netif_napi_add( device, & adapter->napi, lsinet_poll, LSINET_NAPI_WEIGHT ); + adapter->device = device; + printk( "%s:%d - lsinet_poll=0x%lx\n", + __FILE__, __LINE__, ( unsigned long ) lsinet_poll ); +#endif + + /* that's all */ + TRACE_ENDING( ); + return 0; + +} + +/* + ---------------------------------------------------------------------- + appnic_read_proc_ +*/ + +static int +appnic_read_proc_( char * page, char * * start, off_t offset, + int count, int * eof, void * data ) +{ + + int length_; + +#ifdef __APPNIC_C_PROFILE__ + + struct net_device *net_device_ = this_net_device; + appnic_device_t * appnic_device_ = + ( appnic_device_t * ) net_device_->priv; + unsigned long divisor_; + unsigned long tx_tpa_real_; + unsigned long tx_tpa_virt_; + + divisor_ = get_core_speed( ) / 1000000; + +#if 1 + + if( appnic_device_->tx_tail_dma != + read_mac_( APPNIC_DMA_TX_TAIL_POINTER_ADDRESS ) ) { + + ERROR_PRINT( "Real Address Doesn't Match Configuration! " \ + "0x%x 0x%x\n", + appnic_device_->tx_tail_dma, + read_mac_( APPNIC_DMA_TX_TAIL_POINTER_ADDRESS ) ); + + } + + tx_tpa_real_ = appnic_device_->tx_tail_dma; + tx_tpa_virt_ = appnic_device_->tx_tail->raw; + + length_ = sprintf( page, + " GKM TEMP DEBUG Build 5\n" \ + " RX: head=0x%lx tail=0x%lx tail_copy=0x%lx\n" \ + " TX: head=0x%lx tail=0x%lx tail_copy=0x%lx\n" \ + "DMA: IE=0x%x IS=0x%x\n" \ + "VIC: status=0x%x raw=0x%x enable=0x%x\n" \ + " TX: tpa_config=0x%x tpa_real_=0x%lx " \ + "*tpa_virt_=0x%x\n", + appnic_device_->rx_head.raw, + appnic_device_->rx_tail->raw, + appnic_device_->rx_tail_copy.raw, + appnic_device_->tx_head.raw, + appnic_device_->tx_tail->raw, + appnic_device_->tx_tail_copy.raw, + read_mac_( APPNIC_DMA_INTERRUPT_ENABLE ), + read_mac_( APPNIC_DMA_INTERRUPT_STATUS ), + readl( ( APP3XX_VIC_BASE + VICIRQSTATUS ) ), + readl( ( APP3XX_VIC_BASE + VICRAWINTR ) ), + readl( ( APP3XX_VIC_BASE + VICINTENABLE ) ), + read_mac_( APPNIC_DMA_TX_TAIL_POINTER_ADDRESS ), + tx_tpa_real_, + * ( ( unsigned int * ) tx_tpa_virt_ ) ); + + +#else + + length_ = sprintf( page, + +#ifdef LSINET_NAPI + + "-- appnic.c\n" \ + "-- rx_num_desc = %d\n" \ + "-- rx_buf_sz = %d\n" \ + "-- rx_buf_per_desc = %d\n" \ + "-- tx_num_desc = %d\n" \ + "-- tx_buf_sz = %d\n" \ + "-- tx_buf_per_desc = %d\n" \ + "-- dropped_by_stack_ = %lu\n" \ + "-- transmit_interrupts_ = %lu\n" \ + "-- receive_interrupts_ = %lu\n" \ + "-- total_polls_ = %lu\n" \ + "-- jiffies_changed_ = %lu\n" \ + "-- out_of_tx_descriptors_ = %lu\n" \ + "-- divisor_ = %lu\n" \ + "-- RX(ns): min=%lu max=%lu avg/pkt=%llu " + "avg/poll=%llu\n" \ + "-- Max RX Packets Handled/poll: %lu\n" \ + "-- RX Size: min=%lu max=%lu total=%lu " + "average=%lu\n" \ + "-- TX(ns): min=%lu max=%lu avg/pkt=%llu\n" \ + "-- total_tx_packets_: %lu\n" \ + "-- recv t1: min=%lu max=%lu, avg=%llu\n" \ + "-- recv t2: min=%lu max=%lu, avg=%llu\n" \ + "-- recv t3: min=%lu max=%lu, avg=%llu\n", + +#else + + "-- appnic.c\n" \ + "-- rx_num_desc = %d\n" \ + "-- rx_buf_sz = %d\n" \ + "-- rx_buf_per_desc = %d\n" \ + "-- tx_num_desc = %d\n" \ + "-- tx_buf_sz = %d\n" \ + "-- tx_buf_per_desc = %d\n" \ + "-- dropped_by_stack_ = %lu\n" \ + "-- transmit_interrupts_ = %lu\n" \ + "-- total_rx_interrupts_ = %lu\n" \ + "-- jiffies_changed_ = %lu\n" \ + "-- out_of_tx_descriptors_ = %lu\n" \ + "-- divisor_ = %lu\n" \ + "-- RX(ns): min=%lu max=%lu avg/pkt=%llu " + "avg/irq=%llu\n" \ + "-- Max RX Packets Handled/Interrupt: %lu\n" \ + "-- RX Size: min=%lu max=%lu total=%lu " + "average=%lu\n" \ + "-- TX(ns): min=%lu max=%lu avg/pkt=%llu\n" \ + "-- total_tx_packets_: %lu\n" \ + "-- recv t1: min=%lu max=%lu, avg=%llu\n" \ + "-- recv t2: min=%lu max=%lu, avg=%llu\n" \ + "-- recv t3: min=%lu max=%lu, avg=%llu\n", + +#endif + + appnic_device_->rx_num_desc, + appnic_device_->rx_buf_sz, + appnic_device_->rx_buf_per_desc, + appnic_device_->tx_num_desc, + appnic_device_->tx_buf_sz, + appnic_device_->tx_buf_per_desc, + dropped_by_stack_, + transmit_interrupts_, + +#ifdef LSINET_NAPI + + receive_interrupts_, + total_polls_, + +#else + + total_rx_interrupts_, + +#endif + + jiffies_changed_, + out_of_tx_descriptors_, + divisor_, + profile_time_fmt(time_in_rx_min_,divisor_), + profile_time_fmt(time_in_rx_max_,divisor_), + total_rx_packets_handled_ ? + (profile_avg_fmt(total_rx_time_, + total_rx_packets_handled_, + divisor_)) : 0, + +#ifdef LSINET_NAPI + + total_polls_ ? + (profile_avg_fmt(total_rx_time_, + total_polls_, + divisor_)) : 0, + +#else + + total_rx_interrupts_ ? + (profile_avg_fmt(total_rx_time_, + total_rx_interrupts_, + divisor_)) : 0, + +#endif + + max_rx_packets_handled_, + rx_packet_size_min_, rx_packet_size_max_, + total_rx_bytes_, + total_rx_packets_handled_ ? + ( total_rx_bytes_ / total_rx_packets_handled_ ) : + 0, + profile_time_fmt(time_in_tx_min_,divisor_), + profile_time_fmt(time_in_tx_max_,divisor_), + total_tx_packets_ ? + (profile_avg_fmt(total_tx_time_, + total_tx_packets_, + divisor_)) : 0, + total_tx_packets_, + profile_time_fmt(recv_t1_min_,divisor_), + profile_time_fmt(recv_t1_max_,divisor_), + total_rx_packets_handled_ ? + ( total_rx_packets_sent_up_ ? + (profile_avg_fmt(recv_t1_tot_, + total_rx_packets_handled_, + divisor_)) : 0 ) : 0, + profile_time_fmt(recv_t2_min_,divisor_), + profile_time_fmt(recv_t2_max_,divisor_), + total_rx_packets_sent_up_ ? + (profile_avg_fmt(recv_t2_tot_, + total_rx_packets_sent_up_, + divisor_)) : 0, + profile_time_fmt(recv_t3_min_,divisor_), + profile_time_fmt(recv_t3_max_,divisor_), + total_rx_packets_sent_up_ ? + (profile_avg_fmt(recv_t3_tot_, + total_rx_packets_sent_up_, + divisor_)) : 0); + +#endif + + time_in_rx_max_ = 0; + time_in_rx_min_ = 0xffffffff; + rx_packet_size_max_ = 0; + rx_packet_size_min_ = 0xffffffff; + total_rx_bytes_ = 0; + total_rx_packets_handled_ = 1; + total_rx_time_ = 0; + max_rx_packets_handled_ = 0; + total_rx_interrupts_ = 0; + +#ifdef LSINET_NAPI + + receive_interrupts_ = 0; + total_polls_ = 0; + +#endif + + time_in_tx_max_ = 0; + time_in_tx_min_ = 0xffffffff; + total_tx_time_ = 0; + total_tx_packets_ = 1; + jiffies_changed_ = 0; + recv_t1_min_ = 0xffffffff; + recv_t2_min_ = 0xffffffff; + recv_t3_min_ = 0xffffffff; + recv_t1_max_ = 0; + recv_t2_max_ = 0; + recv_t3_max_ = 0; + recv_t1_tot_ = 0; + recv_t2_tot_ = 0; + recv_t3_tot_ = 0; + total_rx_packets_sent_up_ = 1; + +#else + + length_ = sprintf( page, "-- appnic.c -- Profiling is disabled\n" ); + +#endif + + /* that's all */ + return length_; + +} + +/* + ---------------------------------------------------------------------- + lsinet_init +*/ + +int +lsinet_init(void) +{ + int rc = 0; + struct net_device *device; + struct device_node *np = NULL; + const u32 *field; + appnic_device_t *appnic_device; + + TRACE_BEGINNING(); + + /* Allocate space for the device. */ + if ((struct net_device *)0 == + (device = alloc_etherdev(sizeof(appnic_device_t)))) { + ERROR_PRINT( "Couldn't allocate net device." ); + rc = -ENOMEM; + goto out; + } + + this_net_device = device; /* For /proc/reads. */ + appnic_device = (appnic_device_t *)netdev_priv(device); + + /* + Get the physical addresses, interrupt number, etc. from the + device tree. If no entry exists (older boot loader...) just + use the pre-devicetree method. + */ + + np = of_find_node_by_type(np, "network"); + + while (np && !of_device_is_compatible(np, "acp-femac")) + np = of_find_node_by_type(np, "network"); + + if (np) { + u64 value64; + u32 value32; + int length; + + field = of_get_property(np, "enabled", NULL); + + if (!field || (field && (0 == *field))) { + ERROR_PRINT("Not Enabled\n"); + rc = -EINVAL; + goto out; + } + + field = of_get_property(np, "reg", NULL); + + if (!field) { + ERROR_PRINT("Couldn't get \"reg\" property.\n"); + rc = -EINVAL; + goto out; + } + + value64 = of_translate_address(np, field); + value32 = field[1]; + field += 2; + rx_base = ioremap(value64, value32); + appnic_device->rx_base = rx_base; + value64 = of_translate_address(np, field); + value32 = field[1]; + field += 2; + tx_base = ioremap(value64, value32); + appnic_device->tx_base = tx_base; + value64 = of_translate_address(np, field); + value32 = field[1]; + field += 2; + dma_base = ioremap(value64, value32); + appnic_device->dma_base = dma_base; + + field = of_get_property(np, "interrupts", NULL); + + if (field) + appnic_device->interrupt = field[0]; + else + goto device_tree_failed; + + field = of_get_property(np, "mdio-clock", NULL); + + if (!field) { + goto device_tree_failed; + } else { + appnic_device->mdio_clock = field[0]; + } + + field = of_get_property(np, "phy-address", NULL); + + if (!field) { + goto device_tree_failed; + } else { + appnic_device->phy_address = field[0]; + } + + field = of_get_property(np, "ad-value", NULL); + + if (!field) { + goto device_tree_failed; + } else { + appnic_device->ad_value = field[0]; + } + + field = of_get_property(np, "mac-address", &length); + + if (!field || 6 != length) { + goto device_tree_failed; + } else { + int i; + u8 *value; + + value = (u8 *)field; + + for (i = 0; i < 6; ++i) { + /*printk("value[%d] = 0x%2x\n", i, value[i]);*/ + appnic_device->mac_addr[i] = value[i]; + } + } + + memcpy(device->dev_addr, &appnic_device->mac_addr[0], 6); + memcpy(device->perm_addr, &appnic_device->mac_addr[0], 6); + + goto device_tree_succeeded; + + device_tree_failed: + ERROR_PRINT("Reading Device Tree Failed\n"); + iounmap(rx_base); + iounmap(tx_base); + iounmap(dma_base); + rc = -EINVAL; + goto out; + + } else { + unsigned char ethaddr_string[20]; + + if (0 != ubootenv_get("ethaddr", ethaddr_string)) { + ERROR_PRINT("Could not read ethernet address!\n"); + return -EBUSY; + } else { + char *string; + int i = 0; + u8 mac_address[6]; + + string = ethaddr_string; + + while ((0 != string) && (6 > i)) { + char *value; + + value = strsep(&string, ":"); + mac_address[i++] = + simple_strtoul(value, NULL, 16); + } + + memcpy(device->dev_addr, mac_address, 6); + memcpy(device->perm_addr, mac_address, 6); + device->addr_len = 6; + } + + printk("LSI FEMAC: Using Static Addresses and Interrupts.\n"); + rx_base = ioremap(0x002000480000ULL, 0x1000); + appnic_device->rx_base = ioremap(0x002000480000ULL, 0x1000); + tx_base = ioremap(0x002000481000ULL, 0x1000); + appnic_device->tx_base = ioremap(0x002000481000ULL, 0x1000); + dma_base = ioremap(0x002000482000ULL, 0x1000); + appnic_device->dma_base = ioremap(0x002000482000ULL, 0x1000); + appnic_device->interrupt = 33; + } + + device_tree_succeeded: + +#ifdef __APPNIC_C_PROFILE__ + writel( 0xffffffff, ( TIMER7_BASE + TIMER_n_LOAD ) ); + writel( 0xffffffff, ( TIMER7_BASE + TIMER_n_VALUE ) ); + writel( ( TIMER_n_CONTROL_ENABLE | + TIMER_n_CONTROL_MODE | + TIMER_n_CONTROL_SIZE ), + ( TIMER7_BASE + TIMER_n_CONTROL ) ); +#endif /* __APPNIC_C_PROFILE__ */ + + /* Initialize the device. */ + + if( 0 != ( rc = appnic_init( device ) ) ) { + ERROR_PRINT( "appnic_init( ) failed: %d\n", rc ); + rc = -ENODEV; + goto out; + } + + strcpy(this_net_device->name, "eth%d"); + + /* Register the device. */ + + if (0 != (rc = register_netdev(this_net_device))) { + ERROR_PRINT("register_netdev() failed: %d\n", rc); + rc = -ENODEV; + goto out; + } + + /* Create the /proc entry. */ + create_proc_read_entry( "driver/appnic", 0, NULL, + appnic_read_proc_, NULL ); + + out: + TRACE_ENDING( ); + return rc; +} + +module_init(lsinet_init); + +/* + ---------------------------------------------------------------------- + lsinet_exit +*/ + +void __exit +lsinet_exit(void) +{ + TRACE_BEGINNING(); + remove_proc_entry("driver/appnic", NULL); + unregister_netdev(this_net_device); + TRACE_ENDING(); + + return; +} + +module_exit(lsinet_exit); diff --git a/drivers/lsi/acp/pci_plx.c b/drivers/lsi/acp/pci_plx.c new file mode 100644 index 0000000..1a5179e --- /dev/null +++ b/drivers/lsi/acp/pci_plx.c @@ -0,0 +1,795 @@ +/* + * drivers/lsi/acp/pci_plx.c + * + * PCIe PLX controller Driver for LSI's ACP + * + * Copyright (C) 2009 LSI Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Mode PLX API uses to access device*/ +typedef enum _PLX_CHIP_FAMILY +{ + PLX_FAMILY_NONE = 0, + PLX_FAMILY_UNKNOWN, + PLX_FAMILY_BRIDGE_P2L, // 9000 series & 8311 + PLX_FAMILY_BRIDGE_PCI_P2P, // 6000 series + PLX_FAMILY_BRIDGE_PCIE_P2P, // 8111,8112,8114 + PLX_FAMILY_ALTAIR, // 8525,8533,8547,8548 + PLX_FAMILY_ALTAIR_XL, // 8505,8509 + PLX_FAMILY_VEGA, // 8516,8524,8532 + PLX_FAMILY_VEGA_LITE, // 8508,8512,8517,8518 + PLX_FAMILY_DENEB, // 8612,8616,8624,8632,8647,8648 + PLX_FAMILY_SIRIUS, // 8604,8606,8608,8609,8613,8614,8615,8617,8618,8619 + PLX_FAMILY_CYGNUS, // 8625,8636,8649,8664,8680,8696 + PLX_FAMILY_SCOUT, // 8700 + PLX_FAMILY_DRACO_1, // 8408,8416,8712,8716,8724,8732,8747,8748 + PLX_FAMILY_DRACO_2, // 8713,8717,8725,8733,8749 + PLX_FAMILY_MIRA, + PLX_FAMILY_CAPELLA +} PLX_CHIP_FAMILY; + + +// simple version number +#define _template_SOFTWARE_VERSION_NUMBER 1.0 + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) /* not < 2.5 */ +# error "This kernel is too old: not supported by this file" +#endif + +static int i_foo; + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("LSI Corp"); +MODULE_DESCRIPTION("PLX PCIE device driver"); +module_param(i_foo, int, 0444); // Module parameter, unused +MODULE_PARM_DESC(i_foo, "foo frequency"); // unused + +// vendor and device id of the PCI device +#define VENDOR_ID 0x10B5 // vendor id: buggy Kolter card: official 0x1001 but real 0x0001 +#define DEVICE_ID 0x8608 // device id of the Proto-3 card + +// for first and second i/o region (pci memory): +static unsigned long ioport=0L, iolen=0L, memstart=0L, memlen=0L; +static int i_template_major = 231; +static int Uboot_PLX = 1; + + +#define RtlZeroMemory(pDest, count) memset((pDest), 0, (count)) +#define RtlCopyMemory(pDest, pSrc, count) memcpy((pDest), (pSrc), (count)) + + +#define PLX_BUS_READ32_ENDIAN(endian, addr) \ + in_##endian##32((volatile u32 __iomem *) (addr)) + +#define PLX_BUS_READ32_LE(addr) PLX_BUS_READ32_ENDIAN(le, addr) + +#define PLX_BUS_READ32_BE(addr) PLX_BUS_READ32_ENDIAN(be, addr) + + +#define PLX_BUS_WRITE32_ENDIAN(endian, addr, data) \ + do { \ + u32 * __a__ = (u32 *) addr; \ + u32 __d__ = data; \ + out_##endian##32((volatile u32 __iomem *) __a__, __d__); \ + } while (0); + + +#define PLX_BUS_WRITE32_LE(addr, data) PLX_BUS_WRITE32_ENDIAN(le, addr, data) + +#define PLX_BUS_WRITE32_BE(addr, data) PLX_BUS_WRITE32_ENDIAN(be, addr, data) +#if 1 +// Macros for PLX chip register access +#define PLX_8000_REG_READ(addr) PLX_BUS_READ32_LE(addr) + + +#define PLX_8000_REG_WRITE(addr, data) PLX_BUS_WRITE32_LE(addr, data) +#endif + + +// not really necessary; for future use +MODULE_DEVICE_TABLE(pci, pci_drv_ids); + +static struct +pci_device_id pci_drv_ids[] __devinitdata = +{ + // { VENDOR_ID, DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { PCI_DEVICE(VENDOR_ID, DEVICE_ID), }, + { 0, } +}; + +// PCI BAR Properties +typedef struct _PLX_PCI_BAR_PROP +{ + u32 BarValue; // Actual value in BAR + u64 Physical; // BAR Physical Address + u64 Size; // Size of BAR space + int bIoSpace; // Memory or I/O space? + int bPrefetchable; // Is space pre-fetchable? + int b64bit; // Is PCI BAR 64-bit? +} PLX_PCI_BAR_PROP; + +// PCI BAR Space information +typedef struct _PLX_PCI_BAR_INFO +{ + u32 pVa; // BAR Kernel Virtual Address + PLX_PCI_BAR_PROP Properties; // BAR Properties + int bResourceClaimed; // Was driver able to claim region? +} PLX_PCI_BAR_INFO; + +// PCI Device Key Identifier +typedef struct _PLX_DEVICE_KEY +{ + u32 IsValidTag; // Magic number to determine validity + u8 bus; // Physical device location + u8 slot; + u8 function; + u16 VendorId; // Device Identifier + u16 DeviceId; + u16 SubVendorId; + u16 SubDeviceId; + u8 Revision; + u16 PlxChip; // PLX chip type + u8 PlxRevision; // PLX chip revision + u8 PlxFamily; // PLX chip family + u8 ApiIndex; // Used internally by the API + u8 DeviceNumber; // Used internally by device drivers + u8 ApiMode; // Mode API uses to access device + u8 PlxPort; // PLX port number of device + u8 NTPortType; // If NT port, stores NT port type + u8 NTPortNum; // If NT port exists, store NT port number + u32 ApiInternal[2]; // Reserved for internal PLX API use + u8 *pRegVa; // Virtual address to registers + u32 Offset_RegBase; // The NT register base offset + u32 UpstreamBarSize; // For virtual-side, size of upsteam BAR 0 space + PLX_PCI_BAR_INFO PciBar[6]; +} PLX_DEVICE_KEY; + +// Non-transparent Port types +typedef enum _PLX_NT_PORT_TYPE +{ + PLX_NT_PORT_NONE = 0, // Not an NT port + PLX_NT_PORT_PRIMARY = 1, // NT Primary Host side port + PLX_NT_PORT_SECONDARY = 2, // NT Seconday Host side port + PLX_NT_PORT_VIRTUAL = PLX_NT_PORT_PRIMARY, // NT Virtual-side port + PLX_NT_PORT_LINK = PLX_NT_PORT_SECONDARY, // NT Link-side port + PLX_NT_PORT_UNKOWN = 0xFF // NT side is undetermined +} PLX_NT_PORT_TYPE; + + + +// declarations for fops, pci_driver +static int _template_open (struct inode *, struct file *); +static int _template_close (struct inode *, struct file *); +static ssize_t _template_read (struct file *, char *, size_t, loff_t *); +static ssize_t _template_write (struct file *, __user const char *, size_t, loff_t *); +static int device_init(struct pci_dev *, const struct pci_device_id *); +static void device_deinit( struct pci_dev *); +static void device_deinit( struct pci_dev *); +static int __init pci_drv_init(void); +static void __exit pci_drv_exit(void); + +module_init(pci_drv_init); +module_exit(pci_drv_exit); + +static struct +pci_driver pci_drv_template = +{ + .name= "pci_drv_template", + .id_table= pci_drv_ids, + .probe= device_init, + .remove= device_deinit, +}; + +static struct file_operations _template_fops = +{ + .owner = THIS_MODULE, + .read = _template_read, + .write = _template_write, + .open = _template_open, + .release = _template_close, +}; + +// example for reading a PCI config byte +static unsigned char +get_revision(struct pci_dev *dev) +{ + u8 revision; + + pci_read_config_byte(dev, PCI_REVISION_ID, &revision); + return (revision); +} + + +#if 1 + +/******************************************************************************* + * + * Function : PlxRegisterRead + * + * Description: Reads a PLX-specific control register + * + ******************************************************************************/ +static u32 +PlxRegisterRead( + struct pci_dev *dev, + PLX_DEVICE_KEY *key, + u32 offset + ) +{ + u32 value; + u32 MaxOffset; + + + offset += key->Offset_RegBase; + + // Set max possible offset + MaxOffset = 4 * 1024; + + + MaxOffset += 0x11000; + + + // Verify register offset + if ((offset & 0x3) || (offset >= MaxOffset)) + { + printk("ERROR - Invalid register offset (%X)\n", offset); + + return 0; + } + + // Read value + value = in_le32(offset + key->PciBar[0].pVa); + + return value; +} + + + + +/******************************************************************************* + * + * Function : PlxRegisterWrite + * + * Description: Writes to a PLX-specific control register + * + ******************************************************************************/ +static int +PlxRegisterWrite( + struct pci_dev *dev, + PLX_DEVICE_KEY *key, + u32 offset, + u32 value + ) +{ + u32 MaxOffset; + + + // Adjust the offset for correct port + offset += key->Offset_RegBase; + + // Set max possible offset + MaxOffset = 4 * 1024; + + MaxOffset += 0x11000; + + // Verify register offset + if ((offset & 0x3) || (offset >= MaxOffset)) + { + printk("ERROR - Invalid register offset (%X)\n", offset); + return 1; + } + + printk("PlxRegisterWrite: key->PciBar[0].pVa = 0x%04x \n", key->PciBar[0].pVa ); + + // Write the value + out_le32(offset+ (u32)key->PciBar[0].pVa, value ); + + return 0; +} + + +/****************************************************************************** + * + * Function : PlxNtReqIdProbe + * + * Description: Implements a procedure to determine the Requester ID for NT accesses + * + *****************************************************************************/ +static int PlxNtReqIdProbe( + struct pci_dev *dev, + PLX_DEVICE_KEY *key, + u16 bReadTlp, + u16 *pReqId + ) +{ + u16 Offset_CapPcie; + u16 Offset_CapAer; + u32 RegValue; + u32 RegAerMask; + u32 RegPciCommand; + u32 RegPcieCapCsr; + u32 RegAerSeverity; + u32 WriteValue; + + + /********************************************************* + * This function attempts to detect the PCIe Requester ID + * of the Host CPU. The ReqID must be added to the NT + * ReqID LUT so that it accepts TLPs from that requester. + * + * On most systems, the ReqID for both reads & writes is + * the same. On many newer chipsets, the ReqID will be + * different between read & write TLPs. In general, the + * ReqID will be the Root Complex (0,0,0) and/or the + * upper-most parent root of the PLX switch, which will + * be a PCIe Root Port type device. + * + * The basic algorithm is listed below. The premise is to + * disable access to the PLX chip and issue a TLP, which + * should trigger an uncorrectable error and log the TLP. + * + * - Clear any PCIe & AER errors + * - Setup PLX device to generate AER errors (but mask PCIe msg) + * - Disable accesses to the PLX device + * - Issue a dummy memory read or write to a PLX register + * - Restore settings + * - Capture ReqID from the AER TLP header log + ********************************************************/ + + // Default to Req ID of 0 + *pReqId = 0; + + // Set default base offsets for PCIe & AER capabilities + Offset_CapPcie = 0x68; + Offset_CapAer = 0xFB4; + WriteValue = 0x12345678; + + // Get PCIe Device Status/Control & disable error reporting to host ([3:0]) + pci_read_config_dword( dev, (u16)(Offset_CapPcie + 0x8), &RegPcieCapCsr ); + /*printk("PlxNtReqIdProbe: RegPcieCapCsr = 0x%x, value = 0x%x \n", (u16)(Offset_CapPcie + 0x8), RegPcieCapCsr ); */ + RegPcieCapCsr |= (0xF << 16); // Clear any error status bits [19:16] + pci_write_config_dword( dev, (u16)(Offset_CapPcie + 0x8), RegPcieCapCsr & ~(0xF << 0) ); + + // Clear any AER UR errors [20] + pci_write_config_dword( dev, (u16)(Offset_CapAer + 0x4), (1 << 20) ); + + // Make sure AER UR error is not masked [20] + pci_read_config_dword( dev, (u16)(Offset_CapAer + 0x8), &RegAerMask ); +/*printk("PlxNtReqIdProbe: RegAerMask = 0x%x, value = 0x%x \n", (u16)(Offset_CapAer + 0x8), RegAerMask ); */ + if (RegAerMask & (1 << 20)) + pci_write_config_dword( dev, (u16)(Offset_CapAer + 0x8), RegAerMask & ~(1 << 20) ); + + // Set severity for UR errors ([20]). Must be Fatal for read TLPs or no AER logging + pci_read_config_dword( dev, (u16)(Offset_CapAer + 0xC), &RegAerSeverity ); +/*printk("PlxNtReqIdProbe: RegAerSeverity = 0x%x, value = 0x%x \n", (u16)(Offset_CapAer + 0xC), RegAerSeverity ); */ + if (bReadTlp == 1) + pci_write_config_dword( dev, (u16)(Offset_CapAer + 0xC), RegAerSeverity | (1 << 20) ); + else + pci_write_config_dword( dev, (u16)(Offset_CapAer + 0xC), RegAerSeverity & ~(1 << 20) ); + + // Disable PCI accesses [2:0] & SERR enable [8] in PCI command/status + pci_read_config_dword( dev, 0x04, &RegPciCommand ); +/*printk("PlxNtReqIdProbe: RegPciCommand = 0x04, value = 0x%x \n", RegPciCommand ); */ + RegPciCommand |= (0x1F << 27); // Clear any PCI error status ([31:27]) + pci_write_config_dword( dev, 0x04, (RegPciCommand & ~0x107) ); + + /********************************************************* + * Issue a TLP read or write to a PLX register + ********************************************************/ + if (bReadTlp==1) + PlxRegisterRead( dev, key,0); + else + PlxRegisterWrite( dev, key,0, WriteValue); + + // Restore PCI command/status + pci_write_config_dword( dev, 0x04, RegPciCommand ); + + // Verify an AER UR error was flagged + pci_read_config_dword( dev, (u16)(Offset_CapAer + 0x4), &RegValue ); +/*printk("PlxNtReqIdProbe: RegValue = 0x%x, value = 0x%x \n", (u16)(Offset_CapAer + 0x4), RegValue); */ + if ((RegValue & (1 << 20)) == 0) + { + printk("ERROR - ReqID probe failed, unable to capture error TLP\n"); + return 1; + } + + // Check if AER header is valid from First Error Pointer ([4:0]) + pci_read_config_dword( dev, (u16)(Offset_CapAer + 0x18), &RegValue ); +/*printk("PlxNtReqIdProbe: RegValue = 0x%x, value = 0x%x \n", (u16)(Offset_CapAer + 0x18), RegValue); */ + if ((RegValue & 0x1F) != 20) + { + printk( + "WARNING - Error Pointer reports bit %d not UR (20). Log may be invalid\n", + (RegValue & 0x1F)); + } + + // Get the AER logged TLP DWord 1, which contains Req ID + pci_read_config_dword( dev, (u16)(Offset_CapAer + 0x20), &RegValue ); +/*printk("PlxNtReqIdProbe: RegValue = 0x%x, value = 0x%x \n", (u16)(Offset_CapAer + 0x20), RegValue); */ + + // Clear UR status + pci_write_config_dword( dev, (u16)(Offset_CapAer + 0x4), (1 << 20) ); + + // Get Requester ID (DW1[31:16]) + *pReqId = (u16)(RegValue >> 16); + + printk( + "Probed %s ReqID = %04X [b:%02X s:%02X f:%X]\n", + (bReadTlp) ? "Read" : "Write", *pReqId, + (*pReqId >> 8), (*pReqId >> 3) & 0x1F, (*pReqId & 0x7) + ); + + return 0; +} +#endif + +static +irqreturn_t pci_isr( int irq, void *dev_id, struct pt_regs *regs ) +{ + // nothing todo for the irq yet + return (IRQ_HANDLED); +} + + +// Initialising of the module with output about the irq, I/O region and memory region. +static +int device_init(struct pci_dev *dev, const struct pci_device_id *id) +{ + int i_result;/*, i;*/ + u32 bar_w0; + unsigned *ncp_rsvd_ram = 0; + u8 revision; + PLX_DEVICE_KEY *plx_key; + u16 ReqId_Read; + u16 ReqId_Write; + + if(Uboot_PLX == 0) + return -ENODEV; + + // Allocate memory for the device object + plx_key = + kmalloc( + sizeof(PLX_DEVICE_KEY), + GFP_KERNEL + ); + + if (plx_key == NULL) + { + printk("ERROR - memory allocation for device object failed\n"); + return (-ENOMEM); + } + + // Initialize device object + RtlZeroMemory( + plx_key, + sizeof(PLX_DEVICE_KEY) + ); + + // Scan the system for supported devices + // Enable the device + if (pci_enable_device( dev ) == 0) + { + printk(("Enabled PCI device\n")); + } + else + { + printk("WARNING - PCI device enable failed\n"); + } + + // Enable bus mastering + pci_set_master( dev ); + + + plx_key->bus = dev->bus->number; + plx_key->slot = PCI_SLOT(dev->devfn); + plx_key->function = PCI_FUNC(dev->devfn); + plx_key->DeviceId = dev->device; + plx_key->VendorId = dev->vendor; + plx_key->SubVendorId = dev->subsystem_vendor; + plx_key->SubDeviceId = dev->subsystem_device; + plx_key->PlxFamily = PLX_FAMILY_SIRIUS; + plx_key->PlxChip = plx_key->DeviceId; + plx_key->pRegVa = NULL; + + plx_key->Offset_RegBase = 0x10000; + // Adjust offset for NT Link port + plx_key->NTPortType = PLX_NT_PORT_LINK; + plx_key->Offset_RegBase += 0x1000; + + + // Update Revision ID + pci_read_config_byte(dev, PCI_REVISION_ID, &revision); + + plx_key->Revision = (u8)(revision & 0xFF); + + printk( + "Device %04X_%04X = %04X rev %02X\n", + plx_key->DeviceId, plx_key->VendorId, + plx_key->PlxChip, plx_key->PlxRevision + ); + pci_read_config_dword(dev, 0x10, &bar_w0); + + bar_w0 &= ~(0xf); + +/* printk("pci_template: BAR 0 = 0x%08x\n", bar_w0);*/ + + if (0 == (ncp_rsvd_ram = ioremap(bar_w0, 0x20000))) + { + printk("ioremap the bar0 failed!\n"); + } + else + { + printk("ioremap the bar0 address 0x%08x to kernel VA =0x%p \n", bar_w0, ncp_rsvd_ram); + } + + plx_key->PciBar[0].pVa = (u32)ncp_rsvd_ram; + +#if 1 + /************************************************************* + * Determine Requester ID & add LUT entry + ************************************************************/ + printk("Probe for write ReqID : "); + + if (PlxNtReqIdProbe( + dev, + plx_key, + 0, // Probe for writes + &ReqId_Write + ) == 0) + { + printk("ERROR: Unable to probe ReqID\n"); + } + else + { + printk( + "Ok (ReqID=%04X [b:%02X s:%02X f:%01X])\n", + ReqId_Write, + (ReqId_Write >> 8) & 0xFF, + (ReqId_Write >> 3) & 0x1F, + (ReqId_Write >> 0) & 0x03 + ); + } + + printk("Probe for read ReqID : "); + + if (PlxNtReqIdProbe( + dev, + plx_key, + 1, // Probe for reads + &ReqId_Read + ) == 0) + { + printk("ERROR: Unable to probe ReqID\n"); + } + else + { + printk( + "Ok (ReqID=%04X [b:%02X s:%02X f:%01X])\n", + ReqId_Read, + (ReqId_Read >> 8) & 0xFF, + (ReqId_Read >> 3) & 0x1F, + (ReqId_Read >> 0) & 0x03 + ); + + + if (ReqId_Read == ReqId_Write) + { + printk("-- Read Req ID matches write, skip LUT add --\n"); + } + + } +#endif + +#if 0 + if (0 == (ncp_rsvd_ram = ioremap(0x2000000, 0x800000))) + { + printk("ioremap the DMA buffer failed!\n"); + } + else + { + printk("ioremap the DMA buffer address 0xf800000 to kernel VA =0x%p \n",ncp_rsvd_ram); + } + + for ( i = 0; i < 8; i++) + { + u8 achar = 0xaa; + memcpy( (u8 *)ncp_rsvd_ram, &achar, 1); + ncp_rsvd_ram++; + } +#endif + + i_result = get_revision (dev); // example usage to avoid the "defined but not used" message + // change the device name default (.. ...) to the module name + printk(KERN_ERR "pci_template: Old dev->dev.kobj.name: \"%s\"\n", dev->dev.kobj.name); + /*strncpy(dev->dev.kobj.name,"pci_drv_template",KOBJ_NAME_LEN);*/ + +#if 0 + // check irq number (don't request irq 0) before requesting + if ( (dev->irq) and (request_irq(dev->irq,pci_isr,SA_INTERRUPT|SA_SHIRQ,"pci_drv_template",dev)) ) + { + printk(KERN_ERR "pci_template: IRQ %d not free.\n", dev->irq ); + return -EIO; + } + if (dev->irq) + printk(KERN_ERR "pci_template: IRQ %d.\n", dev->irq); + else + printk(KERN_ERR "pci_template: No irq required/requested.\n"); +#endif + // get the first i/o region + ioport = pci_resource_start( dev, 0 ); + iolen = pci_resource_len( dev, 0 ); + // chech iolen before requesting the I/O region + if (iolen and ( NULL == request_region( ioport, iolen, dev->dev.kobj.name ) ) ) + { + printk(KERN_ERR "I/O address conflict for device \"%s\", ioport=%lu=0x%x, iolen=%lu=0x%x\n", + dev->dev.kobj.name, ioport, (unsigned int)ioport, iolen, (unsigned int)iolen); + goto cleanup_irq; + } + if (iolen) + printk(KERN_CRIT "pci_template: request_region( ioport=%lu=0x%x, iolen=%lu=0x%x, dev->dev.kobj.name=%s) successfull.\n", + ioport, (unsigned int)ioport, iolen, (unsigned int)iolen, dev->dev.kobj.name); + else + printk(KERN_CRIT "pci_template: request_region( ioport=%lu=0x%x, iolen=%lu=0x%x, dev->dev.kobj.name=%s) not necessary.\n", + ioport, (unsigned int)ioport, iolen, (unsigned int)iolen, dev->dev.kobj.name); + memstart = pci_resource_start( dev, 1 ); + memlen = pci_resource_len( dev, 1 ); + printk(KERN_CRIT "pci_template: memstart=%lu=0x%x, memlen=%lu=0x%x\n", memstart, (unsigned int)memstart, memlen, (unsigned int)memlen); + // check memlen before requesting the memory region + if (memlen and ( NULL == request_mem_region( memstart, memlen, dev->dev.kobj.name ) )) + { + printk(KERN_ERR "Memory address conflict for device \"%s\", request_mem_region( memstart=%lu=0x%x, memlen=%lu=0x%x, dev->dev.kobj.name=%s) failed.\n", + dev->dev.kobj.name, memstart, (unsigned int)memstart, memlen, (unsigned int)memlen, dev->dev.kobj.name); + goto cleanup_ports; + } + if (memlen) + printk(KERN_ERR "pci_template: request_mem_region( memstart=%lu=0x%x, memlen=%lu=0x%x, dev->dev.kobj.name=%s) successfull.\n", + memstart, (unsigned int)memstart, memlen, (unsigned int)memlen, dev->dev.kobj.name); + else + printk(KERN_ERR "pci_template: request_mem_region( memstart=%lu=0x%x, memlen=%lu=0x%x, dev->dev.kobj.name=%s) not necessary.\n", + memstart, (unsigned int)memstart, memlen, (unsigned int)memlen, dev->dev.kobj.name); + + kfree(plx_key) ; + return (0); + cleanup_ports: + if (iolen) + release_region( ioport, iolen ); + cleanup_irq: + if (dev->irq) + free_irq( dev->irq, dev ); + kfree(plx_key) ; + return (-EIO); +} + + +static void +device_deinit( struct pci_dev *pdev ) +{ + // device driver part + unregister_chrdev (i_template_major, "pci_chrdev_template"); + if (pdev->irq) + free_irq( pdev->irq, pdev ); + if( iolen ) + release_region( ioport, iolen ); + if( memlen ) + release_mem_region( memstart, memlen ); + return; +} + + +// device driver init +static +int __init pci_drv_init(void) +{ + int i_result=0; + struct device_node *np = NULL; + int *plx; + + np = of_find_node_by_type(np, "pci"); + + while (np && !of_device_is_compatible(np, "lsi,plb-pciex")) + np = of_find_node_by_type(np, "pci"); + + if (!np) + return -ENODEV; + + plx = of_get_property(np, "plx", NULL); + + if (!plx || (plx && (0 == *plx))) + return -ENODEV; + + printk (KERN_CRIT "pci_chrdev_template: initialising\n"); + if ((i_result = register_chrdev (i_template_major, "pci_chrdev_template", &_template_fops)) < 0) + { + // dynamic major number allocation + i_result = register_chrdev (0, "pci_chrdev_template", &_template_fops); + i_template_major = i_result; + if (i_result < 0) + { + printk (KERN_CRIT "pci_chrdev_template: Cannot register device.\n"); + return (i_result); + } + } + + if( 0 == pci_register_driver(&pci_drv_template) ) + return 0; + unregister_chrdev( i_template_major,"pci_chrdev_template"); + return (-EIO); +} + + +static +void __exit pci_drv_exit(void) +{ + pci_unregister_driver( &pci_drv_template ); + unregister_chrdev(i_template_major,"pci_chrdev_template"); + return; +} + + +static int +_template_open (struct inode *inode, struct file *filp) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) + MOD_INC_USE_COUNT; +#endif + return (0); +} + + +static int +_template_close (struct inode *inode, struct file *filp) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) + MOD_DEC_USE_COUNT; +#endif + return (0); +} + + +static ssize_t +_template_read (struct file * filp, char *buff, size_t count, loff_t * ppos) +{ + u16 u16_template_dummy = inw(ioport); // read a word from the card + // write to user space + unsigned long ul = copy_to_user (buff, &u16_template_dummy, sizeof(u16_template_dummy)); + + return ( ((unsigned long)sizeof(u16_template_dummy)) - ul); +} + + +static ssize_t +_template_write (struct file * filp, __user const char *buff, size_t count, loff_t * ppos) +{ + u16 u16_template_dummy = 0; + // read from user space + unsigned long ul = copy_from_user (&u16_template_dummy, buff, sizeof(u16_template_dummy)); + + outw(u16_template_dummy, ioport); // write the word to the port + return ( ((unsigned long)sizeof(u16_template_dummy)) - ul); +} diff --git a/drivers/lsi/acp/serial.c b/drivers/lsi/acp/serial.c new file mode 100644 index 0000000..a3da27e --- /dev/null +++ b/drivers/lsi/acp/serial.c @@ -0,0 +1,1342 @@ +/* + * drivers/lsi/acp/serial.c + * + * Driver for AMBA serial ports on LSI's PPC based ACP. + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * Copyright 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * Copyright 2009 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This is a generic driver for ARM AMBA-type serial ports. They + * have a lot of 16550-like features, but are not register compatible. + * Note that although they do have CTS, DCD and DSR inputs, they do + * not have an RI input, nor do they have DTR or RTS outputs. If + * required, these have to be supplied via some other means (eg, GPIO) + * and hooked into this driver. + */ + +#if defined(CONFIG_SERIAL_ACP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/version.h" + +extern int acp_clock_get(int, unsigned long *); + +#define SZ_4K (4*1024) +#define UART_NR 2 +#define SERIAL_AMBA_MAJOR 204 +#define SERIAL_AMBA_MINOR 64 +#define SERIAL_AMBA_NR UART_NR +#define AMBA_ISR_PASS_LIMIT 256 +#define UART_DR_ERROR \ +(UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) +#define UART_DUMMY_DR_RX (1 << 16) + +#undef DEBUG_EXPORT_SYMBOLS +#define DEBUG_EXPORT_SYMBOLS +#ifdef DEBUG_EXPORT_SYMBOLS +#define STATIC +#else +#define STATIC static +#endif + +#define MAX_BAUD_RATE 115200 + +/* + ====================================================================== + ====================================================================== + A modified uart_port structure. + ====================================================================== + ====================================================================== +*/ + +struct uart_acp_port { + struct uart_port port; + irq_hw_number_t hwirq; + unsigned int interrupt_mask; + unsigned int old_status; + void *timer_base; + unsigned long divisor; + unsigned char ibrd; + unsigned char fbrd; +}; + +/* + ====================================================================== + ====================================================================== + Both UARTs share the same clock input, the output of the 2nd timer, + or timer 1, from the APB Dual Input Timers (there are two of these, + thus 4 timers). + ====================================================================== + ====================================================================== +*/ + +#define TIMER_LOAD 0x00 +#define TIMER_VALUE 0x04 +#define TIMER_CONTROL 0x08 +#define TIMER_CONTROL_ENABLE 0x80 +#define TIMER_CONTROL_MODE 0x40 +#define TIMER_CONTROL_INTERRUPT_ENABLE 0x20 +#define TIMER_CONTROL_OUTPUT_MODE 0x10 +#define TIMER_CONTROL_PRESCALER 0x0c +#define TIMER_CONTROL_SIZE 0x02 +#define TIMER_CONTROL_ONE_SHOT 0x01 +#define TIMER_INTCLR 0x0C +#define TIMER_RIS 0x10 +#define TIMER_MIS 0x14 +#define TIMER_BGLOAD 0x18 + +/* + ---------------------------------------------------------------------- + get_clock_stuff +*/ + +STATIC int +get_clock_stuff(struct uart_port *port, int baud_rate) +{ + struct uart_acp_port *uap = (struct uart_acp_port *) port; + unsigned long per_clock; + unsigned long divisor; + unsigned long ibrd; + unsigned long fbrd; + + /* Get the speed of the peripheral clock. */ + acp_clock_get(1, &per_clock); + per_clock *= 1000; + + /* + Since the IBDR (integer part of the baud rate + divisor) is a 16 bit quatity, find the minimum load + value that will let the IBDR/FBDR result in the + desired baud rate. + */ + + divisor = 1; + + do { + ibrd = (per_clock / ++divisor) / (16 * baud_rate); + } while (0xff < ibrd); + + /* + The following forumla is from the ARM document (ARM DDI 0183E). + + Baud Rate Divisor = (Uart Clock / (16 * Baud Rate)) + + Baud Rate Divisor is then split into integral and fractional + parts. The IBRD value is simply the itegral part. The FBRD is + calculated as follows. + + FBRD = fractional part of the Baud Rate Divisor * 64 + 0.5 + + The fractional part of the Baud Rate Divisor can be represented as + follows. + + (Uart Clock % (16 * baud_rate)) / (16 * baud_rate) + + As long as the division isn't done till the end. So, the above * + 64 + 0.5 is the FBRD. Also note that x/y + 1/2 = (2x+y)/2y. This + leads to + + ((Uart Clock % (16 * baud_rate)) * 64 * 2 + (16 * baud_rate)) + --------------------------------------------------------------------- + 2 * (16 * baud_rate) + */ + + port->uartclk = (per_clock / divisor); + + fbrd = port->uartclk % (16 * baud_rate); + fbrd *= 128; + fbrd += (16 * baud_rate); + fbrd /= (2 * (16 * baud_rate)); + + uap->divisor = (divisor - 1); + uap->ibrd = (unsigned char) ibrd; + uap->fbrd = (unsigned char) fbrd; + +#if 0 + printk("\n\n == == DEBUG == ==\n\n"); + printk("\n\n\n\nuap->ibrd=%d ibrd=%d uap->fbrd=%d fbrd=%d " + "port->uartclk=%d per_clock=%d uap->divisor=%d divisor=%d " + "timer_load=%d cbr=%d\n\n\n\n", + uap->ibrd, ibrd, uap->fbrd, fbrd, port->uartclk, per_clock, + uap->divisor, divisor, in_le32(uap->timer_base + TIMER_LOAD), + (per_clock / divisor) * 4 / (64 * ibrd * fbrd)); + printk("\n\n == == == == == ==\n\n"); +#endif + + if (uap->divisor != in_le32(uap->timer_base + TIMER_LOAD)) { + while (0 == + (in_le32((const volatile unsigned *) + (uap->port.membase + UART01x_FR)) & + UART011_FR_TXFE)) + ; + + while (0 != + (in_le32((const volatile unsigned *) + (uap->port.membase + UART01x_FR)) & + UART01x_FR_BUSY)) + ; + + out_le32((uap->timer_base + TIMER_CONTROL), 0); + out_le32((uap->timer_base + TIMER_LOAD), uap->divisor); + out_le32((uap->timer_base + TIMER_CONTROL), + (TIMER_CONTROL_ENABLE | + TIMER_CONTROL_MODE)); + } + + return 0; +} + +/* + ====================================================================== + ====================================================================== + Serial operations. + ====================================================================== + ====================================================================== +*/ + +/* + ------------------------------------------------------------------------------ + acp_serial_wac + + This was added to allow an easy debugging breakpoint. +*/ + +STATIC void +acp_serial_wac(u32 *address, int character, u32 line) +{ + out_le32(address, character); + + return; +} + +/* + ------------------------------------------------------------------------------ + acp_serial_tx_empty +*/ + +STATIC unsigned int +acp_serial_tx_empty(struct uart_port *port) +{ + struct uart_acp_port * uap = (struct uart_acp_port *) port; + unsigned int status = + in_le32((u32 *) (uap->port.membase + UART01x_FR)); + return status & + (UART01x_FR_BUSY | UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; +} + +/* + ---------------------------------------------------------------------- + acp_serial_stop_tx +*/ + +STATIC void +acp_serial_stop_tx(struct uart_port *port) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + + uap->interrupt_mask &= ~UART011_TXIM; + out_le32((u32 *)(uap->port.membase + UART011_IMSC), + uap->interrupt_mask); +} + +/* + ---------------------------------------------------------------------- + acp_serial_start_tx +*/ + +STATIC void +acp_serial_start_tx(struct uart_port *port) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + + uap->interrupt_mask |= UART011_TXIM; + out_le32((u32 *)(uap->port.membase + UART011_IMSC), + uap->interrupt_mask); +} + +void acp_serial_stop_rx(struct uart_port *port) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + + uap->interrupt_mask &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| + UART011_PEIM|UART011_BEIM|UART011_OEIM); + out_le32((u32 *)(uap->port.membase + UART011_IMSC), + uap->interrupt_mask); +} + +void acp_serial_enable_ms(struct uart_port *port) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + + uap->interrupt_mask |= + UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; + out_le32((u32 *)(uap->port.membase + UART011_IMSC), + uap->interrupt_mask); +} + +/* + ---------------------------------------------------------------------- + acp_serial_rx_chars +*/ + +STATIC void +acp_serial_rx_chars(struct uart_acp_port *uap) +{ + struct tty_struct *tty = uap->port.state->port.tty; + unsigned int status, ch, flag, max_count = 256; + + /*status = readw(uap->port.membase + UART01x_FR);*/ + status = in_le32((u32 *)(uap->port.membase + UART01x_FR)); + while ((status & UART01x_FR_RXFE) == 0 && max_count--) { + ch = in_le32((u32 *)(uap->port.membase + UART01x_DR)) | + UART_DUMMY_DR_RX; + flag = TTY_NORMAL; + uap->port.icount.rx++; + + /* + * Note that the error handling code is + * out of the main execution path + */ + if (unlikely(ch & UART_DR_ERROR)) { + if (ch & UART011_DR_BE) { + ch &= ~(UART011_DR_FE | UART011_DR_PE); + uap->port.icount.brk++; + if (uart_handle_break(&uap->port)) + goto ignore_char; + } else if (ch & UART011_DR_PE) + uap->port.icount.parity++; + else if (ch & UART011_DR_FE) + uap->port.icount.frame++; + if (ch & UART011_DR_OE) + uap->port.icount.overrun++; + + ch &= uap->port.read_status_mask; + + if (ch & UART011_DR_BE) + flag = TTY_BREAK; + else if (ch & UART011_DR_PE) + flag = TTY_PARITY; + else if (ch & UART011_DR_FE) + flag = TTY_FRAME; + } + + if (uart_handle_sysrq_char(&uap->port, ch & 255)) + goto ignore_char; + + uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); + + ignore_char: + status = in_le32((u32 *)(uap->port.membase + UART01x_FR)); + } + spin_unlock(&uap->port.lock); + tty_flip_buffer_push(tty); + spin_lock(&uap->port.lock); +} + +/* + ---------------------------------------------------------------------- + acp_serial_tx_chars +*/ + +STATIC void +acp_serial_tx_chars(struct uart_acp_port *uap) +{ + struct circ_buf *xmit = &uap->port.state->xmit; + int count; + + if (uap->port.x_char) { + /*writew(uap->port.x_char, uap->port.membase + UART01x_DR);*/ +#if 0 + out_le32((u32 *)(uap->port.membase + UART01x_DR), + uap->port.x_char); +#endif + acp_serial_wac((u32 *)(uap->port.membase + UART01x_DR), + uap->port.x_char, __LINE__); + uap->port.icount.tx++; + uap->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { + acp_serial_stop_tx(&uap->port); + return; + } + + count = uap->port.fifosize >> 1; + do { +#if 0 + out_le32((u32 *)(uap->port.membase + UART01x_DR), + xmit->buf[xmit->tail]); +#endif + acp_serial_wac((u32 *) (uap->port.membase + UART01x_DR), + xmit->buf[xmit->tail], __LINE__); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + uap->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&uap->port); + + if (uart_circ_empty(xmit)) + acp_serial_stop_tx(&uap->port); +} + +void acp_serial_modem_status(struct uart_acp_port *uap) +{ + unsigned int status, delta; + + status = in_le32((u32 *)(uap->port.membase + UART01x_FR)) & + UART01x_FR_MODEM_ANY; + + delta = status ^ uap->old_status; + uap->old_status = status; + + if (!delta) + return; + + if (delta & UART01x_FR_DCD) + uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); + + if (delta & UART01x_FR_DSR) + uap->port.icount.dsr++; + + if (delta & UART01x_FR_CTS) + uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); + + wake_up_interruptible(&uap->port.state->port.delta_msr_wait); +} + +/* + ------------------------------------------------------------------------------ + acp_serial_isr +*/ + +STATIC irqreturn_t +acp_serial_isr(int irq, void *dev_id) +{ + struct uart_acp_port *uap = dev_id; + unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; + int handled = 0; + + spin_lock(&uap->port.lock); + + /*status = readw(uap->port.membase + UART011_MIS);*/ + status = in_le32((u32 *)(uap->port.membase + UART011_MIS)); + if (status) { + do { +#if 0 + writew(status & ~(UART011_TXIS|UART011_RTIS| + UART011_RXIS), + uap->port.membase + UART011_ICR); +#else + out_le32((u32 *)(uap->port.membase + UART011_ICR), + (status & + ~(UART011_TXIS|UART011_RTIS|UART011_RXIS))); +#endif + + if (status & (UART011_RTIS|UART011_RXIS)) + acp_serial_rx_chars(uap); + if (status & (UART011_DSRMIS|UART011_DCDMIS| + UART011_CTSMIS|UART011_RIMIS)) + acp_serial_modem_status(uap); + if (status & UART011_TXIS) + acp_serial_tx_chars(uap); + + if (pass_counter-- == 0) + break; + + /*status = readw(uap->port.membase + UART011_MIS);*/ + status = + in_le32((u32 *)(uap->port.membase + UART011_MIS)); + } while (status != 0); + handled = 1; + } + + spin_unlock(&uap->port.lock); + + return IRQ_RETVAL(handled); +} + +unsigned int acp_serial_get_mctrl(struct uart_port *port) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + unsigned int result = 0; + /*unsigned int status = readw(uap->port.membase + UART01x_FR);*/ + unsigned int status = in_le32((u32 *)(uap->port.membase + UART01x_FR)); + +#define TIOCMBIT(uartbit, tiocmbit) do { \ + if (status & (uartbit)) \ + result |= (tiocmbit); \ +} while (0); + TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); + TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); + TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); + TIOCMBIT(UART011_FR_RI, TIOCM_RNG); +#undef TIOCMBIT + return result; +} + +void acp_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + unsigned int cr; + + /*cr = readw(uap->port.membase + UART011_CR);*/ + cr = in_le32((u32 *)(uap->port.membase + UART011_CR)); + +#define TIOCMBIT(tiocmbit, uartbit) do { \ + if (mctrl & tiocmbit) \ + cr |= uartbit; \ + else \ + cr &= ~uartbit; \ +} while (0); + + TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); + TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); + TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); + TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); + TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); + +#undef TIOCMBIT + + /*writew(cr, uap->port.membase + UART011_CR);*/ + out_le32((u32 *)(uap->port.membase + UART011_CR), cr); +} + +void acp_serial_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + unsigned long flags; + unsigned int lcr_h; + + spin_lock_irqsave(&uap->port.lock, flags); + /*lcr_h = readw(uap->port.membase + UART011_LCRH);*/ + lcr_h = in_le32((u32 *)(uap->port.membase + UART011_LCRH)); + if (break_state == -1) + lcr_h |= UART01x_LCRH_BRK; + else + lcr_h &= ~UART01x_LCRH_BRK; + /*writew(lcr_h, uap->port.membase + UART011_LCRH);*/ + out_le32((u32 *)(uap->port.membase + UART011_LCRH), lcr_h); + spin_unlock_irqrestore(&uap->port.lock, flags); +} + +#ifdef CONFIG_CONSOLE_POLL + +/* + ---------------------------------------------------------------------- + acp_serial_poll_get_char +*/ + +STATIC int +acp_serial_poll_get_char(struct uart_port *port) +{ + struct uart_acp_port * uap = (struct uart_acp_port *) port; + unsigned int status; + + do { + status = in_le32((u32 *) + (uap->port.membase + UART01x_FR)); + } while (status & UART01x_FR_RXFE); + + return in_le32((u32 *) (uap->port.membase + UART01x_DR)); +} + +/* + ---------------------------------------------------------------------- + acp_serial_poll_put_char +*/ + +STATIC void +acp_serial_poll_put_char(struct uart_port *port, unsigned char ch) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + + while (in_le32((u32 *) (uap->port.membase + UART01x_FR)) & + UART01x_FR_TXFF) { + barrier(); + } + + acp_serial_wac((u32 *)(uap->port.membase + UART01x_DR), ch, + __LINE__); + + return; +} + +#endif /* CONFIG_CONSOLE_POLL */ + +/* + ---------------------------------------------------------------------- + acp_serial_startup +*/ + +STATIC int +acp_serial_startup(struct uart_port *port) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + unsigned int cr; + int retval = 0; + +#ifndef CONFIG_CONSOLE_POLL + + /* + * Set up the interrupt. + */ + + uap->port.irq = irq_create_mapping( NULL, uap->hwirq ); + + if (NO_IRQ == uap->port.irq) { + printk(KERN_ERR "irq_create_mapping() failed!\n"); + goto clk_dis; + } + + retval = irq_set_irq_type(uap->port.irq, IRQ_TYPE_LEVEL_HIGH); + + if (0 != retval) { + printk(KERN_ERR "set_irq_type(%d, 0x%x) failed!\n", + uap->port.irq, IRQ_TYPE_LEVEL_HIGH); + goto clk_dis; + } + + retval = request_irq(uap->port.irq, acp_serial_isr, + IRQF_DISABLED, "uart-pl011", uap); + + if (retval) { + printk(KERN_ERR "request_irq(%d) failed!\n", uap->port.irq); + goto clk_dis; + } + + out_le32((u32 *)(uap->port.membase + UART011_IFLS), + UART011_IFLS_RX4_8|UART011_IFLS_TX4_8); + +#endif /* CONFIG_CONSOLE_POLL */ + + /* + * Provoke TX FIFO interrupt into asserting. + */ + cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; + out_le32((u32 *)(uap->port.membase + UART011_CR), cr); + out_le32((u32 *)(uap->port.membase + UART011_FBRD), 0); + out_le32((u32 *)(uap->port.membase + UART011_IBRD), 1); + out_le32((u32 *)(uap->port.membase + UART011_LCRH), 0); + acp_serial_wac((u32 *) (uap->port.membase + UART01x_DR), 0, + __LINE__); + + while (in_le32((u32 *)(uap->port.membase + UART01x_FR)) & + UART01x_FR_BUSY) + barrier(); + + cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; + /*writew(cr, uap->port.membase + UART011_CR);*/ + out_le32((u32 *)(uap->port.membase + UART011_CR), cr); + + /* + * initialise the old status of the modem signals + */ +#if 0 + uap->old_status = + readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; +#else + uap->old_status = + in_le32((u32 *)(uap->port.membase + UART01x_FR)) & + UART01x_FR_MODEM_ANY; +#endif + + /* + * Finally, enable interrupts + */ + spin_lock_irq(&uap->port.lock); + uap->interrupt_mask = UART011_RXIM | UART011_RTIM; + /*writew(uap->interrupt_mask, uap->port.membase + UART011_IMSC);*/ + out_le32((u32 *)(uap->port.membase + UART011_IMSC), + uap->interrupt_mask); + spin_unlock_irq(&uap->port.lock); + + return 0; + + clk_dis: + /*clk_disable(uap->clk);*/ +/* out:*/ + return retval; +} + +/* + ---------------------------------------------------------------------- + acp_serial_shutdown +*/ + +STATIC void +acp_serial_shutdown(struct uart_port *port) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + unsigned long val; + + /* + * disable all interrupts + */ + spin_lock_irq(&uap->port.lock); + uap->interrupt_mask = 0; + out_le32((u32 *)(uap->port.membase + UART011_IMSC), + uap->interrupt_mask); + out_le32((u32 *)(uap->port.membase + UART011_ICR), 0xffff); + spin_unlock_irq(&uap->port.lock); + + /* + * Free the interrupt + */ + free_irq(uap->port.irq, uap); + + /* + * disable the port + */ + out_le32((u32 *)(uap->port.membase + UART011_CR), + UART01x_CR_UARTEN | UART011_CR_TXE); + + /* + * disable break condition and fifos + */ + val = in_le32((u32 *)(uap->port.membase + UART011_LCRH)); + val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); + out_le32((u32 *)(uap->port.membase + UART011_LCRH), val); +} + +/* + ---------------------------------------------------------------------- + acp_serial_set_termios +*/ + +STATIC void +acp_serial_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + unsigned int lcr_h, old_cr; + unsigned long flags; + int baud; + struct uart_acp_port *uap = (struct uart_acp_port *)port; + + /* + * Set up the clock, and calculate the divisors. + */ + + /*baud = termios->c_ospeed;*/ + baud = 9600; + get_clock_stuff(port, baud); + + switch (termios->c_cflag & CSIZE) { + case CS5: + lcr_h = UART01x_LCRH_WLEN_5; + break; + case CS6: + lcr_h = UART01x_LCRH_WLEN_6; + break; + case CS7: + lcr_h = UART01x_LCRH_WLEN_7; + break; + default: /* CS8 */ + lcr_h = UART01x_LCRH_WLEN_8; + break; + } + if (termios->c_cflag & CSTOPB) + lcr_h |= UART01x_LCRH_STP2; + if (termios->c_cflag & PARENB) { + lcr_h |= UART01x_LCRH_PEN; + if (!(termios->c_cflag & PARODD)) + lcr_h |= UART01x_LCRH_EPS; + } + if (port->fifosize > 1) + lcr_h |= UART01x_LCRH_FEN; + + spin_lock_irqsave(&port->lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + port->read_status_mask = UART011_DR_OE | 255; + if (termios->c_iflag & INPCK) + port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + port->read_status_mask |= UART011_DR_BE; + + /* + * Characters to ignore + */ + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; + if (termios->c_iflag & IGNBRK) { + port->ignore_status_mask |= UART011_DR_BE; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= UART011_DR_OE; + } + + /* + * Ignore all characters if CREAD is not set. + */ + if ((termios->c_cflag & CREAD) == 0) + port->ignore_status_mask |= UART_DUMMY_DR_RX; + + if (UART_ENABLE_MS(port, termios->c_cflag)) + acp_serial_enable_ms(port); + + /* first, disable everything */ + old_cr = in_le32((u32 *)(uap->port.membase + UART011_CR)); + out_le32((u32 *)(uap->port.membase + UART011_CR), 0); + + /* Set baud rate */ + out_le32((u32 *)(uap->port.membase + UART011_FBRD), uap->fbrd); + out_le32((u32 *)(uap->port.membase + UART011_IBRD), uap->ibrd); + + /* + * ----------v----------v----------v----------v----- + * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L + * ----------^----------^----------^----------^----- + */ + out_le32((u32 *)(uap->port.membase + UART011_LCRH), lcr_h); + out_le32((u32 *)(uap->port.membase + UART011_CR), old_cr); + + spin_unlock_irqrestore(&port->lock, flags); +} + +const char *acp_serial_type(struct uart_port *port) +{ + return port->type == PORT_AMBA ? "AMBA/PL011" : NULL; +} + +/* + * Release the memory region(s) being used by 'port' + */ +void acp_serial_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, SZ_4K); +} + +/* + * Request the memory region(s) being used by 'port' + */ +int acp_serial_request_port(struct uart_port *port) +{ + return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") + != NULL ? 0 : -EBUSY; +} + +/* + * Configure/autoconfigure the port. + */ +void acp_serial_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + port->type = PORT_AMBA; + acp_serial_request_port(port); + } +} + +/* + * verify the new serial_struct (for TIOCSSERIAL). + */ +int acp_serial_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) + ret = -EINVAL; + if (ser->irq < 0 || ser->irq >= nr_irqs) + ret = -EINVAL; + if (ser->baud_base < 9600) + ret = -EINVAL; + return ret; +} + +static struct uart_ops amba_acp_pops = { + .tx_empty = acp_serial_tx_empty, + .set_mctrl = acp_serial_set_mctrl, + .get_mctrl = acp_serial_get_mctrl, + .stop_tx = acp_serial_stop_tx, + .start_tx = acp_serial_start_tx, + .stop_rx = acp_serial_stop_rx, + .enable_ms = acp_serial_enable_ms, + .break_ctl = acp_serial_break_ctl, + .startup = acp_serial_startup, + .shutdown = acp_serial_shutdown, + .set_termios = acp_serial_set_termios, + .type = acp_serial_type, + .release_port = acp_serial_release_port, + .request_port = acp_serial_request_port, + .config_port = acp_serial_config_port, + .verify_port = acp_serial_verify_port, +#ifdef CONFIG_CONSOLE_POLL + .poll_get_char = acp_serial_poll_get_char, + .poll_put_char = acp_serial_poll_put_char, +#endif +}; + +static struct uart_acp_port *acp_ports[2]; + +#ifdef CONFIG_SERIAL_ACP_CONSOLE + +/* + ---------------------------------------------------------------------- + acp_serial_console_putchar +*/ + +STATIC void +acp_serial_console_putchar(struct uart_port *port, int ch) +{ + struct uart_acp_port *uap = (struct uart_acp_port *)port; + + while (in_le32((u32 *)(uap->port.membase + UART01x_FR)) & + UART01x_FR_TXFF) { + barrier(); + } + + /*out_le32((u32 *)(uap->port.membase + UART01x_DR), ch);*/ + acp_serial_wac((u32 *) (uap->port.membase + UART01x_DR), ch, + __LINE__); +} + +void +acp_console_write(struct console *co, const char *s, unsigned int count) +{ + struct uart_acp_port *uap = acp_ports[co->index]; + unsigned int status, old_cr, new_cr; + + /*clk_enable(uap->clk);*/ + + /* + * First save the CR then disable the interrupts + */ + /*old_cr = readw(uap->port.membase + UART011_CR);*/ + old_cr = in_le32((u32 *)(uap->port.membase + UART011_CR)); + new_cr = old_cr & ~UART011_CR_CTSEN; + new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; + /*writew(new_cr, uap->port.membase + UART011_CR);*/ + out_le32((u32 *)(uap->port.membase + UART011_CR), new_cr); + + uart_console_write(&uap->port, s, count, acp_serial_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the TCR + */ + do { + /*status = readw(uap->port.membase + UART01x_FR);*/ + status = + in_le32((u32 *)(u32 *)(uap->port.membase + UART01x_FR)); + } while (status & UART01x_FR_BUSY); + /*writew(old_cr, uap->port.membase + UART011_CR);*/ + out_le32((u32 *)(uap->port.membase + UART011_CR), old_cr); + + /*clk_disable(uap->clk);*/ +} + +void __init +acp_console_get_options(struct uart_acp_port *uap, int *baud, + int *parity, int *bits) +{ + /*if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {*/ + if (in_le32((u32 *)(u32 *)(uap->port.membase + UART011_CR)) & + UART01x_CR_UARTEN) { + unsigned int lcr_h, ibrd, fbrd; + + lcr_h = in_le32((u32 *)(u32 *)(uap->port.membase + + UART011_LCRH)); + + *parity = 'n'; + if (lcr_h & UART01x_LCRH_PEN) { + if (lcr_h & UART01x_LCRH_EPS) + *parity = 'e'; + else + *parity = 'o'; + } + + if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) + *bits = 7; + else + *bits = 8; + + ibrd = in_le32((u32 *)(u32 *)(uap->port.membase + + UART011_IBRD)); + fbrd = in_le32((u32 *)(u32 *)(uap->port.membase + + UART011_FBRD)); + + *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); + } +} + +int __init acp_console_setup(struct console *co, char *options) +{ + struct uart_acp_port *uap; + int baud = 9600; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index >= UART_NR) + co->index = 0; + uap = acp_ports[co->index]; + if (!uap) + return -ENODEV; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + else + acp_console_get_options(uap, &baud, &parity, &bits); + + return uart_set_options(&uap->port, co, baud, parity, bits, flow); +} + +static struct uart_driver acp_serial_driver; +static struct console acp_console = { + .name = "ttyS", + .write = acp_console_write, + .device = uart_console_device, + .setup = acp_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &acp_serial_driver, +}; + +static int __init +acp_console_init(void) +{ + register_console(&acp_console); + + return 0; +} + +console_initcall(acp_console_init); + +#define ACP_CONSOLE (&acp_console) +#else +#define ACP_CONSOLE NULL +#endif + +static struct uart_driver acp_serial_driver = { + .owner = THIS_MODULE, + .driver_name = "serial", + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .nr = UART_NR, + .cons = ACP_CONSOLE, +}; + +/* + ---------------------------------------------------------------------- + acp_serial_add_ports +*/ + +STATIC int +acp_serial_add_ports(struct uart_driver *driver) +{ + struct uart_acp_port *uap; + int i, ret; + struct device_node *np = NULL; + u64 addr = 0; + const u32 *reg, *interrupts, *clk, *speed; + int baud_rate; + int *enabled; + + for (i = 0; i < ARRAY_SIZE(acp_ports); ++i) { + if (acp_ports[i] == NULL) { + break; + } + } + + if (i == ARRAY_SIZE(acp_ports)) { + ret = -EBUSY; + goto out; + } + + uap = kzalloc(sizeof(struct uart_acp_port), GFP_KERNEL); + + if (NULL == uap) { + ret = -ENOMEM; + goto out; + } + + np = of_find_node_by_type(np, "serial"); + + while (np && !of_device_is_compatible(np, "acp-uart0")) + np = of_find_node_by_type(np, "serial"); + + if (np) { + enabled = of_get_property(np, "enabled", NULL); + } + + if (!enabled) { + /* + Older LSI U-Boot package (prior to 4.8.1.36). + + Only use UART0. The timer registers are defined + differently in the device tree. + */ + uap->timer_base = ioremap(0x002000408040ULL, 0x20); + } else { + /* + Newer LSI U-Boot package (4.8.1.36 on). + + Only use a serial port if it is enabled. + */ + + if (!np || (0 == *enabled)) { + np = NULL; + np = of_find_node_by_type(np, "serial"); + + while (np && !of_device_is_compatible(np, "acp-uart1")) + np = of_find_node_by_type(np, "serial"); + + if (np) { + enabled = of_get_property(np, "enabled", NULL); + printk("uart1 *enabled=%d\n", *enabled); + } + } + + if (np && (0 != *enabled)) { + reg = of_get_property(np, "clock-reg", NULL); + + if (reg) { + addr = of_translate_address(np, reg); + if (addr == OF_BAD_ADDR) + addr = 0; + } + + if (addr) + uap->timer_base = ioremap(addr, reg[1]); + else { + printk(KERN_ERR "timer io address not found\n"); + ret = -ENOMEM; + } + } + } + + if (np) { + reg = of_get_property(np, "reg", NULL); + + if (reg) { + addr = of_translate_address(np, reg); + if (addr == OF_BAD_ADDR) + addr = 0; + } + + if (addr) + uap->port.membase = ioremap(addr, reg[1]); + else { + printk(KERN_ERR "serial io address not found\n"); + ret = -ENOMEM; + } + + interrupts = of_get_property(np, "interrupts", NULL); + + if (interrupts) + uap->hwirq = interrupts[0]; + else { + printk(KERN_ERR "serial irq not found\n"); + uap->hwirq = 22; + } + + clk = of_get_property(np, "clock-frequency", NULL); + + if (clk && *clk) + uap->port.uartclk = *clk; + else { + printk(KERN_ERR "serial clock frequency not found\n"); + uap->port.uartclk = 6500000; + } + + speed = of_get_property(np, "current-speed", NULL); + + if (speed && *speed) + baud_rate = *speed; + else { + printk(KERN_ERR "current speed not found\n"); + baud_rate = 9600; + } + } else { + ret = -ENOMEM; + } + + uap->port.iotype = UPIO_MEM; + uap->port.fifosize = 16; + uap->port.ops = &amba_acp_pops; + uap->port.flags = UPF_BOOT_AUTOCONF; + uap->port.line = i; + get_clock_stuff(&uap->port, baud_rate); + acp_ports[i] = uap; + ret = uart_add_one_port(driver, &uap->port); + + if (0 != ret) { + acp_ports[i] = NULL; + kfree(uap); + } + + out: + return ret; +} + +/* + ---------------------------------------------------------------------- + acp_serial_delete_ports +*/ + +STATIC int +acp_serial_delete_ports(struct uart_driver *driver) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(acp_ports); ++i) { + if (NULL != acp_ports[i]) { + uart_remove_one_port(driver, + &(acp_ports[i])->port); + kfree(acp_ports[i]); + acp_ports[i] = NULL; + } + } + + return 0; +} + +/* + ====================================================================== + ====================================================================== + For debugging, export symbols... + ====================================================================== + ====================================================================== +*/ + +#ifdef DEBUG_EXPORT_SYMBOLS + +EXPORT_SYMBOL(acp_serial_isr); +EXPORT_SYMBOL(acp_serial_set_termios); +EXPORT_SYMBOL(acp_serial_shutdown); +EXPORT_SYMBOL(get_clock_stuff); +EXPORT_SYMBOL(acp_serial_startup); +EXPORT_SYMBOL(acp_serial_tx_empty); +EXPORT_SYMBOL(acp_serial_tx_chars); +EXPORT_SYMBOL(acp_serial_add_ports); +EXPORT_SYMBOL(acp_serial_delete_ports); +EXPORT_SYMBOL(acp_serial_wac); +EXPORT_SYMBOL(acp_serial_start_tx); +EXPORT_SYMBOL(acp_serial_stop_tx); + +#ifdef CONFIG_SERIAL_ACP_CONSOLE +EXPORT_SYMBOL(acp_serial_console_putchar); +#endif + +#ifdef CONFIG_CONSOLE_POLL +EXPORT_SYMBOL(acp_serial_poll_put_char); +EXPORT_SYMBOL(acp_serial_poll_get_char); +#endif + +#endif + +/* + ====================================================================== + ====================================================================== + Linux module stuff. + ====================================================================== + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + acp_init +*/ + +int __init +acp_serial_init(void) +{ + int ret; + + printk(KERN_INFO "Serial: ACP Serial Driver\n"); + + /* Clear the ports array */ + memset((void *) &acp_ports[0], 0, + sizeof(struct uart_acp_port *) * ARRAY_SIZE(acp_ports)); + + /* Register the driver */ + ret = uart_register_driver(&acp_serial_driver); + + if (0 != ret) { + printk(KERN_ERR + "uart_register_driver() failed with %d\n", ret); + goto out; + } + + /* Add ports */ + ret = acp_serial_add_ports(&acp_serial_driver); + + if (0 != ret) { + printk(KERN_ERR + "acp_serial_add_ports() failed with %d\n", ret); + goto out; + } + + out: + return ret; +} + +module_init(acp_serial_init); + +/* + ---------------------------------------------------------------------- + acp_serial_exit +*/ + +void __exit +acp_serial_exit(void) +{ + acp_serial_delete_ports(&acp_serial_driver); + uart_unregister_driver(&acp_serial_driver); +} + +module_exit(acp_serial_exit); + +MODULE_AUTHOR("LSI Corporation"); +MODULE_DESCRIPTION("ARM AMBA serial port on PPC476 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/lsi/acp/test.c b/drivers/lsi/acp/test.c new file mode 100644 index 0000000..46cdf1e --- /dev/null +++ b/drivers/lsi/acp/test.c @@ -0,0 +1,300 @@ +/* + * drivers/lsi/acp/test.c + * + * Copyright (C) 2010 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include + +#undef TICK_TEST +/*#define TICK_TEST*/ + +#undef ENV_TEST +/*#define ENV_TEST*/ + +#undef IO_TEST +/*#define IO_TEST*/ + +#undef LOCK_TEST +/*#define LOCK_TEST*/ + +#if defined(TICK_TEST) + +/* + ====================================================================== + ====================================================================== + Wall Time + ====================================================================== + ====================================================================== +*/ + +#include + +int __init +acp_test(void) +{ + int count = 120; + char *output[] = { "tick", "tock" }; + int index = 0; + + while (0 < count) { + printk(KERN_WARN "%s\n", output[index]); + index ^= 1; + udelay(1000 * 1000); + } + +} + +#elif defined(ENV_TEST) + +/* + ====================================================================== + ====================================================================== + U-Boot Environment + ====================================================================== + ====================================================================== +*/ + +#include + +int __init +acp_test(void) +{ + struct mtd_info *mtd_env0; + struct mtd_info *mtd_env1; + loff_t offset; + void *buffer_env0; + void *buffer_env1; + int i; + int rc; + + mtd_env0 = get_mtd_device_nm("env-0"); + + if ((struct mtd_info *) -ENODEV == mtd_env0) { + printk(KERN_WARN " --> Couldn't Get MTD Device by name!\n"); + return 0; + } + + mtd_env1 = get_mtd_device_nm("env-1"); + + if ((struct mtd_info *) -ENODEV == mtd_env1) { + printk(KERN_WARN " --> Couldn't Get MTD Device by name!\n"); + return 0; + } + + printk(KERN_INFO " --> Got the MTD Devices by name: 0x%x/0x%x %llu/%llu " + "%u/%u %d/%d\n", + (unsigned int) mtd_env0, (unsigned int) mtd_env1, + mtd_env0->size, mtd_env1->size, + mtd_env0->erasesize, mtd_env1->erasesize, + mtd_env0->numeraseregions, mtd_env1->numeraseregions); + + for (offset = 0; + offset < mtd_env0->size; + offset += mtd_env0->erasesize) { + printk(" --> mtd_env0 --> offset:0x%08llx is_bad:%d\n", + offset, mtd_env0->block_isbad(mtd_env0, offset)); + } + + for (offset = 0; + offset < mtd_env1->size; + offset += mtd_env1->erasesize) { + printk(" --> mtd_env1 --> offset:0x%08llx is_bad:%d\n", + offset, mtd_env1->block_isbad(mtd_env1, offset)); + } + + buffer_env0 = kmalloc(0x20000, GFP_KERNEL); + + if (0 == buffer_env0) { + printk(KERN_WARN "buffer allocation failed!\n"); + return 0; + } + + rc = mtd_env0->read(mtd_env0, 0, 0x20000, &i, buffer_env0); + printk(KERN_INFO "rc=%d i=0x%x\n", rc, i); + + for (i = 0; i < 16; ++i) { + printk(KERN_INFO "0x%08x ", + ((unsigned long *) buffer_env0)[i]); + } + + kfree(buffer_env0); + + return 0; +} + +#elif defined(IO_TEST) + +/* + ====================================================================== + ====================================================================== + IO test -- Map IO from various regions... + ====================================================================== + ====================================================================== +*/ + +#include + +#define ROM_PHYSICAL_ADDRESS 0x2100000000ULL +#define LCM_PHYSICAL_ADDRESS 0x1000000000ULL + +int __init +acp_test(void) +{ + void __iomem *virtual_address; + + /* Map in ROM */ + + virtual_address = ioremap(ROM_PHYSICAL_ADDRESS, (16 * 1024)); + + if ((void __iomem *) 0 == virtual_address) { + printk(KERN_ERR "iorema() of 0x%llx failed", + ROM_PHYSICAL_ADDRESS); + } else { + unsigned long *rom = (unsigned long *) virtual_address; + printk("ROM: 0x%lx 0x%lx 0x%lx 0x%lx\n", + rom[0], rom[1], rom[2], rom[3]); + } + + /* Map in LCM */ + + virtual_address = ioremap(LCM_PHYSICAL_ADDRESS, (16 * 1024)); + + if ((void __iomem *) 0 == virtual_address) { + printk(KERN_ERR "iorema() of 0x%llx failed", + LCM_PHYSICAL_ADDRESS); + } else { + unsigned long * lcm = (unsigned long *) virtual_address; + printk("LCM: 0x%lx 0x%lx 0x%lx 0x%lx\n", + lcm[0], lcm[1], lcm[2], lcm[3]); + } + + return 0; +} + +#elif defined(LOCK_TEST) + +#include +#include +#include +#include +#include +#include +#include + +#include "ncr.h" + +static unsigned long passes; +static unsigned long plls[4]; +static spinlock_t pll_test_spinlock = SPIN_LOCK_UNLOCKED; + +static struct task_struct *pll_test_thread; + +static int +pll_test(void *input) +{ + unsigned long ppcsys; + unsigned long ddr1; + unsigned long ddr0; + + for (;;) { + if (kthread_should_stop()) + break; + + schedule(); + spin_lock(&pll_test_spinlock); + ppcsys = mfdcr(0xd01); + ddr1 = ddr0 = 0; + + if (0 != ncr_read(NCP_REGION_ID(0xd, 0), 0x1c, 4, &ddr1)) + printk(KERN_ERR "DDR1 NCR Read Error\n"); + + if (0 != ncr_read(NCP_REGION_ID(0x23, 0), 0x1c, 4, &ddr0)) + printk(KERN_ERR "DDR1 NCR Read Error\n"); + + ++passes; + + if (0 == (ppcsys & 0x80000000)) + ++plls[0]; + + if (0 == (ppcsys & 0x40000000)) + ++plls[1]; + + if (0 == (ddr1 & 0x1)) + ++plls[2]; + + if (0 == (ddr0 & 0x1)) + ++plls[3]; + + spin_unlock(&pll_test_spinlock); + } + + return 0; +} + +static int pll_read_proc(char *page, char **start, off_t offset, + int count, int *eof, void *data) +{ + int length; + + spin_lock(&pll_test_spinlock); + length = sprintf(page, + "Passes:0x%08x PLL:0x%08x SYS:0x%08x DDR1:0x%08x " + "DDR0:0x%08x\n", + passes, plls[0], plls[1], plls[2], plls[3]); + passes = 0; + plls[0] = plls[1] = plls[2] = plls[3] = 0; + spin_unlock(&pll_test_spinlock); + *eof = 1; + + return length; +} + +int __init +acp_test(void) +{ + create_proc_read_entry("driver/lost_locks", + 0, NULL, pll_read_proc, NULL); + pll_test_thread = kthread_run(pll_test, (void *)0, "PLL Lock Test"); + return 0; +} + +#else + +/* + ====================================================================== + ====================================================================== + No Test Defined... + ====================================================================== + ====================================================================== +*/ + +int __init +acp_test(void) +{ + printk("Define a Test!\n"); + + return 0; +} + +#endif + +module_init(acp_test); + +MODULE_AUTHOR("LSI Corporation"); +MODULE_DESCRIPTION("Timing Test"); +MODULE_LICENSE("GPL"); diff --git a/drivers/lsi/acp/ubootenv.c b/drivers/lsi/acp/ubootenv.c new file mode 100644 index 0000000..c40c35d --- /dev/null +++ b/drivers/lsi/acp/ubootenv.c @@ -0,0 +1,557 @@ +/* + * drivers/lsi/acp/ubootenv.c + * + * Copyright (C) 2009 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 021.1.1_pre.17 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + ====================================================================== + Data types and Macros + ====================================================================== +*/ + +#undef DEBUG_EXPORT_SYMBOLS +/*#define DEBUG_EXPORT_SYMBOLS*/ +#ifdef DEBUG_EXPORT_SYMBOLS +#define STATIC +#else +#define STATIC static +#endif + +/* + DEBUG +*/ + +#undef DEBUG +/*#define DEBUG*/ +#if defined( DEBUG ) +#define DEBUG_PRINT( format, args... ) do { \ +printk( "ubootenv:%s:%d - DEBUG - ", __FUNCTION__, __LINE__ ); \ +printk( format, ##args ); \ +} while( 0 ); +#else +#define DEBUG_PRINT( format, args... ) { } +#endif + +/* + WARN +*/ + +#undef WARN +#define WARN +#if defined( WARN ) +#define WARN_PRINT( format, args... ) do { \ +printk( "ubootenv:%s:%d - WARN - ", __FUNCTION__, __LINE__ ); \ +printk( format, ##args ); \ +} while( 0 ); +#else +#define WARN_PRINT( format, args... ) { } +#endif + +/* + ERROR +*/ + +#define ERROR_PRINT( format, args... ) do { \ +printk( "ubootenv:%s:%d - ERROR - ", __FUNCTION__, __LINE__ ); \ +printk( format, ##args ); \ +} while( 0 ); + +/* + ====================================================================== + Global Variables + ====================================================================== +*/ + +static unsigned long uboot_env_size = (128 * 1024); +static unsigned long uboot_env_cs_size = (128 * 1024); +static int uboot_env_current = -1; + +#define ENVIRONMENT_DATA_SIZE( size ) ( size - ( 2 * sizeof( unsigned long ) ) ) + +typedef struct environment { + + unsigned long crc32; + unsigned long flags; + unsigned char data [ ]; + +} __attribute__ ( ( packed ) ) environment_t; + +static environment_t * environment = ( environment_t * ) 0; + +static unsigned long crc32_lut [ 256 ] = { + + /* 0 -- */ 0u, 1996959894u, 3993919788u, 2567524794u, + /* 4 -- */ 124634137u, 1886057615u, 3915621685u, 2657392035u, + /* 8 -- */ 249268274u, 2044508324u, 3772115230u, 2547177864u, + /* 12 -- */ 162941995u, 2125561021u, 3887607047u, 2428444049u, + /* 16 -- */ 498536548u, 1789927666u, 4089016648u, 2227061214u, + /* 20 -- */ 450548861u, 1843258603u, 4107580753u, 2211677639u, + /* 24 -- */ 325883990u, 1684777152u, 4251122042u, 2321926636u, + /* 28 -- */ 335633487u, 1661365465u, 4195302755u, 2366115317u, + /* 32 -- */ 997073096u, 1281953886u, 3579855332u, 2724688242u, + /* 36 -- */ 1006888145u, 1258607687u, 3524101629u, 2768942443u, + /* 40 -- */ 901097722u, 1119000684u, 3686517206u, 2898065728u, + /* 44 -- */ 853044451u, 1172266101u, 3705015759u, 2882616665u, + /* 48 -- */ 651767980u, 1373503546u, 3369554304u, 3218104598u, + /* 52 -- */ 565507253u, 1454621731u, 3485111705u, 3099436303u, + /* 56 -- */ 671266974u, 1594198024u, 3322730930u, 2970347812u, + /* 60 -- */ 795835527u, 1483230225u, 3244367275u, 3060149565u, + /* 64 -- */ 1994146192u, 31158534u, 2563907772u, 4023717930u, + /* 68 -- */ 1907459465u, 112637215u, 2680153253u, 3904427059u, + /* 72 -- */ 2013776290u, 251722036u, 2517215374u, 3775830040u, + /* 76 -- */ 2137656763u, 141376813u, 2439277719u, 3865271297u, + /* 80 -- */ 1802195444u, 476864866u, 2238001368u, 4066508878u, + /* 84 -- */ 1812370925u, 453092731u, 2181625025u, 4111451223u, + /* 88 -- */ 1706088902u, 314042704u, 2344532202u, 4240017532u, + /* 92 -- */ 1658658271u, 366619977u, 2362670323u, 4224994405u, + /* 96 -- */ 1303535960u, 984961486u, 2747007092u, 3569037538u, + /* 100 -- */ 1256170817u, 1037604311u, 2765210733u, 3554079995u, + /* 104 -- */ 1131014506u, 879679996u, 2909243462u, 3663771856u, + /* 108 -- */ 1141124467u, 855842277u, 2852801631u, 3708648649u, + /* 112 -- */ 1342533948u, 654459306u, 3188396048u, 3373015174u, + /* 116 -- */ 1466479909u, 544179635u, 3110523913u, 3462522015u, + /* 120 -- */ 1591671054u, 702138776u, 2966460450u, 3352799412u, + /* 124 -- */ 1504918807u, 783551873u, 3082640443u, 3233442989u, + /* 128 -- */ 3988292384u, 2596254646u, 62317068u, 1957810842u, + /* 132 -- */ 3939845945u, 2647816111u, 81470997u, 1943803523u, + /* 136 -- */ 3814918930u, 2489596804u, 225274430u, 2053790376u, + /* 140 -- */ 3826175755u, 2466906013u, 167816743u, 2097651377u, + /* 144 -- */ 4027552580u, 2265490386u, 503444072u, 1762050814u, + /* 148 -- */ 4150417245u, 2154129355u, 426522225u, 1852507879u, + /* 152 -- */ 4275313526u, 2312317920u, 282753626u, 1742555852u, + /* 156 -- */ 4189708143u, 2394877945u, 397917763u, 1622183637u, + /* 160 -- */ 3604390888u, 2714866558u, 953729732u, 1340076626u, + /* 164 -- */ 3518719985u, 2797360999u, 1068828381u, 1219638859u, + /* 168 -- */ 3624741850u, 2936675148u, 906185462u, 1090812512u, + /* 172 -- */ 3747672003u, 2825379669u, 829329135u, 1181335161u, + /* 176 -- */ 3412177804u, 3160834842u, 628085408u, 1382605366u, + /* 180 -- */ 3423369109u, 3138078467u, 570562233u, 1426400815u, + /* 184 -- */ 3317316542u, 2998733608u, 733239954u, 1555261956u, + /* 188 -- */ 3268935591u, 3050360625u, 752459403u, 1541320221u, + /* 192 -- */ 2607071920u, 3965973030u, 1969922972u, 40735498u, + /* 196 -- */ 2617837225u, 3943577151u, 1913087877u, 83908371u, + /* 200 -- */ 2512341634u, 3803740692u, 2075208622u, 213261112u, + /* 204 -- */ 2463272603u, 3855990285u, 2094854071u, 198958881u, + /* 208 -- */ 2262029012u, 4057260610u, 1759359992u, 534414190u, + /* 212 -- */ 2176718541u, 4139329115u, 1873836001u, 414664567u, + /* 216 -- */ 2282248934u, 4279200368u, 1711684554u, 285281116u, + /* 220 -- */ 2405801727u, 4167216745u, 1634467795u, 376229701u, + /* 224 -- */ 2685067896u, 3608007406u, 1308918612u, 956543938u, + /* 228 -- */ 2808555105u, 3495958263u, 1231636301u, 1047427035u, + /* 232 -- */ 2932959818u, 3654703836u, 1088359270u, 936918000u, + /* 236 -- */ 2847714899u, 3736837829u, 1202900863u, 817233897u, + /* 240 -- */ 3183342108u, 3401237130u, 1404277552u, 615818150u, + /* 244 -- */ 3134207493u, 3453421203u, 1423857449u, 601450431u, + /* 248 -- */ 3009837614u, 3294710456u, 1567103746u, 711928724u, + /* 252 -- */ 3020668471u, 3272380065u, 1510334235u, 755167117u + +}; + +/* + ====================================================================== + Prototypes + ====================================================================== +*/ + +STATIC unsigned long ubootenv_crc32( unsigned char *, unsigned long ); +STATIC int ubootenv_initialize( void ); +STATIC void ubootenv_finalize( void ); +STATIC int ubootenv_update( void ); +STATIC int ubootenv_read( struct mtd_info *, size_t, void * ); +STATIC int ubootenv_write( struct mtd_info *, size_t, void * ); + +/* + ====================================================================== + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + ubootenv_crc32 +*/ + +STATIC unsigned long +ubootenv_crc32( unsigned char * start, unsigned long size ) +{ + + unsigned long crc = ( unsigned long ) 0xffffffff, index; + + DEBUG_PRINT( "start=0x%lx size=0x%lx\n", (unsigned long) start, size ); + + for( index = 0; index < size; index ++ ) { + + unsigned long temp = ( crc ^ * ( start ++ ) ) & 0x000000ff; + crc = ( ( crc >> 8 ) & 0x00ffffff ) ^ crc32_lut [ temp ]; + + } + + return ~ crc; + +} + +#ifdef DEBUG_EXPORT_SYMBOLS +EXPORT_SYMBOL( ubootenv_crc32 ); +#endif /* DEBUG_EXPORT_SYMBOLS */ + +/* + ---------------------------------------------------------------------- + ubootenv_read +*/ + +STATIC int +ubootenv_read(struct mtd_info *mtd, size_t size, void *buffer) +{ + int read = 0; + loff_t offset = 0; + + DEBUG_PRINT("size=0x%x mtd->erasesize=0x%x mtd->size=0x%llx\n", + size, mtd->erasesize, mtd->size); + + if( 0 != size % mtd->erasesize ) { + ERROR_PRINT( "size=%u/%llu is not a multiple of erasesize=%u\n", + size, mtd->size, mtd->erasesize ); + return -1; + } + + if( size > mtd->size ) { + ERROR_PRINT( "size=%llu can't contain size=%u\n", + mtd->size, size ); + return -1; + } + + while( ( read < size ) && ( offset < mtd->size ) ) { + int return_code; + size_t bytes_read; + + DEBUG_PRINT("read=0x%x size=0x%x offset=0x%llx\n", + read, size, offset); + + if( 0 != mtd->block_isbad( mtd, offset ) ) { + offset += mtd->erasesize; + continue; + } + + return_code = mtd->read( mtd, offset, mtd->erasesize, + & bytes_read, ( u_char * ) buffer ); + + if( mtd->erasesize != bytes_read ) { + ERROR_PRINT( "Error Reading Environment!\n" ); + return -1; + } + + offset += mtd->erasesize; + read += mtd->erasesize; + buffer += mtd->erasesize; + } + + return 0; +} + +#ifdef DEBUG_EXPORT_SYMBOLS +EXPORT_SYMBOL( ubootenv_read ); +#endif /* DEBUG_EXPORT_SYMBOLS */ + +/* + ---------------------------------------------------------------------- + ubootenv_write +*/ + +STATIC int +ubootenv_write( struct mtd_info * mtd, size_t size, void * buffer ) +{ + DEBUG_PRINT( "Erasing %s\n", mtd->name ); + return 0; +} + +#ifdef DEBUG_EXPORT_SYMBOLS +EXPORT_SYMBOL( ubootenv_write ); +#endif /* DEBUG_EXPORT_SYMBOLS */ + +/* + ---------------------------------------------------------------------- + ubootenv_initialize +*/ + +STATIC int +ubootenv_initialize( void ) +{ + environment_t * env0; + environment_t * env1; + unsigned long crc32_env0; + unsigned long crc32_env1; + struct mtd_info * mtd_env0; + struct mtd_info * mtd_env1; + + DEBUG_PRINT( "Getting MTD Devices.\n" ); + + if( ( struct mtd_info * ) -ENODEV == + ( mtd_env0 = get_mtd_device_nm( "env-0" ) ) ) { + ERROR_PRINT( " --> Couldn't get MTD device by name!\n" ); + return -1; + } + + if( ( struct mtd_info * ) -ENODEV == + ( mtd_env1 = get_mtd_device_nm( "env-1" ) ) ) { + ERROR_PRINT( " --> Couldn't get MTD device by name!\n" ); + return -1; + } + + /* + If the erasesize is larger than the size of the environment, + change the environment size (so reading and writing will + work as expected) but use the original environment size to + calculate the checksum. + */ + + if (mtd_env0->erasesize > uboot_env_size) + uboot_env_size = mtd_env0->erasesize; + + DEBUG_PRINT( "Allocating Environment Buffers.\n" ); + + if( ( environment_t * ) 0 == + ( env0 = ( environment_t * ) vmalloc( uboot_env_size ) ) ) { + ERROR_PRINT( "Unable to allocate %lu bytes\n", uboot_env_size ); + return -1; + } + + if( ( environment_t * ) 0 == + ( env1 = ( environment_t * ) vmalloc( uboot_env_size ) ) ) { + ERROR_PRINT( "Unable to allocate %lu bytes\n", uboot_env_size ); + vfree( ( void * ) env0 ); + return -1; + } + + DEBUG_PRINT( "Reading Environments.\n" ); + + if( 0 != ubootenv_read( mtd_env0, uboot_env_size, env0 ) ) { + return -1; + } + + if( 0 != ubootenv_read( mtd_env1, uboot_env_size, env1 ) ) { + return -1; + } + + DEBUG_PRINT( "Calculating CRC values.\n" ); + crc32_env0 = ubootenv_crc32((unsigned char *)env0->data, + ENVIRONMENT_DATA_SIZE(uboot_env_cs_size)); + crc32_env1 = ubootenv_crc32((unsigned char *)env1->data, + ENVIRONMENT_DATA_SIZE(uboot_env_cs_size)); + DEBUG_PRINT( "crc32_env0=0x%lx env0->crc32=0x%lx\n", + crc32_env0, env0->crc32); + DEBUG_PRINT( "crc32_env2=0x%lx env1->crc32=0x%lx\n", + crc32_env1, env1->crc32); + DEBUG_PRINT( "Picking a Copy.\n" ); + + if( ( crc32_env0 == env0->crc32 ) && + ( crc32_env1 != env1->crc32 ) ) { + /* Use env0 */ + DEBUG_PRINT( "Using Copy 0.\n" ); + uboot_env_current = 0; + vfree( ( void * ) env1 ); + environment = env0; + } else if( ( crc32_env0 != env0->crc32 ) && + ( crc32_env1 == env1->crc32 ) ) { + /* Use env1 */ + DEBUG_PRINT( "Using Copy 1.\n" ); + uboot_env_current = 1; + vfree( ( void * ) env0 ); + environment = env1; + } else if( ( crc32_env0 != env0->crc32 ) && + ( crc32_env1 != env1->crc32 ) ) { + /* No Environment Available */ + uboot_env_current = -1; + vfree( ( void * ) env0 ); + vfree( ( void * ) env1 ); + ERROR_PRINT( "Bad CRCs: No Valid U-Boot Environment Found!\n" ); + return -1; + } else if( env0->flags > env1->flags ) { + /* Use env0 */ + DEBUG_PRINT( "Using Copy 0.\n" ); + uboot_env_current = 0; + vfree( ( void * ) env1 ); + environment = env0; + } else if( env0->flags < env1->flags ) { + /* Use env1 */ + DEBUG_PRINT( "Using Copy 1.\n" ); + uboot_env_current = 1; + vfree( ( void * ) env0 ); + environment = env1; + } else if( env0->flags == env1->flags ) { + /* Use Either */ + DEBUG_PRINT( "Using Copy 0.\n" ); + uboot_env_current = 0; + vfree( ( void * ) env1 ); + environment = env0; + } else { + /* No Environment Available */ + uboot_env_current = -1; + vfree( ( void * ) env0 ); + vfree( ( void * ) env1 ); + ERROR_PRINT( "Bad Flags: No Valid U-Boot Environment Found!\n" ); + return -1; + } + + DEBUG_PRINT( "Done...\n" ); + return 0; + +} + +#ifdef DEBUG_EXPORT_SYMBOLS +EXPORT_SYMBOL( ubootenv_initialize ); +#endif /* DEBUG_EXPORT_SYMBOLS */ + +/* + ---------------------------------------------------------------------- + ubootenv_update +*/ + +STATIC int +ubootenv_update( void ) +{ + if( NULL == environment ) { + ERROR_PRINT( "No Environment Available to Write.\n" ); + return -1; + } + + if( -1 == uboot_env_current ) { + ERROR_PRINT( "Environment Copy Selection is Invalid.\n" ); + return -1; + } + + if( 0 == uboot_env_current ) { + DEBUG_PRINT( "Saving Environment in Copy 1.\n" ); + } else { + DEBUG_PRINT( "Saving Environment in Copy 0.\n" ); + } + + return 0; +} + +#ifdef DEBUG_EXPORT_SYMBOLS +EXPORT_SYMBOL( ubootenv_update ); +#endif /* DEBUG_EXPORT_SYMBOLS */ + +/* + ---------------------------------------------------------------------- + ubootenv_finalize +*/ + +STATIC void +ubootenv_finalize( void ) +{ + DEBUG_PRINT( "Freeing the environment.\n" ); + + if( ( void * ) 0 != environment ) { + vfree( ( void * ) environment ); + } + + environment = ( environment_t * ) 0; +} + +#ifdef DEBUG_EXPORT_SYMBOLS +EXPORT_SYMBOL( ubootenv_finalize ); +#endif /* DEBUG_EXPORT_SYMBOLS */ + +/* + ====================================================================== + Public Interface + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + ubootenv_get +*/ + +int +ubootenv_get( const char * key, char * value ) +{ + int return_code = -1; + char * string; + + if( NULL == environment ) { + ERROR_PRINT( "Environment Isn't Available!\n" ); + return -1; + } + + string = environment->data; + + while( 0x00 != string [ 0 ] ) { + + if( 0 == strncmp( key, string, strlen( key ) ) ) { + char * value_ = strchr( string, '=' ); + ++ value_; + strcpy( value, value_ ); + return_code = 0; + break; + } + + string += ( strlen( string ) + 1 ); + } + + return return_code; +} + +/* + ====================================================================== + ====================================================================== + Linux Module Stuff + ====================================================================== + ====================================================================== +*/ + +/* + ---------------------------------------------------------------------- + ubootenv_module_init +*/ + +int __init +ubootenv_module_init( void ) +{ + DEBUG_PRINT( "\n" ); + return ubootenv_initialize( ); +} + +module_init( ubootenv_module_init ); + +/* + ---------------------------------------------------------------------- + ubootenv_module_exit +*/ + +void __exit +ubootenv_module_exit( void ) +{ + DEBUG_PRINT( "\n" ); + ubootenv_finalize( ); + return; +} + +module_exit( ubootenv_module_exit ); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR( "John Jacques " ); +MODULE_DESCRIPTION("Read Access of the U-Boot Environment"); diff --git a/drivers/lsi/acp/version.c b/drivers/lsi/acp/version.c new file mode 100644 index 0000000..6c193c7 --- /dev/null +++ b/drivers/lsi/acp/version.c @@ -0,0 +1,347 @@ +/* + * version.c + * + * Copyright (C) 2010 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 021_2_6.17 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/debug.h" +#include "../common/version.h" +#include "ncr.h" + +#undef TLBERRORCOUNTER +/*#define TLBERRORCOUNTER*/ +#ifdef TLBERRORCOUNTER +unsigned long dtlb_misses = 0; +unsigned long itlb_misses = 0; +#endif + +extern int ubootenv_get(const char *, char *); + +/* + MODULE +*/ + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Information about the Agere APP3xx"); + +/* + */ + +unsigned agere_app3xx_revision; +EXPORT_SYMBOL(agere_app3xx_revision); + +/* + ---------------------------------------------------------------------- + timer_test_ +*/ + +#ifdef TIMER_TEST + +static void +timer_test_(void) +{ + const int first_timer_ = 0; + const int last_timer_ = 7; + int timer_; + unsigned long timer_base_[] = { + TIMER0_BASE, TIMER1_BASE, TIMER2_BASE, TIMER3_BASE, + TIMER4_BASE, TIMER5_BASE, TIMER6_BASE, TIMER7_BASE + }; + + { + const int number_of_reads_ = 200; + unsigned long time_[number_of_reads_]; + int index_; + + for (index_ = 0; index_ < number_of_reads_; ++index_) + time_[index_] = ~(readl((TIMER0_BASE + TIMER_n_VALUE))); + + for (index_ = 0; index_ < number_of_reads_; ++index_) { + printk(KERN_INFO "%03d : 0x%08x\n", index_, time_[index_]); + + if (0 < index_) { + if (time_[index_] <= time_[(index_ - 1)]) { + printk(KERN_ERR "WHAT!\n"); + } + } + } + } + + for (timer_ = first_timer_; timer_ <= last_timer_; ++timer_) { + unsigned long base_ = timer_base_[timer_]; + + printk(KERN_INFO "load value=0x%x control=0x%x background load=0x%x\n", + readl((base_ + TIMER_n_LOAD)), + readl((base_ + TIMER_n_CONTROL)), + readl((base_ + TIMER_n_BACKGROUND_LOAD))); + } +} + +#endif /* TIMER_TEST */ + +#ifdef SHMEM_TEST + +/* + ---------------------------------------------------------------------- + shmem_test +*/ + +void +shmem_test(void) +{ + void __iomem *cached_shmem; + void __iomem *uncached_shmem; + unsigned i; + unsigned long start_time; + + uncached_shmem = ioremap_nocache(APP3K_PHYS_SHMEM_BASE, PAGE_SZ); + cached_shmem = ioremap_cached(APP3K_PHYS_SHMEM_BASE + PAGE_SZ, + APP_SHMEM_SIZE - PAGE_SZ); + + if ((void __iomem *) 0 == cached_shmem) { + printk(KERN_ERR "Unable to map shmem as cached IO\n"); + return; + } + + printk("cached_shmem=0x%08p shmem=0x%08x uncached_shmem=0x%08p\n", + cached_shmem, APP_SHMEM_BASE, uncached_shmem); + +#if 0 + i = 0; + start_time = jiffies; + while (jiffies == start_time) + ; + start_time = jiffies; + while (jiffies == start_time) { + + unsigned j; + unsigned char * dest = (unsigned char *) APP_SHMEM_BASE; + + for (j = 0; j < APP_SHMEM_SIZE; ++j, ++dest) { + *dest = j; + } + + ++i; + } + + printk("%d iterations uncached\n", i); + + i = 0; + start_time = jiffies; + while (jiffies == start_time) + ; + start_time = jiffies; + while (jiffies == start_time) { + unsigned j; + unsigned char * dest = (unsigned char *) cached_shmem; + + for (j = 0; j < APP_SHMEM_SIZE; ++j, ++dest) { + *dest = j; + } + + ++i; + } + + printk(KERN_INFO "%d iterations cached\n", i); +#endif + + return; +} + +#endif /* SHMEM_TEST */ + +#ifdef TLBERRORCOUNTER + +static int +tlberror_create_string(char *buffer) +{ + int length = 0; + + length = sprintf(buffer, + "Data TLB Errors: %d\n" + "Instruction TLB Errors: %d\n", + dtlb_misses, itlb_misses); + + return length; +} + +/* + ---------------------------------------------------------------------- + tlberror_read_proc +*/ + +static int +tlberror_read_proc(char *page, char **start, off_t offset, + int count, int *eof, void *data) +{ + int length = 0; + + length = tlberror_create_string(page); + *eof = 1; + + return length; +} + +#endif /* TLBERRORCOUNTER */ + +/* + ------------------------------------------------------------------------------ + is_asic +*/ + +int +is_asic(void) +{ +#ifdef CONFIG_ACPISS + return 0; +#else +#if 1 + unsigned long nca_config; + + if (0 == ncr_read(NCP_REGION_ID(0x16, 0xff), 0x10, 4, &nca_config)) { + return (0 == (nca_config & 0x80000000)); + } + + return -1; +#else + printk("%s:%s:%d - Writing 0x%x to 0x%x (NCA=0x%x)\n", + __FILE__, __FUNCTION__, __LINE_, + value, address, NCA); /* ZZZ */ + return 0; +#endif +#endif +} + +/* + ---------------------------------------------------------------------- + info_create_string +*/ + +static int +info_create_string(char *buffer) +{ + int length = 0; + char uboot_version2[80]; + char uboot_version3[80]; + +#ifdef CONFIG_ACPISS + sprintf(uboot_version2, "Unknown"); + sprintf(uboot_version3, "Unknown"); +#else + if (0 != ubootenv_get("version2", uboot_version2)) { + sprintf(uboot_version2, "Unknown"); + } + + if (0 != ubootenv_get("version3", uboot_version3)) { + sprintf(uboot_version3, "Unknown"); + } +#endif + + length = sprintf(buffer, + "LSI ACP Info\n" \ + "LSI Version %s\n" \ + "Platform: %s\n" \ + "U-Boot Version (2nd Stage) %s\n" \ + "U-Boot Version (3rd Stage) %s\n", + ACP_VERSION, (is_asic() ? "ASIC" : "FPGA"), + uboot_version2, uboot_version3); + + /* that's all */ + return length; + +} + +/* + ---------------------------------------------------------------------- + info_read_proc +*/ + +static int +info_read_proc(char *page, char **start, off_t offset, + int count, int *eof, void *data) +{ + int length_ = 0; + +#ifdef SHMEM_TEST + shmem_test(); +#endif /* SHMEM_TEST */ + +#ifdef TIMER_TEST + timer_test_(); +#endif /* TIMER_TEST */ + +#if !defined(SHMEM_TEST) && !defined(TIMER_TEST) + length_ = info_create_string(page); +#endif + *eof = 1; + + return length_; +} + +/* + ---------------------------------------------------------------------- + info_module_init +*/ + +int __init +info_module_init(void) +{ + + char buffer_[256]; + + create_proc_read_entry("driver/version", 0, NULL, info_read_proc, NULL); + info_create_string(buffer_); + printk("%s", buffer_); + +#ifdef TLBERRORCOUNTER + create_proc_read_entry("driver/tlberrors", + 0, NULL, tlberror_read_proc, NULL); +#endif + + return 0; + +} + +module_init(info_module_init); + +/* + ---------------------------------------------------------------------- + info_module_exit +*/ + +void __exit +info_module_exit(void) +{ +#ifdef TLBERRORCOUNTER + remove_proc_entry("driver/tlberrors", NULL); +#endif + remove_proc_entry("driver/version", NULL); + + return; +} + +module_exit(info_module_exit); diff --git a/drivers/lsi/acp/wrappers.c b/drivers/lsi/acp/wrappers.c new file mode 100644 index 0000000..be9b663 --- /dev/null +++ b/drivers/lsi/acp/wrappers.c @@ -0,0 +1,257 @@ +/* + * drivers/lsi/acp/wrappers.c + * + * Copyright (C) 2010 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +extern int is_asic(void); +extern int acp_clock_get(int, unsigned long *); + +/* + ============================================================================== + ============================================================================== + MDIO Access + ============================================================================== + ============================================================================== +*/ + +#ifndef CONFIG_ACPISS + +#undef BZ33327_WA +#define BZ33327_WA + +static unsigned long mdio_base; +DEFINE_SPINLOCK(mdio_lock); + +#define MDIO_CONTROL_RD_DATA ((void *)(mdio_base + 0x0)) +#define MDIO_STATUS_RD_DATA ((void *)(mdio_base + 0x4)) +#define MDIO_CLK_OFFSET ((void *)(mdio_base + 0x8)) +#define MDIO_CLK_PERIOD ((void *)(mdio_base + 0xc)) + +/* + ------------------------------------------------------------------------------ + acp_mdio_read +*/ + +int +acp_mdio_read(unsigned long address, unsigned long offset, unsigned short *value) +{ + unsigned long command = 0; + unsigned long status; + unsigned long flags; + + spin_lock_irqsave(&mdio_lock, flags); +#if defined(BZ33327_WA) + /* Set the mdio_busy (status) bit. */ + status = in_le32(MDIO_STATUS_RD_DATA); + status |= 0x40000000; + out_le32(MDIO_STATUS_RD_DATA, status); +#endif /* BZ33327_WA */ + + /* Write the command.*/ + command |= 0x10000000; /* op_code: read */ + command |= (address & 0x1f) << 16; /* port_addr (target device) */ + command |= (offset & 0x1f) << 21; /* device_addr (target register) */ + out_le32(MDIO_CONTROL_RD_DATA, command); + +#if defined(BZ33327_WA) + /* Wait for the mdio_busy (status) bit to clear. */ + do { + status = in_le32(MDIO_STATUS_RD_DATA); + } while (0 != (status & 0x40000000)); + + /* Wait for the mdio_busy (control) bit to clear. */ + do { + command = in_le32(MDIO_CONTROL_RD_DATA); + } while(0 != (command & 0x80000000)); + + *value = (unsigned short)(command & 0xffff); +#endif /* BZ33327_WA */ + spin_unlock_irqrestore(&mdio_lock, flags); + + return 0; +} + +EXPORT_SYMBOL(acp_mdio_read); + +/* + ------------------------------------------------------------------------------ + acp_mdio_write +*/ + +int +acp_mdio_write(unsigned long address, unsigned long offset, unsigned short value) +{ + unsigned long command = 0; + unsigned long status; + unsigned long flags; + + spin_lock_irqsave(&mdio_lock, flags); + + /* Wait for mdio_busy (control) to be clear. */ + do { + command = in_le32(MDIO_CONTROL_RD_DATA); + } while (0 != (command & 0x80000000)); + +#if defined(BZ33327_WA) + /* Set the mdio_busy (status) bit. */ + status = in_le32(MDIO_STATUS_RD_DATA); + status |= 0x40000000; + out_le32(MDIO_STATUS_RD_DATA, status); +#endif /* BZ33327_WA */ + + /* Write the command. */ + command = 0x08000000; /* op_code: write */ + command |= (address & 0x1f) << 16; /* port_addr (target device) */ + command |= (offset & 0x1f) << 21; /* device_addr (target register) */ + command |= (value & 0xffff); /* value */ + out_le32(MDIO_CONTROL_RD_DATA, command); + +#if defined(BZ33327_WA) + /* Wait for the mdio_busy (status) bit to clear. */ + do { + status = in_le32(MDIO_STATUS_RD_DATA); + } while (0 != (status & 0x40000000)); +#endif /* BZ33327_WA */ + + /* Wait for the mdio_busy (control) bit to clear. */ + do { + command = in_le32(MDIO_CONTROL_RD_DATA); + } while (0 != (command & 0x80000000)); + + spin_unlock_irqrestore(&mdio_lock, flags); + + return 0; +} + +EXPORT_SYMBOL(acp_mdio_write); + +/* + ------------------------------------------------------------------------------ + acp_mdio_initialize +*/ + +static int +acp_mdio_initialize(void) +{ + if (is_asic()) { + out_le32(MDIO_CLK_OFFSET, 0x10); + out_le32(MDIO_CLK_PERIOD, 0x2c); + } else { + out_le32(MDIO_CLK_OFFSET, 0x05); + out_le32(MDIO_CLK_PERIOD, 0x0c); + } + + return 0; +} + +#endif /* CONFIG_ACPISS */ + +/* + ============================================================================== + ============================================================================== + Interrupts + ============================================================================== + ============================================================================== +*/ + +/* + ------------------------------------------------------------------------------ + acp_irq_create_mapping +*/ + +unsigned int +acp_irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq) +{ + return irq_create_mapping(host, hwirq); +} + +EXPORT_SYMBOL(acp_irq_create_mapping); + +/* + ------------------------------------------------------------------------------ + acp_wrappers_init +*/ + +int __init +acp_wrappers_init(void) +{ + int rc = -1; + struct device_node *np = NULL; + const u32 *field; + u64 mdio_phys_address; + u32 mdio_size; + + printk(KERN_INFO "Initializing ACP Wrappers.\n"); + +#ifndef CONFIG_ACPISS + np = of_find_node_by_type(np, "network"); + + while (np && !of_device_is_compatible(np, "acp-femac")) + np = of_find_node_by_type(np, "network"); + + if (np) { + field = of_get_property(np, "enabled", NULL); + + if (!field || (field && (0 == *field))) { + printk(KERN_WARNING + "Networking is Not Enabled.\n"); + goto acp_wrappers_init_done; + } + + field = of_get_property(np, "mdio-reg", NULL); + + if (!field) { + printk(KERN_ERR + "Couldn't get \"mdio-reg\" property.\n"); + } else { + mdio_phys_address = of_translate_address(np, field); + mdio_size = field[1]; + rc = 0; + } + } + + if (0 != rc) { + mdio_phys_address = 0x002000409000ULL; + mdio_size = 0x1000; + printk(KERN_WARNING + "** MDIO Address Not Specified in Device Tree.\n"); + } + + mdio_base = ioremap(mdio_phys_address, mdio_size); + rc = acp_mdio_initialize(); +#endif + + if (0 != rc) + printk(KERN_ERR, "MDIO Initiailzation Failed!\n"); + + acp_wrappers_init_done: + + return 0; +} + +module_init(acp_wrappers_init); + +MODULE_AUTHOR("LSI Corporation"); +MODULE_DESCRIPTION("Timing Test"); +MODULE_LICENSE("GPL"); diff --git a/drivers/lsi/common/debug.h b/drivers/lsi/common/debug.h new file mode 100644 index 0000000..71581e9 --- /dev/null +++ b/drivers/lsi/common/debug.h @@ -0,0 +1,63 @@ +/* + * drivers/acp/common/debug.h + * + * Copyright (C) 2010 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __DRIVERS_LSI_COMMON_DEBUG_H +#define __DRIVERS_LSI_COMMON_DEBUG_H + +/* + DEBUG +*/ + +#if defined(DEBUG) +#define DEBUG_PRINT(format, args...) do { \ +printk("%s:%s:%d - DEBUG - ", __FILE__, __FUNCTION__, __LINE__); \ +printk(format, ##args); \ +} while (0); +#else +#define DEBUG_PRINT(format, args...) { } +#endif + +/* + WARN +*/ + +#if defined(WARN) +#define WARN_PRINT(format, args...) do { \ +printk("%s:%s:%d - WARN - ", __FILE__, __FUNCTION__, __LINE__); \ +printk(format, ##args); \ +} while (0); +#else +#define WARN_PRINT(format, args...) { } +#endif + +/* + ERROR +*/ + +#if defined(ERROR) +#define ERROR_PRINT(format, args...) do { \ +printk("%s:%s:%d - ERROR - ", __FILE__, __FUNCTION__, __LINE__); \ +printk(format, ##args); \ +} while (0); +#else +#define ERROR_PRINT(format, args...) { } +#endif + +#endif /* __DRIVERS_LSI_COMMON_DEBUG_H */ diff --git a/drivers/lsi/common/version.h b/drivers/lsi/common/version.h new file mode 100644 index 0000000..a79d452 --- /dev/null +++ b/drivers/lsi/common/version.h @@ -0,0 +1,28 @@ +/* + * drivers/lsi/common/version.h + * + * Copyright (C) 2009 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __DRIVERS_ACP_VERSION_H +#define __DRIVERS_ACP_VERSION_H + +#define ACP_VERSION "3.8.1.22" + +int is_asic(void); + +#endif /* __DRIVERS_ACP_VERSION_H */ diff --git a/drivers/mtd/devices/phram.c b/drivers/mtd/devices/phram.c index 23423bd..f5be315 100644 --- a/drivers/mtd/devices/phram.c +++ b/drivers/mtd/devices/phram.c @@ -288,6 +288,7 @@ MODULE_PARM_DESC(phram, "Memory region to map. \"phram=,,\" static int __init init_phram(void) { + printk("%s:%d - \n", __FILE__, __LINE__); /* ZZZ */ return 0; } diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index a46e9bb..77b7a5a 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -30,6 +30,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com */ #include @@ -49,6 +50,36 @@ #include #include +#ifdef CONFIG_LSI_NAND +#define LSI_NAND_BASE 0xf0040000 +#define NAND_DATA_REG 0x00000000 +#define NAND_CMD_REG 0x00008000 +#define NAND_INDEX_REG 0x00008004 +#define NAND_STATUS1_REG 0x00008008 +#define NAND_STATUS2_REG 0x0000800C +#define NAND_ID0_REG 0x00008010 +#define NAND_ID1_REG 0x00008014 +#define NAND_ID2_REG 0x00008018 +#define NAND_ID3_REG 0x0000801C +#define NAND_ID4_REG 0x00008020 +#define NAND_ID5_REG 0x00008024 +#define NAND_ID6_REG 0x00008028 +#define NAND_ID7_REG 0x0000802C +#define NAND_INTR_EN_REG 0x00008030 +#define NAND_INTR_STATUS_REG 0x00008034 +#define NAND_INTR_REG 0x00008038 +#define NAND_ECC_ADDR_LOG_REG 0x0000803C +#define NAND_ECC_VAL_REG 0x00008040 +#define NAND_ECC_INJECT_REG 0x00008044 +#define NAND_EXT_INDEX_REG 0x00008048 +#define NAND_TIMING1_REG 0x0000804C +#define NAND_TIMING2_REG 0x00008050 +#define NAND_CONFIG_REG 0x00008054 +#define NAND_PECC_REG 0x00008058 + +extern lsi_nand_set_config(struct mtd_info *, struct nand_chip *); +#endif /* CONFIG_LSI_NAND */ + /* Define default oob placement schemes for large and small page devices */ static struct nand_ecclayout nand_oob_8 = { .eccbytes = 3, @@ -458,7 +489,12 @@ static int nand_check_wp(struct mtd_info *mtd) /* Check the WP bit */ chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); +#ifdef CONFIG_LSI_NAND + return (readl(chip->IO_ADDR_R + NAND_STATUS1_REG) & + NAND_STATUS_WP) ? 0 : 1; +#else return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; +#endif } /** @@ -2645,6 +2681,12 @@ erase_exit: /* Deselect and wake up anyone waiting on the device */ nand_release_device(mtd); +#ifdef CONFIG_LSI_NAND + /* if erase failed for a block, mark it as bad block */ + if (status & NAND_STATUS_FAIL) + mtd->block_markbad(mtd, page << chip->page_shift); +#endif /* CONFIG_LSI_NAND */ + /* Do call back function */ if (!ret) mtd_erase_callback(instr); @@ -2921,9 +2963,13 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read manufacturer and device IDs */ +#ifdef CONFIG_LSI_NAND + *maf_id = readb(chip->IO_ADDR_R + NAND_ID0_REG); + *dev_id = readb(chip->IO_ADDR_R + NAND_ID2_REG); +#else /* CONFIG_LSI_NAND */ *maf_id = chip->read_byte(mtd); *dev_id = chip->read_byte(mtd); - +#endif /* LSI_NAND */ /* Try again to make sure, as some systems the bus-hold or other * interface concerns can cause random data which looks like a * possibly credible NAND flash to appear. If the two results do @@ -2932,9 +2978,13 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); +#ifdef CONFIG_LSI_NAND + id_data[0] = readb(chip->IO_ADDR_R + NAND_ID0_REG); + id_data[1] = readb(chip->IO_ADDR_R + NAND_ID2_REG); +#else for (i = 0; i < 2; i++) id_data[i] = chip->read_byte(mtd); - +#endif if (id_data[0] != *maf_id || id_data[1] != *dev_id) { printk(KERN_INFO "%s: second ID read did not match " "%02x,%02x against %02x,%02x\n", __func__, @@ -2961,8 +3011,15 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Read entire ID string */ +#ifdef CONFIG_LSI_NAND + id_data[0] = readb(chip->IO_ADDR_R + NAND_ID0_REG); + id_data[1] = readb(chip->IO_ADDR_R + NAND_ID2_REG); + id_data[2] = readb(chip->IO_ADDR_R + NAND_ID4_REG); + id_data[3] = readb(chip->IO_ADDR_R + NAND_ID6_REG); +#else for (i = 0; i < 8; i++) id_data[i] = chip->read_byte(mtd); +#endif if (!type->name) return ERR_PTR(-ENODEV); @@ -2977,11 +3034,18 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, busw = chip->init_size(mtd, chip, id_data); } else if (!type->pagesize) { int extid; +#ifdef CONFIG_LSI_NAND + /* dimka: move this out to chip->init_size */ + /* The 3rd id byte holds MLC / multichip data */ + chip->cellinfo = readb(chip->IO_ADDR_R + NAND_ID4_REG); + /* The 4th id byte is the important one */ + extid = readb(chip->IO_ADDR_R + NAND_ID6_REG); +#else /* CONFIG_LSI_NAND */ /* The 3rd id byte holds MLC / multichip data */ chip->cellinfo = id_data[2]; /* The 4th id byte is the important one */ extid = id_data[3]; - +#endif /* * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) @@ -3018,6 +3082,18 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, (((extid >> 1) & 0x04) | (extid & 0x03)); busw = 0; } else { + /* Add workaournd for Micron MT29Fxxxxxx NAND flash*/ + if (id_data[0] == NAND_MFR_MICRON && id_data[1] == 0x48) { + /* Calc pagesize */ + mtd->writesize = 1024 << (extid & 0x03); + extid >>= 2; + /*Calc oobsize */ + mtd->oobsize = ((extid & 0x03) == 0x03) ? 218: 224; + extid >>= 3; + /* Calc blocksize. Blocksize is multiples of 256KiB */ + mtd->erasesize = (256 * 1024) << (extid & 0x03); + busw = 0; + }else{ /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); extid >>= 2; @@ -3030,6 +3106,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, extid >>= 2; /* Get buswidth information */ busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + } } } else { /* @@ -3069,6 +3146,11 @@ ident_done: */ chip->options |= NAND_NO_AUTOINCR; +#ifdef CONFIG_LSI_NAND + /* Set the EP501/EP501G1 config register. */ + lsi_nand_set_config(mtd, chip); +#endif /* CONFIG_LSI_NAND */ + /* Try to identify manufacturer */ for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { if (nand_manuf_ids[maf_idx].id == *maf_id) diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 00cf1b0..9e9b85b 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -114,6 +114,7 @@ struct nand_flash_dev nand_flash_ids[] = { {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + {"NAND 2GiB 3,3V 16-bit", 0x48, 0, 2048, 0, LP_OPTIONS}, /* 32 Gigabit */ {"NAND 4GiB 1,8V 8-bit", 0xA7, 0, 4096, 0, LP_OPTIONS}, diff --git a/drivers/rapidio/Kconfig b/drivers/rapidio/Kconfig index 070211a..0ab0efe 100644 --- a/drivers/rapidio/Kconfig +++ b/drivers/rapidio/Kconfig @@ -20,6 +20,8 @@ config RAPIDIO_ENABLE_RX_TX_PORTS ports for Input/Output direction to allow other traffic than Maintenance transfers. +source "drivers/rapidio/mports/Kconfig" + source "drivers/rapidio/switches/Kconfig" config RAPIDIO_DEBUG diff --git a/drivers/rapidio/Makefile b/drivers/rapidio/Makefile index 89b8eca..2951859 100644 --- a/drivers/rapidio/Makefile +++ b/drivers/rapidio/Makefile @@ -4,5 +4,6 @@ obj-y += rio.o rio-access.o rio-driver.o rio-scan.o rio-sysfs.o obj-$(CONFIG_RAPIDIO) += switches/ +obj-$(CONFIG_RAPIDIO) += mports/ subdir-ccflags-$(CONFIG_RAPIDIO_DEBUG) := -DDEBUG diff --git a/drivers/rapidio/mports/Kconfig b/drivers/rapidio/mports/Kconfig new file mode 100644 index 0000000..e72b98b --- /dev/null +++ b/drivers/rapidio/mports/Kconfig @@ -0,0 +1,23 @@ +# +# RapidIO master port configuration +# + +config RAPIDIO_ACP + bool "Support ACP Internal RapidIO endpoint" + depends on RAPIDIO + default "y" + ---help--- + Include support for ACP RapidIO bridge as a RapidIO master port. + +config RAPIDIO_ACP_RX_SIZE + int "Number of inbound message entries" + depends on RAPIDIO_ACP + default "128" + +# FIXME: COMMENTED OUT TO KEEP TSI620 BUILD AS AN EXTERNAL MODULE ONLY +# config RAPIDIO_TSI620 +# bool "Support Tsi620 PCI RapidIO endpoint" +# depends on RAPIDIO +# default "y" +# ---help--- +# Include support for Tsi620 PCI-RapidIO bridge as a RapidIO master port. diff --git a/drivers/rapidio/mports/Makefile b/drivers/rapidio/mports/Makefile new file mode 100644 index 0000000..a12148d --- /dev/null +++ b/drivers/rapidio/mports/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for RapidIO interconnect services +# +#obj-$(CONFIG_RAPIDIO_ACP) += acp/ +obj-$(CONFIG_RAPIDIO_TSI620) += tsi620/ diff --git a/drivers/rapidio/mports/tsi620/Makefile b/drivers/rapidio/mports/tsi620/Makefile new file mode 100644 index 0000000..7db9008 --- /dev/null +++ b/drivers/rapidio/mports/tsi620/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for RapidIO master ports +# + +# FIXME: Out of the tree build only (for now) +obj-$(CONFIG_RAPIDIO_TSI620) += tsi620.o diff --git a/drivers/rapidio/mports/tsi620/tsi620.c b/drivers/rapidio/mports/tsi620/tsi620.c new file mode 100644 index 0000000..48bc4a6 --- /dev/null +++ b/drivers/rapidio/mports/tsi620/tsi620.c @@ -0,0 +1,703 @@ +/* Tsi620 Driver + * + * Copyright 2009, Integrated Device Technology, Inc. + * + * Autor(s): + * Randy Noah (IDT) + * Jason McKenna (Tundra Semiconductor Corp.) + * + * This driver is not a modification of the Linux kernel, however has been + * designed to work with it. For restrictions on use of the driver (as + * either source code or compiled module) including distribution rights, + * please contact IDT. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tsi620.h" + +MODULE_AUTHOR("Randy Noah, Jason McKenna"); +MODULE_DESCRIPTION("Tsi620 PCI/RapidIO Bridge"); +MODULE_VERSION("2.0"); +MODULE_LICENSE("Proprietary"); + +/***************************************************************************** + * Definitions + *****************************************************************************/ + +/* Set this to self-adjust PCI addresses (great for insane bootloaders) */ +#define TSI620_FIX_MAPPING +//#undef TSI620_FIX_MAPPING + +/* Macro used for debugging things. */ +//#define TSI620_DEBUG(_str_, ...) printk(KERN_INFO "(%s:%d) " _str_, __FILE__, __LINE__, ## __VA_ARGS__) +#define TSI620_DEBUG(_str_, ...) + +/***************************************************************************** + * Prototypes + *****************************************************************************/ +extern void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); + +int tsi620_probe(struct pci_dev *dev, const struct pci_device_id *id); +void tsi620_remove(struct pci_dev *dev); +int tsi620_remap_device(struct pci_dev *pdev); +int tsi620_setup_mport(struct pci_dev *pdev); +void tsi620_init_translation(struct pci_dev* dev); +void tsi620_init_p2o_bar2_luts(void); + +/* RIO low level routines */ +int tsi620_lcread (struct rio_mport *mport, int index, u32 offset, int len, + u32 *data); +int tsi620_lcwrite (struct rio_mport *mport, int index, u32 offset, int len, + u32 data); +int tsi620_cread (struct rio_mport *mport, int index, u16 destid, + u8 hopcount, u32 offset, int len, u32 *data); +int tsi620_cwrite (struct rio_mport *mport, int index, u16 destid, + u8 hopcount, u32 offset, int len, u32 data); +int tsi620_dsend (struct rio_mport *mport, int index, u16 destid, u16 data); + +void* tsi620_ioremap(void* rio_address, u16 destid, unsigned int length); +void tsi620_unmap(void* address); + +/***************************************************************************** + * Structures/variables + *****************************************************************************/ +struct tsi620_device *tsi620; + +static struct pci_device_id tsi620_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TSI620) }, + { 0, } /* terminate list */ +}; + +MODULE_DEVICE_TABLE(pci, tsi620_pci_tbl); + +static struct pci_driver tsi620_driver = { + .name = "tsi620", + .id_table = tsi620_pci_tbl, + .probe = tsi620_probe, + .remove = tsi620_remove, +}; + +/***************************************************************************** + * Code + *****************************************************************************/ + +/***************************************************************************** + * Read SREP register + *****************************************************************************/ +int tsi620_lcread (struct rio_mport *mport, int index, u32 offset, int len, + u32 *data) +{ + if (0 == len % 4) + while (len) + { + *data = in_le32((void*)tsi620->srep + offset); + offset += 4; + len -= 4; + } + else + { + TSI620_DEBUG("RIO local read of DWORDs only supported\n"); + return -EINVAL; + } + return 0; +} + +/***************************************************************************** + * Write SREP register + *****************************************************************************/ +int tsi620_lcwrite (struct rio_mport *mport, int index, u32 offset, int len, + u32 data) +{ + if (0 == len % 4) + while (len) + { + out_le32((void*)tsi620->srep + offset, data); + offset += 4; + len -= 4; + } + else + { + TSI620_DEBUG("RIO local write of DWORDs only supported\n"); + return -EINVAL; + } + return 0; +} + + +/***************************************************************************** + * Perform a maint. read from SREP + *****************************************************************************/ +int tsi620_cread (struct rio_mport *mport, int index, u16 destid, + u8 hopcount, u32 offset, int len, u32 *data) +{ + if (hopcount) + { + + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_PTY_CTL), MAINT_BAR_LUT); + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_UPPER), (hopcount << 24) | 0x00f00000 | destid); + + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_LOWER), 0x000000a0); + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_RIO_PARMS), 0x00008081); + *data = in_be32((void*) (tsi620->maint + offset)); + + } + else + { + *data = in_le32((void*) (tsi620->regs + offset)); + } + return 0; +} + +/***************************************************************************** + * Perform a maint. write from SREP + *****************************************************************************/ +int tsi620_cwrite (struct rio_mport *mport, int index, u16 destid, + u8 hopcount, u32 offset, int len, u32 data) +{ + if (hopcount) + { + + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_PTY_CTL), MAINT_BAR_LUT); + + + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_UPPER), (hopcount << 24) | 0x00f00000 | destid); + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_LOWER), 0x000000a0); + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_RIO_PARMS), 0x00008081); + + out_be32((void*) (tsi620->maint + offset), data); + } + else + { + out_le32((void*) (tsi620->regs + offset), data); + } + return 0; +} + +/***************************************************************************** + * Send a doorbell from SREP + *****************************************************************************/ +int tsi620_dsend (struct rio_mport *mport, int index, u16 destid, u16 data) +{ + TSI620_DEBUG("Doorbell\n"); + return 0; +} + +/***************************************************************************** + * Probe for and initialize device + *****************************************************************************/ +int tsi620_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + /* Variables... */ + int rc; + rc = tsi620_remap_device(pdev); + + if (rc) + return rc; + + /* All well and good -- now let's register this as a master port... */ + rc = tsi620_setup_mport(pdev); + + /* Enumerate all registered ports */ + rc = rio_init_mports(); + if (rc) + return rc; + return rc; +} + + +/***************************************************************************** + * Remap IO space + *****************************************************************************/ +int tsi620_remap_device(struct pci_dev *pdev) +{ + /* Location and size of Tsi620 register window (PCI space) */ + unsigned long location; + unsigned long size; + int result; + + tsi620 = (struct tsi620_device *) kmalloc(sizeof(struct tsi620_device), GFP_KERNEL); + memset(tsi620, 0, sizeof(struct tsi620_device)); + + /* Enable the device */ + result = pci_enable_device(pdev); + + +#if defined(TSI620_FIX_MAPPING) + { + /* Some boot loaders will assign 0 bytes of PCI space to BAR0 (rather + * than the required 256KB). This code will check if this is the case, + * and fix both the internal registers as well as the Linux resource + * cache. */ + + TSI620_DEBUG("Checking if mapping adjustment needs to be made...\n"); + + if (pdev->resource[2].start && !(pdev->resource[0].start)) + { + // Linux detected space allocated for BAR2, but not BAR0... + u32 temp; + + TSI620_DEBUG("Fixing...\n"); + + temp = pdev->resource[2].end - pdev->resource[2].start + 1; + temp /= 2; + TSI620_DEBUG("new size of bar2 = 0x%x\n", temp); + + pdev->resource[0].start = pdev->resource[2].start; + pdev->resource[0].end = pdev->resource[0].start + (256 * 1024) - 1; + TSI620_DEBUG("bar0 from = 0x%x to 0x%x\n", pdev->resource[0].start, pdev->resource[0].end); + + pdev->resource[2].start += temp; + TSI620_DEBUG("bar2 from = 0x%x to 0x%x\n", pdev->resource[2].start, pdev->resource[2].end); + + temp = pdev->resource[0].start; + pci_write_config_dword(pdev, 0x10, temp); + + temp = pdev->resource[2].start; + pci_write_config_dword(pdev, 0x18, temp); + + temp = pci_read_config_dword(pdev, 0x4c, &temp); + TSI620_DEBUG("P2O_PAGE_SIZES 0x%x\n", temp); + if (0 == temp) + { + u32 wanted = pdev->resource[2].end - pdev->resource[2].start + 1; + u32 cur = (32 * 1024); + + TSI620_DEBUG("0 value seen -- fixing\n"); + + temp = 0x00000500; + while (cur < wanted) + { + temp += 0x00000800; + cur <<= 1; + } + } + else + { + //reduce space by 1/2 + temp -= 0x00000800; + } + TSI620_DEBUG("New value: 0x%x\n", temp); + pci_write_config_dword(pdev, 0x4c, temp); + + } + + TSI620_DEBUG("updating resource lists...\n"); + pci_update_resource(pdev, &(pdev->resource[0]), 0); + pci_update_resource(pdev, &(pdev->resource[2]), 2); + } +#endif + + /* Ok, try to remap this bad boy */ + location = pci_resource_start (pdev, 0); + size = pci_resource_len(pdev, 0); + + tsi620->regs = (u32) ioremap(location, TSI620_CONFIG_SPACE_SIZE); + + /* Now to remap some memory access space */ + location = pci_resource_start (pdev, 2); + size = pci_resource_len(pdev, 2); + + TSI620_DEBUG("mem location/size = 0x%lx / 0x%lx\n", location, size); + tsi620->i2rBase = location; + tsi620->memSize = size; + + tsi620->base = (u32) ioremap(tsi620->i2rBase, tsi620->memSize); + + + if (!tsi620->regs) + { + TSI620_DEBUG("Unable to remap IO space\n"); + return -ENOMEM; + } + + if (!tsi620->base) + { + TSI620_DEBUG("Unable to remap memory\n"); + return -ENOMEM; + } + + TSI620_DEBUG("Remapped spaces: regs -- 0x%x, mem -- 0x%x\n", (u32) tsi620->regs, (u32) tsi620->base); + + tsi620->srep = tsi620->regs + TSI620_SREP_OFFSET; + tsi620->pci = tsi620->regs + TSI620_PCI_OFFSET; + + /* Ok, so this "mem space" exists -- let's break it up into some chunks */ + tsi620_init_translation(pdev); + + return 0; +} + +/***************************************************************************** + * Map all PCI BAR2 transactions to target the SREP interface * + *****************************************************************************/ +void tsi620_init_p2o_bar2_luts() +{ + int lutIndex; + u32 p2o_page_sizes; + + /* Map transactions to SREP (= port 0) with no address translation. */ + p2o_page_sizes = in_le32((void*)(tsi620->pci + TSI620_PCI_P2O_PAGE_SIZES)); + p2o_page_sizes |= 0x00000400; + out_le32((void*)(tsi620->pci + TSI620_PCI_P2O_PAGE_SIZES), p2o_page_sizes); + + for (lutIndex = 0; lutIndex < TSI620_PCI_NUM_P2O_LUTS; lutIndex++) { + out_le32((void*)(tsi620->pci + TSI620_PCI_P2O_BAR2_LUTx(lutIndex)), 0x00000000); + out_le32((void*)(tsi620->pci + TSI620_PCI_P2O_BAR2_LUTx_UPPER(lutIndex)), 0x00000000); + } +} + +/*************************************************************** + * Returns log2 (highest order bit) of the number + ***************************************************************/ +int getLog2(u32 n) +{ + /* Note that there are faster ways to do this... but this is clean and easy to read */ + int l = 0; + while (n >>= 1) l++; + return l; +} + +/*************************************************************** +* Convert a size (number of bytes) to a value suitilbe to programming +* into I2R_BARx_LUT_CSR +***************************************************************/ +u32 sizeToBarSizeId(u32 barSize) +{ + // Note that we expect barSize to be a valid value (a power of 2) + int x = getLog2(barSize); + x -= 12; + x <<= 8; + return x; +} + +/*************************************************************** +* Convert the number of LUTs into a value suitible to program into +* I2R_BARx_LUT_CSR +***************************************************************/ +u32 lutsToLutsId(int luts) +{ + return getLog2(luts); +} + +/************************************************************** +* Setup a given bar based on the inputted parameters +***************************************************************/ +void tsi620_setup_srep_hw_bar(int barIndex, u32 isfAddress, u32 barSize, + int firstLut, int luts, int enabled) +{ + u32 temp; // The value to program in the register (as value is being built) + + //Setup the LUT CSR + temp = (firstLut << 16) | sizeToBarSizeId(barSize) | lutsToLutsId(luts); + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_BARx_LUT_CSR(barIndex)), temp); + + //Setup the LOWER register + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_BARx_LOWER(barIndex)), + (isfAddress & 0xfffff000) | (enabled ? 1 : 0)); + + //Setup the UPPER register (0) + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_BARx_UPPER(barIndex)), 0); +} + +/************************************************************** +* Setup a given LUT based on the inputted parameters +***************************************************************/ +void tsi620_setup_srep_hw_lut(int lutIndex, u16 destId, u8 hopcount, + u32 rio_addr, u16 transaction) +{ + u32 lower; + + lower = rio_addr & 0xffffff00; + lower |= 0x000000a0; + + /* These will be filled in by tsi620_rio_config_write/read */ + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_PTY_CTL), lutIndex); + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_UPPER), + ((hopcount & 0xff) << 24) | 0x00d00000 | destId); + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_LOWER), 0x000000a0 | (rio_addr & 0xfffff000)); //read and write priority 2 + out_le32((void*)(tsi620->srep + TSI620_SREP_I2R_LUT_TA_RIO_PARMS), (u32) transaction); +} + + +/*************************************************************** + * Setup a LUT to translate to the specified opration on the + * specified RIO device + ***************************************************************/ +void tsi620_setup_srep_region(int barIndex, int lutIndex, u32 isfAddress, + u32 size, u16 destId, u8 hopcount, u32 rio_addr, + u16 transaction, int enabled) +{ + struct tsi620_bar* bar = &(tsi620->bar[barIndex]); + + //setup the HW registers + tsi620_setup_srep_hw_lut(lutIndex, destId, hopcount, rio_addr, transaction); + tsi620_setup_srep_hw_bar(barIndex, isfAddress, size, lutIndex, 1, enabled); + + //Mark it in SW + bar->enabled = enabled; + bar->luts = 1; + bar->firstLut = lutIndex; + bar->isfAddr = isfAddress; + bar->destid = destId; + bar->hopcount = hopcount; + bar->size = size; + if (enabled) + { + bar->procAddr = (void*) (tsi620->base + (isfAddress - tsi620->i2rBase)); + } + else + { + bar->procAddr = NULL; + } + + TSI620_DEBUG("bar %d setup to dest 0x%x, hc 0x%x, rio_addr 0x%x at proc addr 0x%x\n", barIndex, destId, hopcount, rio_addr, (u32) bar->procAddr); +} + +/***************************************************************************** + * Setup regions in the memory space for transactions + *****************************************************************************/ +void tsi620_init_translation(struct pci_dev* dev) +{ + + /* Memory space will be divided into sections + * Top 1MB will be used for maintainence transactions + * Below that will be doorbells (eventually) + * Below that will be memory access + */ + + u32 top; + + /* What is the PCI address of the top? */ + top = tsi620->i2rBase + tsi620->memSize; + + /* Let's assume that worked (I know, I know...) */ + /* So, next thing we do is map all of these PCI transactions to SREP */ + { + /* So that means we should put maintaince transactions where? */ + tsi620->i2rMaint = top - TSI620_MAINT_SPACE_SIZE; + tsi620->maint = tsi620->base + (tsi620->i2rMaint - tsi620->i2rBase); + + TSI620_DEBUG("Mem PCI addr: 0x%08x\n", tsi620->i2rBase); + TSI620_DEBUG("Maint PCI addr: 0x%08x\n\n", tsi620->i2rMaint); + TSI620_DEBUG("Proc addr: 0x%08x\n", tsi620->base); + TSI620_DEBUG("Maint proc addr: 0x%08x\n\n", tsi620->maint); + tsi620_init_p2o_bar2_luts(); + } + + /* Next, let's set up the maintainece window */ + { + u32 barIndex; + + /* Set up 7 BAR regions (except for maint region)*/ + for (barIndex = 0; barIndex < 7; barIndex++) + { + tsi620_setup_srep_region(barIndex, barIndex, 0, 0x1000, 0xff, + DEFAULT_HOPCOUNT, 0, TSI620_SREP_LUT_MAINT_TRANS, 0); + } + + tsi620_setup_srep_region(MAINT_BAR, MAINT_BAR_LUT, tsi620->i2rMaint, + TSI620_MAINT_SPACE_SIZE, 0xff, DEFAULT_HOPCOUNT, 0, + TSI620_SREP_LUT_MAINT_TRANS, 1); + + } +} + +/***************************************************************************** + * Setup RIO subsystem with Tsi620 as a master port + *****************************************************************************/ +int tsi620_setup_mport(struct pci_dev *pdev) +{ + int retval = 0; + struct rio_ops *ops; + + struct rio_mport *mport; + + ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL); + if (!ops) + { + TSI620_DEBUG("Could not allocate memory for rio_ops\n"); + return -ENOMEM; + } + memset(ops, 0, sizeof(struct rio_ops)); + ops->lcread = tsi620_lcread; + ops->lcwrite = tsi620_lcwrite; + ops->cread = tsi620_cread; + ops->cwrite = tsi620_cwrite; + ops->dsend = tsi620_dsend; + ops->rio_ioremap = tsi620_ioremap; + ops->rio_unmap = tsi620_unmap; + + mport = kmalloc(sizeof(struct rio_mport), GFP_KERNEL); + if (!mport) + { + kfree(ops); + TSI620_DEBUG("Could not allocate memory for rio_ops\n"); + return -ENOMEM; + } + mport->ops = ops; + mport->id = 0; + mport->index = 0; + mport->sys_size = 0; /* small system */ + mport->phy_type = RIO_PHY_SERIAL; + mport->name[0] = 'T'; + mport->name[1] = 0; + mport->priv = (void*) tsi620; + mport->host_deviceid = 1; /* TODO -- read from cmd line */ + + INIT_LIST_HEAD(&mport->dbells); + + mport->iores.start = tsi620->base; + mport->iores.end = tsi620->base + tsi620->memSize; + mport->iores.flags = IORESOURCE_MEM; + strcpy(mport->name, "Tsi620 mport"); + + rio_register_mport(mport); + return retval; +} + +/***************************************************************************** + * Find an available bar + *****************************************************************************/ +int findFreeRegion(u32 length, u32* pAddr) +{ + int bar; + int nextBar; + int barStartAddress = tsi620->i2rBase; + int maxSize = 0; + + for (bar = 0; bar < TSI620_SREP_I2R_NUMBARS; bar++) + { + + TSI620_DEBUG("Checking bar %d\n", bar); + if (!(tsi620->bar[bar].enabled)) + { + TSI620_DEBUG("bar %d not enabled... is it big enough?\n", bar); + //Ok, so we have a free bar -- but is it big enough? + nextBar = bar+1; + + while(nextBar < TSI620_SREP_I2R_NUMBARS) + + //for (nextBar = (bar+1); nextBar < TSI620_SREP_I2R_NUMBARS; nextBar++); + { + if(tsi620->bar[nextBar].enabled) + { + //Ok, so we found the next bar that's in use... we can use it's address to determine max size of this bar + maxSize = tsi620->bar[nextBar].isfAddr - barStartAddress; + break; + } + else + { + nextBar++; + } + } + + /* Ok, so we found the next used BAR, and we know the maximum size this bar can be */ + if (maxSize >= length) + { + break; + } + else + { + } + } + else + { + //update the lowest possible start address, and look at the next BAR + barStartAddress = tsi620->bar[bar].isfAddr + tsi620->bar[bar].size; + } + } + + if (TSI620_SREP_I2R_NUMBARS == bar) + { + TSI620_DEBUG("Could not find a free BAR with 0x%x of space :( -- aborting\n", length); + return -1; + } + else + { + TSI620_DEBUG("bar %d works starting at 0x%x!\n", bar, barStartAddress); + *pAddr = barStartAddress; + return bar; + } +} + +/***************************************************************************** + * Map an area of processor space to a RIO device memory + *****************************************************************************/ +void* tsi620_ioremap(void* rio_address, u16 destid, unsigned int length) +{ + u32 isfAddr; + + int bar = findFreeRegion(length, &isfAddr); + + TSI620_DEBUG("Remapping to bar %d, ISF addr 0x%x\n", bar, isfAddr); + + if (-1 == bar) + return NULL; + + tsi620_setup_srep_region(bar, bar, isfAddr, + length, destid, 0xff, (u32) rio_address, + TSI620_SREP_LUT_NR_NW_TRANS, 1); + + + tsi620->bar[bar].procAddr = (void*) (tsi620->base + (isfAddr - tsi620->i2rBase)); + + TSI620_DEBUG("Proc addr 0x%x\n", (u32) tsi620->bar[bar].procAddr); + + return tsi620->bar[bar].procAddr; +} + +void tsi620_unmap(void* address) +{ + int bar; + + for (bar = 0; bar < TSI620_SREP_I2R_NUMBARS; bar++) + { + if (tsi620->bar[bar].procAddr == address) + { + tsi620_setup_srep_region(bar, bar, 0, + 0x1000, 0xff, DEFAULT_HOPCOUNT, 0, + TSI620_SREP_LUT_NR_NW_TRANS, 0); + tsi620->bar[bar].procAddr = 0; + break; + } + } +} + +/***************************************************************************** + * Unload driver + *****************************************************************************/ +void tsi620_remove(struct pci_dev *pdev) +{ + iounmap((void*) tsi620->base); + iounmap((void*) tsi620->regs); + kfree(tsi620); +} + +static int __init tsi620_init(void) +{ + return pci_register_driver(&tsi620_driver); +} + +static void __exit tsi620_exit(void) +{ + pci_unregister_driver(&tsi620_driver); +} + + +module_init(tsi620_init); +module_exit(tsi620_exit); + + diff --git a/drivers/rapidio/mports/tsi620/tsi620.h b/drivers/rapidio/mports/tsi620/tsi620.h new file mode 100644 index 0000000..e32dfd3 --- /dev/null +++ b/drivers/rapidio/mports/tsi620/tsi620.h @@ -0,0 +1,123 @@ +/* Tsi620 Header + * + * Copyright 2009, Integrated Device Technology, Inc. + * + * The register offsets and values defined in this file represent the Tsi620 + * PCI to RapidIO bridge. These offsets and values should be trated with the + * same discretion and NDA terms as the Tsi620 User Manual, available from IDT. + * + * Other aspects of this file (data structures, etc) are used by the Tsi620 + * driver code. While these are not described in the Tsi620 User Manual, + * these aspects should again be considered confidental, as should the + * tsi620.c driver code. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef __TSI620_H +#define __TSI620_H + +#define DEFAULT_HOPCOUNT 0xff + +/* PCI vendor and device ID */ +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TSI620 0x0620 + +/* Which BAR/LUTs to use */ +#define TSI620_SREP_I2R_NUMBARS (8) +#define TSI620_SREP_I2R_NUMLUTS (255) +#define MAINT_BAR (TSI620_SREP_I2R_NUMBARS - 1) +#define MAINT_BAR_LUT (TSI620_SREP_I2R_NUMLUTS - 1) +#define MEM_BAR 0x0 + +/* Memory space sizes */ +#define TSI620_CONFIG_SPACE_SIZE (1024 * 256) /* 256K */ +#define TSI620_MAINT_SPACE_SIZE (1024 * 1024 * 1) /* 1M */ + +/* Register offsets */ + +/* Offset to a block within the registers */ +#define TSI620_SREP_OFFSET 0x20000 +#define TSI620_PCI_OFFSET 0x22000 + +/* Offset from a block base address to individual registers */ +/* SREP */ +#define TSI620_SREP_R2Ix_LUT_CSR(_x_) (0x500 + (_x_ * 0x10)) +#define TSI620_SREP_I2R_BARx_LUT_CSR(_x_) (0x600 + (_x_ * 0x10)) +#define TSI620_SREP_I2R_BARx_UPPER(_x_) (0x604 + (_x_ * 0x10)) +#define TSI620_SREP_I2R_BARx_LOWER(_x_) (0x608 + (_x_ * 0x10)) +#define TSI620_SREP_I2R_LUT_PTY_CTL (0x6a0) +#define TSI620_SREP_I2R_LUT_TA_UPPER (0x6a4) +#define TSI620_SREP_I2R_LUT_TA_LOWER (0x6ac) +#define TSI620_SREP_I2R_LUT_TA_RIO_PARMS (0x6bc) + +#define TSI620_SREP_BAR_SIZE_4K 0x0000 +#define TSI620_SREP_BAR_SIZE_8K 0x0100 +#define TSI620_SREP_BAR_SIZE_16K 0x0200 +#define TSI620_SREP_BAR_SIZE_32K 0x0300 +#define TSI620_SREP_BAR_SIZE_64K 0x0400 +#define TSI620_SREP_BAR_SIZE_128K 0x0500 +#define TSI620_SREP_BAR_SIZE_256K 0x0600 +#define TSI620_SREP_BAR_SIZE_512K 0x0700 +#define TSI620_SREP_BAR_SIZE_1M 0x0800 +#define TSI620_SREP_BAR_SIZE_2M 0x0900 +#define TSI620_SREP_BAR_SIZE_4M 0x0a00 +#define TSI620_SREP_BAR_SIZE_8M 0x0b00 +#define TSI620_SREP_BAR_SIZE_16M 0x0c00 +#define TSI620_SREP_BAR_SIZE_32M 0x0d00 +#define TSI620_SREP_BAR_SIZE_64M 0x0e00 +#define TSI620_SREP_BAR_SIZE_128M 0x0f00 +#define TSI620_SREP_BAR_SIZE_256M 0x1000 +#define TSI620_SREP_BAR_SIZE_512M 0x1100 +#define TSI620_SREP_BAR_SIZE_1G 0x1200 +#define TSI620_SREP_BAR_SIZE_2G 0x1300 + +/* Various common type of transactions in LUT */ +#define TSI620_SREP_LUT_MAINT_TRANS 0x8081 //Maint read, maint write +#define TSI620_SREP_LUT_NR_NW_TRANS 0x2454 //NREAD, NWRITE +#define TSI620_SREP_LUT_NR_NWR_TRANS 0x2555 //NREAD, NWRITE_R + +#define MAINT_BAR_SIZE_ID TSI620_SREP_BAR_SIZE_1M + +/* PCI */ +#define TSI620_PCI_BAR2 0x018 +#define TSI620_PCI_MEM_BAR TSI620_PCI_BAR2 +#define TSI620_PCI_P2O_BAR2_LUTx(x) (0x500 + (x * 0x08)) +#define TSI620_PCI_P2O_BAR2_LUTx_UPPER(x) (0x504 + (x * 0x08)) +#define TSI620_PCI_P2O_PAGE_SIZES 0x04c +#define TSI620_PCI_NUM_P2O_LUTS 32 + +#define TSI620_PCI_P2O_PAGE_SIZES__BAR2_SIZE_MASK 0x0000f800 + +struct tsi620_bar +{ + int firstLut; + int luts; + u32 isfAddr; + void* procAddr; + u16 destid; + u8 hopcount; + int size; + int enabled; +}; + +/* global variables -- all in a nice, neat struct */ +struct tsi620_device { + u32 regs; /* Window into all Tsi620 regs */ + u32 srep; /* Serial RapidIO endpoint registers */ + u32 pci; /* PCI registers */ + + u32 memSize; + + u32 i2rBase; /* This is the PCI address where we start I2R space */ + u32 base; /* This is the processor space address used to access I2R space */ + + u32 i2rMaint; /* PCI address of where we start maintainence space */ + u32 maint; /* Processor address of where we start maint space */ + + struct tsi620_bar bar[TSI620_SREP_I2R_NUMBARS]; +}; + +#endif diff --git a/drivers/rapidio/rio-scan.c b/drivers/rapidio/rio-scan.c index ebe77dd..68d5828 100644 --- a/drivers/rapidio/rio-scan.c +++ b/drivers/rapidio/rio-scan.c @@ -36,6 +36,9 @@ #include "rio.h" +#undef pr_debug +#define pr_debug printk + LIST_HEAD(rio_devices); static LIST_HEAD(rio_switches); @@ -376,7 +379,7 @@ static struct rio_dev __devinit *rio_setup_device(struct rio_net *net, int ret = 0; struct rio_dev *rdev; struct rio_switch *rswitch = NULL; - int result, rdid; + u32 result, rdid; size_t size; u32 swpinfo = 0; @@ -1198,6 +1201,8 @@ int __devinit rio_enum_mport(struct rio_mport *mport) } out: + printk(KERN_INFO "RIO: master port %d destid %d\n", + mport->id, mport->host_deviceid); return rc; } @@ -1256,6 +1261,7 @@ static void rio_enum_timeout(unsigned long data) * peer discovery. Returns %0 if discovery succeeds or %-EBUSY * on failure. */ + int __devinit rio_disc_mport(struct rio_mport *mport) { struct rio_net *net = NULL; @@ -1266,6 +1272,7 @@ int __devinit rio_disc_mport(struct rio_mport *mport) /* If master port has an active link, allocate net and discover peers */ if (rio_mport_is_active(mport)) { + if (!(net = rio_alloc_net(mport))) { printk(KERN_ERR "RIO: Failed to allocate new net\n"); goto bail; @@ -1277,6 +1284,7 @@ int __devinit rio_disc_mport(struct rio_mport *mport) jiffies + CONFIG_RAPIDIO_DISC_TIMEOUT * HZ; rio_enum_timer.data = (unsigned long)&enum_timeout_flag; add_timer(&rio_enum_timer); + while (!rio_enum_complete(mport)) { mdelay(1); if (enum_timeout_flag) { @@ -1304,7 +1312,6 @@ int __devinit rio_disc_mport(struct rio_mport *mport) rio_build_route_tables(); } - return 0; timeout: diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c index 86c9a09..4a2487b 100644 --- a/drivers/rapidio/rio.c +++ b/drivers/rapidio/rio.c @@ -243,7 +243,15 @@ int rio_request_inb_dbell(struct rio_mport *mport, { int rc = 0; - struct resource *res = kmalloc(sizeof(struct resource), GFP_KERNEL); + struct resource *res; + + if (mport->ops->open_inb_mbox == NULL) + { + rc = -ENOTSUPP; + goto out; + } + + res = kmalloc(sizeof(struct resource), GFP_KERNEL); if (res) { rio_init_dbell_res(res, start, end); @@ -831,7 +839,7 @@ int rio_inb_pwrite_handler(union rio_pw_msg *pw_msg) RIO_PORT_N_ACK_CLEAR); /* Schedule Extraction Service */ - pr_debug("RIO_PW: Device Extraction on [%s]-P%d\n", + printk("RIO_PW: Device Extraction on [%s]-P%d\n", rio_name(rdev), portnum); } } @@ -1184,6 +1192,21 @@ int rio_register_mport(struct rio_mport *port) return 0; } +void* rio_ioremap(struct rio_mport *mport, void* rio_address, + u16 destid, unsigned int length) +{ + if (!mport->ops->rio_ioremap) + return NULL; + return mport->ops->rio_ioremap(rio_address, destid, length); +} + +void rio_unmap(struct rio_mport *mport, void* address) +{ + if (!mport->ops->rio_unmap) + return; + mport->ops->rio_unmap(address); +} + EXPORT_SYMBOL_GPL(rio_local_get_device_id); EXPORT_SYMBOL_GPL(rio_get_device); EXPORT_SYMBOL_GPL(rio_get_asm); @@ -1195,3 +1218,7 @@ EXPORT_SYMBOL_GPL(rio_request_inb_mbox); EXPORT_SYMBOL_GPL(rio_release_inb_mbox); EXPORT_SYMBOL_GPL(rio_request_outb_mbox); EXPORT_SYMBOL_GPL(rio_release_outb_mbox); +EXPORT_SYMBOL_GPL(rio_ioremap); +EXPORT_SYMBOL_GPL(rio_unmap); +EXPORT_SYMBOL_GPL(rio_register_mport); +EXPORT_SYMBOL_GPL(rio_init_mports); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index ab085f1..890c08d 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -230,6 +230,19 @@ config USB_OXU210HP_HCD To compile this driver as a module, choose M here: the module will be called oxu210hp-hcd. +config USB_CI13612_HCD + tristate "CI13612A HCD support" + depends on USB + ---help--- + The CI13612A is an USB host/OTG/device controller. Enable this + option if your board has this chip. If unsure, say N. + + This driver does not support isochronous transfers and doesn't + implement OTG nor USB device controllers. + + To compile this driver as a module, choose M here: the + module will be called CI13612-hcd. + config USB_ISP116X_HCD tristate "ISP116X HCD support" depends on USB diff --git a/drivers/usb/host/ci13612.h b/drivers/usb/host/ci13612.h new file mode 100644 index 0000000..b893018 --- /dev/null +++ b/drivers/usb/host/ci13612.h @@ -0,0 +1,887 @@ +/* + * System definitions + */ +#define ci13612_PHY_ADDR 0x0020004A0000 +#define ci13162_PHY_ADDR_SIZE 0x20000 + +#define MAX_EHCI_FRAME_LIST_SIZE 8 +#define MAX_EHCI_FRAME_LIST_BITS EHCI_CMD_FRAME_SIZE_8 + +#define MAX_QH_DESCRS (8) +#define MAX_QTD_DESCRS (16) +#define MAX_ITD_DESCRS (16) +#define MAX_SITD_DESCRS (16) + + +#define USB_MAX_INTERFACES (10) +#define RX_BUFFER_SIZE (0xFF) + +/* Macro for alignment to specific byte boundary */ +#define USB_MEM32_ALIGN(n) ((n) + (-(n) & 31)) +#define USB_MEM512_ALIGN(n) ((n) + (-(n) & 511)) +#define USB_MEM4096_ALIGN(n) ((n) + (-(n) & 4095)) + +#define BitStuffTime(x) (7* 8 * x / 6) + +/* + * Host interface registers + */ + +/* define CI13612 USB registers here */ + + +#define ci13612_USB_CMD 0x140 + /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ + #define USB_CMD_PARK (1<<11) /* enable "park" on async qh */ + #define USB_CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ + #define USB_CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ + #define USB_CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ + #define USB_CMD_ASE (1<<5) /* async schedule enable */ + #define USB_CMD_PSE (1<<4) /* periodic schedule enable */ + /* 3:2 is periodic frame list size */ + #define USB_CMD_RESET (1<<1) /* reset HC not bus */ + #define USB_CMD_RUN (1<<0) /* start/stop HC */ + + +#define ci13612_USB_STS 0x144 + #define USB_STS_ASS (1<<15) /* Async Schedule Status */ + #define USB_STS_PSS (1<<14) /* Periodic Schedule Status */ + #define USB_STS_RECL (1<<13) /* Reclamation */ + #define USB_STS_HALT (1<<12) /* Not running (any reason) */ + /* some bits reserved */ + /* these STS_* flags are also intr_enable bits (USBINTR) */ + #define USB_STS_IAA (1<<5) /* Interrupted on async advance */ + #define USB_STS_FATAL (1<<4) /* such as some PCI access errors */ + #define USB_STS_FLR (1<<3) /* frame list rolled over */ + #define USB_STS_PCD (1<<2) /* port change detect */ + #define USB_STS_ERR (1<<1) /* "error" completion (overflow, ...) */ + #define USB_STS_INT (1<<0) /* "normal" completion (short, ...) */ + +#define ci13612_USB_INTEN 0x148 + + +#define ci13612_HCS_PARAMS 0x104 +#define ci13612_HCC_PARAMS 0x108 + +#define ci13612_USBSTS 0x144 +#define ci13612_USBINTR 0x148 +#define ci13612_FRINDEX 0x14C +#define ci13612_CTRLDSSEGMENT 0x150 +#define ci13612_CONFIGFLAG 0x180 +#define ci13612_PORTSCX0 0x184 + + +#define ci13612_DEVICEID 0x00 + #define ci13612_REV_MASK 0xffff0000 + #define ci13612_REV_SHIFT 16 + #define ci13612_REV_2100 0x2100 + #define ci13612_BO_SHIFT 8 + #define ci13612_BO_MASK (0x3 << ci13612_BO_SHIFT) + #define ci13612_MAJ_REV_SHIFT 4 + #define ci13612_MAJ_REV_MASK (0xf << ci13612_MAJ_REV_SHIFT) + #define ci13612_MIN_REV_SHIFT 0 + #define ci13612_MIN_REV_MASK (0xf << ci13612_MIN_REV_SHIFT) +#define ci13612_HOSTIFCONFIG 0x04 +#define ci13612_SOFTRESET 0x08 + #define ci13612_SRESET (1 << 0) + +#define ci13612_PIOBURSTREADCTRL 0x0C + +#define ci13612_CHIPIRQSTATUS 0x10 +#define ci13612_CHIPIRQEN_SET 0x14 +#define ci13612_CHIPIRQEN_CLR 0x18 + #define ci13612_USBSPHLPWUI 0x00000080 + #define ci13612_USBOTGLPWUI 0x00000040 + #define ci13612_USBSPHI 0x00000002 + #define ci13612_USBOTGI 0x00000001 + +#define ci13612_CLKCTRL_SET 0x1C + #define ci13612_SYSCLKEN 0x00000008 + #define ci13612_USBSPHCLKEN 0x00000002 + #define ci13612_USBOTGCLKEN 0x00000001 + +#define ci13612_ASO 0x68 + #define ci13612_SPHPOEN 0x00000100 + #define ci13612_OVRCCURPUPDEN 0x00000800 + #define ci13612_ASO_OP (1 << 10) + #define ci13612_COMPARATOR 0x000004000 + +#define ci13612_USBMODE 0x1A8 + #define ci13612_VBPS 0x00000020 + #define ci13612_ES_LITTLE 0x00000004 + #define ci13612_CM_HOST_ONLY 0x00000003 + +/* + * Proper EHCI structs & defines + */ + +/* Magic numbers that can affect system performance */ +#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ +#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ +#define EHCI_TUNE_RL_TT 0 +#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ +#define EHCI_TUNE_MULT_TT 1 +#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ + +struct ci13612_hcd; + +/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ + +/* Section 2.2 Host Controller Capability Registers */ +#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ +#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ +#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ +#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ +#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ +#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ +#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ +#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ +#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ +#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ +#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ +#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ +#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ +#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ +#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ + + +struct ehci_caps { + /* these fields are specified as 8 and 16 bit registers, + * but some hosts can't perform 8 or 16 bit PCI accesses. + */ + u32 hc_capbase; + u32 hcs_params; /* HCSPARAMS - offset 0x4 */ + u32 hcc_params; /* HCCPARAMS - offset 0x8 */ + u8 portroute[8]; /* nibbles for routing - offset 0xC */ +} __attribute__ ((packed)); + +/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ +#define CMD_PARK (1<<11) /* enable "park" on async qh */ +#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ +#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ +#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ +#define CMD_ASE (1<<5) /* async schedule enable */ +#define CMD_PSE (1<<4) /* periodic schedule enable */ +/* 3:2 is periodic frame list size */ +#define CMD_RESET (1<<1) /* reset HC not bus */ +#define CMD_RUN (1<<0) /* start/stop HC */ + +#define STS_ASS (1<<15) /* Async Schedule Status */ +#define STS_PSS (1<<14) /* Periodic Schedule Status */ +#define STS_RECL (1<<13) /* Reclamation */ +#define STS_HALT (1<<12) /* Not running (any reason) */ +/* some bits reserved */ + /* these STS_* flags are also intr_enable bits (USBINTR) */ +#define STS_IAA (1<<5) /* Interrupted on async advance */ +#define STS_FATAL (1<<4) /* such as some PCI access errors */ +#define STS_FLR (1<<3) /* frame list rolled over */ +#define STS_PCD (1<<2) /* port change detect */ +#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ +#define STS_INT (1<<0) /* "normal" completion (short, ...) */ + +#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) + +#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ + + +/* 31:23 reserved */ +#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ +#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ +#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ +/* 19:16 for port testing */ +#define PORT_LED_OFF (0<<14) +#define PORT_LED_AMBER (1<<14) +#define PORT_LED_GREEN (2<<14) +#define PORT_LED_MASK (3<<14) +#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ +#define PORT_POWER (1<<12) /* true: has power (see PPC) */ +#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ +/* 11:10 for detecting lowspeed devices (reset vs release ownership) */ +/* 9 reserved */ +#define PORT_RESET (1<<8) /* reset port */ +#define PORT_SUSPEND (1<<7) /* suspend port */ +#define PORT_RESUME (1<<6) /* resume it */ +#define PORT_OCC (1<<5) /* over current change */ +#define PORT_OC (1<<4) /* over current active */ +#define PORT_PEC (1<<3) /* port enable change */ +#define PORT_PE (1<<2) /* port enable */ +#define PORT_CSC (1<<1) /* connect status change */ +#define PORT_CONNECT (1<<0) /* device connected */ +#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) + + +/* Section 2.3 Host Controller Operational Registers */ +struct ehci_regs { + /* USBCMD: offset 0x00 */ + u32 command; + /* USBSTS: offset 0x04 */ + u32 status; + /* USBINTR: offset 0x08 */ + u32 intr_enable; + /* FRINDEX: offset 0x0C */ + u32 frame_index; /* current microframe number */ + /* CTRLDSSEGMENT: offset 0x10 */ + u32 segment; /* address bits 63:32 if needed */ + /* PERIODICLISTBASE: offset 0x14 */ + u32 frame_list; /* points to periodic list */ + /* ASYNCLISTADDR: offset 0x18 */ + u32 async_next; /* address of next async queue head */ + u32 reserved[9]; + /* CONFIGFLAG: offset 0x40 */ + u32 configured_flag; + /* PORTSC: offset 0x44 */ + u32 port_status[8]; /* up to N_PORTS */ + +} __attribute__ ((packed)); + +/* Appendix C, Debug port ... intended for use with special "debug devices" + * that can help if there's no serial console. (nonstandard enumeration.) + */ +struct ehci_dbg_port { + u32 control; +#define DBGP_OWNER (1<<30) +#define DBGP_ENABLED (1<<28) +#define DBGP_DONE (1<<16) +#define DBGP_INUSE (1<<10) +#define DBGP_ERRCODE(x) (((x)>>7)&0x07) +# define DBGP_ERR_BAD 1 +# define DBGP_ERR_SIGNAL 2 +#define DBGP_ERROR (1<<6) +#define DBGP_GO (1<<5) +#define DBGP_OUT (1<<4) +#define DBGP_LEN(x) (((x)>>0)&0x0f) + u32 pids; +#define DBGP_PID_GET(x) (((x)>>16)&0xff) +#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok)) + u32 data03; + u32 data47; + u32 address; +#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) +} __attribute__ ((packed)); + + +#define QTD_NEXT(dma) cpu_to_le32((u32)dma) + +/* + * EHCI Specification 0.95 Section 3.5 + * QTD: describe data transfer components (buffer, direction, ...) + * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". + * + * These are associated only with "QH" (Queue Head) structures, + * used with control, bulk, and interrupt transfers. + */ +struct ehci_qtd { + /* first part defined by EHCI spec */ + __le32 hw_next; /* see EHCI 3.5.1 */ + __le32 hw_alt_next; /* see EHCI 3.5.2 */ + __le32 hw_token; /* see EHCI 3.5.3 */ +#define QTD_TOGGLE (1 << 31) /* data toggle */ +#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) +#define QTD_IOC (1 << 15) /* interrupt on complete */ +#define QTD_CERR(tok) (((tok)>>10) & 0x3) +#define QTD_PID(tok) (((tok)>>8) & 0x3) +#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ +#define QTD_STS_HALT (1 << 6) /* halted on error */ +#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ +#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ +#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ +#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ +#define QTD_STS_STS (1 << 1) /* split transaction state */ +#define QTD_STS_PING (1 << 0) /* issue PING? */ + __le32 hw_buf[5]; /* see EHCI 3.5.4 */ + __le32 hw_buf_hi[5]; /* Appendix B */ + + /* the rest is HCD-private */ + dma_addr_t qtd_dma; /* qtd address */ + struct list_head qtd_list; /* sw qtd list */ + struct urb *urb; /* qtd's urb */ + size_t length; /* length of buffer */ + + u32 qtd_buffer_len; + void *buffer; + dma_addr_t buffer_dma; + void *transfer_buffer; + void *transfer_dma; +} __attribute__ ((aligned(32))); + +/* mask NakCnt+T in qh->hw_alt_next */ +#define QTD_MASK __constant_cpu_to_le32 (~0x1f) + +#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) + +/* Type tag from {qh, itd, sitd, fstn}->hw_next */ +#define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1)) + +/* values for that type tag */ +#define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1) + +/* next async queue entry, or pointer to interrupt/periodic QH */ +#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH) + +/* for periodic/async schedules and qtd lists, mark end of list */ +#define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */ + +/* + * Entries in periodic shadow table are pointers to one of four kinds + * of data structure. That's dictated by the hardware; a type tag is + * encoded in the low bits of the hardware's periodic schedule. Use + * Q_NEXT_TYPE to get the tag. + * + * For entries in the async schedule, the type tag always says "qh". + */ +union ehci_shadow { + struct ehci_qh *qh; /* Q_TYPE_QH */ + __le32 *hw_next; /* (all types) */ + void *ptr; +}; + +/* + * EHCI Specification 0.95 Section 3.6 + * QH: describes control/bulk/interrupt endpoints + * See Fig 3-7 "Queue Head Structure Layout". + * + * These appear in both the async and (for interrupt) periodic schedules. + */ + +struct ehci_qh { + /* first part defined by EHCI spec */ + __le32 hw_next; /* see EHCI 3.6.1 */ + __le32 hw_info1; /* see EHCI 3.6.2 */ +#define QH_HEAD 0x00008000 + __le32 hw_info2; /* see EHCI 3.6.2 */ +#define QH_SMASK 0x000000ff +#define QH_CMASK 0x0000ff00 +#define QH_HUBADDR 0x007f0000 +#define QH_HUBPORT 0x3f800000 +#define QH_MULT 0xc0000000 + __le32 hw_current; /* qtd list - see EHCI 3.6.4 */ + + /* qtd overlay (hardware parts of a struct ehci_qtd) */ + __le32 hw_qtd_next; + __le32 hw_alt_next; + __le32 hw_token; + __le32 hw_buf[5]; + __le32 hw_buf_hi[5]; + + /* the rest is HCD-private */ + dma_addr_t qh_dma; /* address of qh */ + union ehci_shadow qh_next; /* ptr to qh; or periodic */ + struct list_head qtd_list; /* sw qtd list */ + struct ehci_qtd *dummy; + struct ehci_qh *reclaim; /* next to reclaim */ + + struct ci13612_hcd *ci13612; + struct kref kref; + unsigned stamp; + + u8 qh_state; +#define QH_STATE_LINKED 1 /* HC sees this */ +#define QH_STATE_UNLINK 2 /* HC may still see this */ +#define QH_STATE_IDLE 3 /* HC doesn't see this */ +#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ +#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ + + /* periodic schedule info */ + u8 usecs; /* intr bandwidth */ + u8 gap_uf; /* uframes split/csplit gap */ + u8 c_usecs; /* ... split completion bw */ + u16 tt_usecs; /* tt downstream bandwidth */ + unsigned short period; /* polling interval */ + unsigned short start; /* where polling starts */ +#define NO_FRAME ((unsigned short)~0) /* pick new start */ + struct usb_device *dev; /* access to TT */ +} __attribute__ ((aligned(32))); + +/* + * Proper ci13612 structs + */ + +#define ci13612_OTG_CORE_OFFSET 0x0 +#define ci13612_OTG_CAP_OFFSET (ci13612_OTG_CORE_OFFSET + 0x100) +#define ci13612_SPH_CORE_OFFSET 0x0 +#define ci13612_SPH_CAP_OFFSET (ci13612_SPH_CORE_OFFSET + 0x100) + +#define ci13612_OTG_MEM 0xE000 +#define ci13612_SPH_MEM 0x16000 + +/* Only how many elements & element structure are specifies here. */ +/* 2 host controllers are enabled - total size <= 28 kbytes */ +#define DEFAULT_I_TDPS 1024 +#define QHEAD_NUM 8 +#define QTD_NUM 16 +#define SITD_NUM 16 +#define MURB_NUM 8 + +#define BUFFER_NUM 8 +#define BUFFER_SIZE 512 + +struct ci13612_info { + struct usb_hcd *hcd[2]; +}; + +struct ci13612_buf { + u8 buffer[BUFFER_SIZE]; +} __attribute__ ((aligned(BUFFER_SIZE))); + +struct ci13612_onchip_mem { + struct ci13612_buf db_pool[BUFFER_NUM]; + + u32 frame_list[DEFAULT_I_TDPS]; + struct ehci_qh qh_pool[QHEAD_NUM]; + struct ehci_qtd qtd_pool[QTD_NUM]; +} __attribute__ ((aligned(4 << 10))); + +#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ + +struct ci13612_murb { + struct urb urb; + struct urb *main; + u8 last; +}; + +struct ci13612_hcd { /* one per controller */ + unsigned int is_otg:1; + + u8 qh_used[QHEAD_NUM]; + u8 qtd_used[QTD_NUM]; + u8 db_used[BUFFER_NUM]; + u8 murb_used[MURB_NUM]; + + struct ci13612_onchip_mem __iomem *mem; + spinlock_t mem_lock; + + struct timer_list urb_timer; + + struct ehci_caps __iomem *caps; + struct ehci_regs __iomem *regs; + + __u32 hcs_params; /* cached register copy */ + spinlock_t lock; + + u32 FRAME_LIST_SIZE; + u8 UFRAME_COUNT; + u8 reset_in_progress; + u32 SPEED; + u32 PORT_NUM; + + /* async schedule support */ + struct ehci_qh *async; + struct ehci_qh *reclaim; + unsigned reclaim_ready:1; + unsigned scanning:1; + + /* periodic schedule support */ + unsigned periodic_size; + __le32 *periodic; /* hw periodic table */ + dma_addr_t periodic_dma; + unsigned i_thresh; /* uframes HC might cache */ + + union ehci_shadow *pshadow; /* mirror hw periodic table */ + int next_uframe; /* scan periodic, start here */ + unsigned periodic_sched; /* periodic activity count */ + + /* per root hub port */ + unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; + /* bit vectors (one bit per port) */ + unsigned long bus_suspended; /* which ports were + * already suspended at the + * start of a bus suspend + */ + unsigned long companion_ports;/* which ports are dedicated + * to the companion controller + */ + + struct timer_list watchdog; + unsigned long actions; + unsigned stamp; + unsigned long next_statechange; + u32 command; + + /* SILICON QUIRKS */ + struct list_head urb_list; /* this is the head to urb + * queue that didn't get enough + * resources + */ + struct ci13612_murb *murb_pool; /* murb per split big urb */ + unsigned urb_len; + + u8 sbrn; /* packed release number */ +}; + +#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */ +#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ +#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ +#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ + +enum ehci_timer_action { + TIMER_IO_WATCHDOG, + TIMER_IAA_WATCHDOG, + TIMER_ASYNC_SHRINK, + TIMER_ASYNC_OFF, +}; + + +/* Host specific */ +#define USB_DEBOUNCE_DELAY (101) +#define USB_RESET_RECOVERY_DELAY (11) +#define USB_RESET_DELAY (60) +#define USB_RESUME_RECOVERY_DELAY (100) + + +/* VUSBHS specific defines */ +#define VUSBHS_MAX_PORTS (8) +#define EHCI_CAP_LEN_MASK (0x000000FF) +#define EHCI_DATA_STRUCTURE_BASE_ADDRESS (0) + +/* Command Register Bit Masks */ +#define EHCI_CMD_RUN_STOP (0x00000001) +#define EHCI_CMD_CTRL_RESET (0x00000002) +#define EHCI_CMD_SETUP_TRIPWIRE_SET (0x00002000) +#define EHCI_CMD_SETUP_TRIPWIRE_CLEAR ~EHCI_CMD_SETUP_TRIPWIRE_SET + +/* Bit 14 is the tripwire bit not bit 12 as some versions of the docs state. */ +#define EHCI_CMD_ATDTW_TRIPWIRE_SET (0x00004000) +#define EHCI_CMD_ATDTW_TRIPWIRE_CLEAR ~EHCI_CMD_ATDTW_TRIPWIRE_SET + + /*bit 15,3,2 are for frame list size */ + #define EHCI_CMD_FRAME_SIZE_1024 (0x00000000) /* 000 */ + #define EHCI_CMD_FRAME_SIZE_512 (0x00000004) /* 001 */ + #define EHCI_CMD_FRAME_SIZE_256 (0x00000008) /* 010 */ + #define EHCI_CMD_FRAME_SIZE_128 (0x0000000C) /* 011 */ + #define EHCI_CMD_FRAME_SIZE_64 (0x00008000) /* 100 */ + #define EHCI_CMD_FRAME_SIZE_32 (0x00008004) /* 101 */ + #define EHCI_CMD_FRAME_SIZE_16 (0x00008008) /* 110 */ + #define EHCI_CMD_FRAME_SIZE_8 (0x0000800C) /* 111 */ + + +/* Hardware Rev 4.0 related change */ +#ifdef STREAM_ENABLE + /* Mode Register Bit Masks */ + #define VUSBHS_MODE_CTRL_MODE_IDLE (0x00000010) + #define VUSBHS_MODE_CTRL_MODE_DEV (0x00000012) + #define VUSBHS_MODE_CTRL_MODE_HOST (0x00000013) + #define VUSBHS_MODE_BIG_ENDIAN (0x00000014) + #define VUSBHS_MODE_SETUP_LOCK_DISABLE (0x00000008) + +#else + /* Mode Register Bit Masks */ + #define VUSBHS_MODE_CTRL_MODE_IDLE (0x00000000) + #define VUSBHS_MODE_CTRL_MODE_DEV (0x00000002) + #define VUSBHS_MODE_CTRL_MODE_HOST (0x00000003) + #define VUSBHS_MODE_BIG_ENDIAN (0x00000004) + #define VUSBHS_MODE_SETUP_LOCK_DISABLE (0x00000008) +#endif + +/* Interrupt Enable Register Bit Masks */ +#define EHCI_INTR_INT_EN (0x00000001) +#define EHCI_INTR_ERR_INT_EN (0x00000002) +#define EHCI_INTR_PORT_CHANGE_DETECT_EN (0x00000004) + +#define EHCI_INTR_ASYNC_ADV_AAE (0x00000020) + #define EHCI_INTR_ASYNC_ADV_AAE_ENABLE (0x00000020) /* | with this to enable */ + #define EHCI_INTR_ASYNC_ADV_AAE_DISABLE (0xFFFFFFDF) /* & with this to disable */ + +#define EHCI_INTR_RESET_EN (0x00000040) +#define EHCI_INTR_SOF_UFRAME_EN (0x00000080) +#define EHCI_INTR_DEVICE_SUSPEND (0x00000100) + +/* Interrupt Status Register Masks */ +#define EHCI_STS_SOF (0x00000080) +#define EHCI_STS_RESET (0x00000040) +#define EHCI_STS_PORT_CHANGE (0x00000004) +#define EHCI_STS_ERR (0x00000002) +#define EHCI_STS_INT (0x00000001) +#define EHCI_STS_SUSPEND (0x00000100) +#define EHCI_STS_HC_HALTED (0x00001000) + +/* Endpoint Queue Head Bit Masks */ +#define VUSB_EP_QUEUE_HEAD_IOS (0x00008000) +#define VUSB_EP_QUEUE_HEAD_IOC (0x00008000) +#define VUSB_EP_QUEUE_HEAD_INT (0x00000100) +#define VUSB_EP_QUEUE_HEAD_NEXT_TERMINATE (0x00000001) +#define VUSB_EP_QUEUE_HEAD_MAX_PKT_LEN_POS (16) +#define VUSB_EP_QUEUE_HEAD_ZERO_LEN_TER_SEL (0x20000000) +#define VUSB_EP_QUEUE_HEAD_MULT_POS (30) +#define VUSB_EP_MAX_LENGTH_TRANSFER (0x4000) + +#define VUSB_EP_QUEUE_HEAD_STATUS_ACTIVE (0x00000080) + +#define VUSBHS_TD_NEXT_TERMINATE (0x00000001) +#define VUSBHS_TD_IOC (0x00008000) +#define VUSBHS_TD_STATUS_ACTIVE (0x00000080) +#define VUSBHS_TD_STATUS_HALTED (0x00000040) +#define VUSBHS_TD_RESERVED_FIELDS (0x00007F00) +#define VUSBHS_TD_ERROR_MASK (0x68) +#define VUSBHS_TD_ADDR_MASK (0xFFFFFFE0) +#define VUSBHS_TD_LENGTH_BIT_POS (16) + +#define EHCI_EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) +#define EHCI_EPCTRL_TX_EP_STALL (0x00010000) +#define EHCI_EPCTRL_RX_EP_STALL (0x00000001) +#define EHCI_EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) +#define EHCI_EPCTRL_RX_ENABLE (0x00000080) +#define EHCI_EPCTRL_TX_ENABLE (0x00800000) +#define EHCI_EPCTRL_CONTROL (0x00000000) +#define EHCI_EPCTRL_ISOCHRONOUS (0x00040000) +#define EHCI_EPCTRL_BULK (0x00080000) +#define EHCI_EPCTRL_INT (0x000C0000) +#define EHCI_EPCTRL_TX_TYPE (0x000C0000) +#define EHCI_EPCTRL_RX_TYPE (0x0000000C) +#define EHCI_EPCTRL_DATA_TOGGLE_INHIBIT (0x00000020) +#define EHCI_EPCTRL_TX_EP_TYPE_SHIFT (18) +#define EHCI_EPCTRL_RX_EP_TYPE_SHIFT (2) + +#define EHCI_PORTSCX_FORCE_FULL_SPEED_CONNECT (0x01000000) // set bit 24 (PFSC) in PORTSCX register +#define EHCI_PORTSCX_PHY_CLOCK_DISABLE (0x00800000) // set bit 23 (PHCD) in PORTSCX register +#define EHCI_PORTSCX_PORT_TEST_MODE_DISABLE_MASK (0x000F0000) +#define EHCI_PORTSCX_PORT_TEST_CONTROL_J_STATE (0x00010000) +#define EHCI_PORTSCX_PORT_TEST_CONTROL_K_STATE (0x00020000) +#define EHCI_PORTSCX_PORT_TEST_CONTROL_SE0_NAK (0x00030000) +#define EHCI_PORTSCX_PORT_TEST_CONTROL_PACKET (0x00040000) +#define EHCI_PORTSCX_PORT_TEST_CONTROL_FORCE_HS (0x00050000) +#define EHCI_PORTSCX_PORT_TEST_CONTROL_FORCE_FS (0x00060000) +#define EHCI_PORTSCX_PORT_TEST_CONTROL_FORCE_LS (0x00070000) +#define EHCI_PORTSCX_PORT_POWER (0x00001000) +#define EHCI_PORTSCX_LINE_STATUS_BITS (0x00000C00) +#define EHCI_PORTSCX_LINE_STATUS_SE0 (0x00000000) +#define EHCI_PORTSCX_LINE_STATUS_KSTATE (0x00000400) +#define EHCI_PORTSCX_LINE_STATUS_JSTATE (0x00000800) +#define EHCI_PORTSCX_PORT_HIGH_SPEED (0x00000200) +#define EHCI_PORTSCX_PORT_RESET (0x00000100) +#define EHCI_PORTSCX_PORT_SUSPEND (0x00000080) +#define EHCI_PORTSCX_PORT_FORCE_RESUME (0x00000040) +#define EHCI_PORTSCX_PORT_EN_DIS_CHANGE (0x00000008) +#define EHCI_PORTSCX_PORT_ENABLE (0x00000004) +#define EHCI_PORTSCX_CONNECT_STATUS_CHANGE (0x00000002) +#define EHCI_PORTSCX_CURRENT_CONNECT_STATUS (0x00000001) + +#define VUSBHS_PORTSCX_PORT_SPEED_FULL (0x00000000) +#define VUSBHS_PORTSCX_PORT_SPEED_LOW (0x04000000) +#define VUSBHS_PORTSCX_PORT_SPEED_HIGH (0x08000000) +#define VUSBHS_SPEED_MASK (0x0C000000) +#define VUSBHS_SPEED_BIT_POS (26) + +#define EHCI_PORTSCX_W1C_BITS (0x2A) +#define VUSB_EP_QH_PACKET_SIZE (0x3FFF0000) +#define VUSB_EP_TR_PACKET_SIZE (0x7FFF0000) + +#define VUSBHS_FRINDEX_MS_MASK (0xFFFFFFF8) +#define VUSBHS_ADDRESS_BIT_SHIFT (25) + +#define VUSB20_MAX_ENDPTS_SUPPORTED (0x1F) +#define EHCI_HCC_PARAMS_64_BIT_ADDR_CAP (0x01) +#define EHCI_HCC_PARAMS_PGM_FRM_LIST_FLAG (0x02) +#define EHCI_HCC_PARAMS_ASYNC_PARK_CAP (0x04) +#define EHCI_HCC_PARAMS_ISOCH_SCHED_THRESHOLD (0xF0) +#define EHCI_HCC_PARAMS_ISOCH_FRAME_CACHED (0x80) + +#define VUSB20_HCS_PARAMS_PORT_POWER_CONTROL_FLAG (0x10) + +#define VUSB20_HOST_INTR_EN_BITS (0x37) + +#define VUSB20_DEFAULT_PERIODIC_FRAME_LIST_SIZE (1024) +#define VUSB20_NEW_PERIODIC_FRAME_LIST_BITS (2) +#define EHCI_FRAME_LIST_ELEMENT_POINTER_T_BIT (0x01) +#define EHCI_ITD_T_BIT (0x01) +#define EHCI_SITD_T_BIT (0x01) +#define EHCI_QUEUE_HEAD_POINTER_T_BIT (0x01) + + +/************************************************************ +Split transatcions specific defines +************************************************************/ +#define EHCI_START_SPLIT_MAX_BUDGET 188 + +#define EHCI_ELEMENT_TYPE_ITD (0x00) +#define EHCI_ELEMENT_TYPE_QH (0x02) +#define EHCI_ELEMENT_TYPE_SITD (0x04) +#define EHCI_ELEMENT_TYPE_FSTN (0x06) +#define EHCI_ELEMENT_TYPE_MASK (0x06) + +#define EHCI_FRAME_LIST_ELEMENT_TYPE_ITD (0x00) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_QH (0x01) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_SITD (0x02) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_FSTN (0x03) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_BIT_POS (1) + + +#define EHCI_QH_ELEMENT_TYPE_ITD (0x00) +#define EHCI_QH_ELEMENT_TYPE_QH (0x01) +#define EHCI_QH_ELEMENT_TYPE_SITD (0x02) +#define EHCI_QH_ELEMENT_TYPE_FSTN (0x03) + +#define EHCI_QH_ELEMENT_TYPE_BIT_POS (1) + +#define EHCI_QTD_PID_OUT_TOKEN (0x000) +#define EHCI_QTD_PID_IN_TOKEN (0x100) +#define EHCI_QTD_PID_SETUP_TOKEN (0x200) +#define EHCI_QTD_IOC (0x8000) +#define EHCI_QTD_STATUS_ACTIVE (0x0080) +#define EHCI_QTD_STATUS_HALTED (0x0040) +#define EHCI_QTD_PID_SETUP (0x0200) +#define EHCI_QTD_PID_IN (0x0100) +#define EHCI_QTD_PID_OUT (0x0000) +#define EHCI_QTD_LENGTH_BIT_POS (16) +#define EHCI_QTD_DATA_TOGGLE (0x80000000) +#define EHCI_QTD_DATA_TOGGLE_BIT_POS (31) +#define EHCI_QTD_LENGTH_BIT_MASK (0x7FFF0000) +#define EHCI_QTD_ERROR_BITS_MASK (0x0000003E) +#define EHCI_QTD_DEFAULT_CERR_VALUE (0xC00) + +#define EHCI_SETUP_TOKEN (2) +#define EHCI_OUT_TOKEN (0) +#define EHCI_IN_TOKEN (1) + +#define EHCI_QTD_T_BIT (0x01) + +#define EHCI_QH_ENDPOINT_SPEED_FULL (0x00) +#define EHCI_QH_ENDPOINT_SPEED_LOW (0x01) +#define EHCI_QH_ENDPOINT_SPEED_HIGH (0x02) +#define EHCI_QH_ENDPOINT_SPEED_RESERVED (0x03) + +#define EHCI_ITD_LENGTH_BIT_POS (16) +#define EHCI_ITD_IOC_BIT (0x00008000) +#define EHCI_ITD_ACTIVE_BIT (0x80000000) +#define EHCI_ITD_PG_SELECT_BIT_POS (12) +#define EHCI_ITD_DIRECTION_BIT_POS (11) +#define EHCI_ITD_EP_BIT_POS (8) +#define EHCI_ITD_STATUS (0xF0000000) + #define EHCI_ITD_STATUS_ACTIVE (0x80000000) /*bit 4 = 1000*/ + #define EHCI_ITD_STATUS_DATA_BUFFER_ERR (0x40000000) /*bit 3 = 0100*/ + #define EHCI_ITD_STATUS_BABBLE_ERROR (0x20000000) /*bit 2 = 0010*/ + #define EHCI_ITD_STATUS_TRANSACTION_ERR (0x10000000) /*bit 4 = 0001*/ + +#define EHCI_ITD_LENGTH_TRANSMITTED (0x0FFF0000) +#define EHCI_ITD_BUFFER_OFFSET (0x00000FFF) +#define EHCI_ITD_PAGE_NUMBER (0x00007000) +#define EHCI_ITD_BUFFER_POINTER (0xFFFFF000) +#define EHCI_ITD_MULTI_TRANSACTION_BITS (0x00000003) + + + +/* SITD position bits */ +#define EHCI_SITD_DIRECTION_BIT_POS (31) +#define EHCI_SITD_PORT_NUMBER_BIT_POS (24) +#define EHCI_SITD_HUB_ADDR_BIT_POS (16) +#define EHCI_SITD_EP_ADDR_BIT_POS (8) + +#define EHCI_SITD_COMPLETE_SPLIT_MASK_BIT_POS (8) + +#define EHCI_SITD_IOC_BIT_SET (0x80000000) +#define EHCI_SITD_PAGE_SELECT_BIT_POS (30) +#define EHCI_SITD_TRANSFER_LENGTH_BIT_POS (16) +#define EHCI_SITD_STATUS_ACTIVE (0x80) + +#define EHCI_SITD_STATUS (0xFF) +#define EHCI_SITD_LENGTH_TRANSMITTED (0x03FF0000) +#define EHCI_SITD_BUFFER_OFFSET (0x00000FFF) +#define EHCI_SITD_PAGE_NUMBER (0x40000000) +#define EHCI_SITD_BUFFER_POINTER (0xFFFFF000) + + + +#define EHCI_SITD_BUFFER_PTR_BIT_POS (12) +#define EHCI_SITD_TP_BIT_POS (3) + #define EHCI_SITD_TP_ALL (0) + #define EHCI_SITD_TP_BEGIN (1) + #define EHCI_SITD_TP_MID (2) + #define EHCI_SITD_TP_END (3) + + + +/* Interrupt enable bit masks */ +#define EHCI_IER_ASYNCH_ADVANCE (0x00000020) +#define EHCI_IER_HOST_SYS_ERROR (0x00000010) +#define EHCI_IER_FRAME_LIST_ROLLOVER (0x00000008) +#define EHCI_IER_PORT_CHANGE (0x00000004) +#define EHCI_IER_USB_ERROR (0x00000002) +#define EHCI_IER_USB_INTERRUPT (0x00000001) + +/* Interrupt status bit masks */ +#define EHCI_STS_RECLAIMATION (0x00002000) +#define EHCI_STS_SOF_COUNT (0x00000080) +#define EHCI_STS_ASYNCH_ADVANCE (0x00000020) +#define EHCI_STS_HOST_SYS_ERROR (0x00000010) +#define EHCI_STS_FRAME_LIST_ROLLOVER (0x00000008) +#define EHCI_STS_PORT_CHANGE (0x00000004) +#define EHCI_STS_USB_ERROR (0x00000002) +#define EHCI_STS_USB_INTERRUPT (0x00000001) + +/* Status bit masks */ +#define EHCI_STS_ASYNCH_SCHEDULE (0x00008000) +#define EHCI_STS_PERIODIC_SCHEDULE (0x00004000) +#define EHCI_STS_RECLAMATION (0x00002000) +#define EHCI_STS_HC_HALTED (0x00001000) + +/* USB command bit masks */ +#define EHCI_USBCMD_ASYNC_SCHED_ENABLE (0x00000020) +#define EHCI_USBCMD_PERIODIC_SCHED_ENABLE (0x00000010) + +#define EHCI_HCS_PARAMS_N_PORTS (0x0F) + +#define VUSB_HS_DELAY (3500) + +#define EHCI_QH_EP_NUM_MASK (0x0F00) +#define EHCI_QH_EP_NUM_BITS_POS (8) +#define EHCI_QH_DEVICE_ADDRESS_MASK (0x7F) +#define EHCI_QH_SPEED_BITS_POS (12) +#define EHCI_QH_MAX_PKT_SIZE_BITS_POS (16) +#define EHCI_QH_NAK_COUNT_RL_BITS_POS (28) +#define EHCI_QH_EP_CTRL_FLAG_BIT_POS (27) +#define EHCI_QH_HEAD_RECLAMATION_BIT_POS (15) +#define EHCI_QH_DTC_BIT_POS (14) +#define EHCI_QH_HIGH_BW_MULT_BIT_POS (30) +#define EHCI_QH_HUB_PORT_NUM_BITS_POS (23) +#define EHCI_QH_HUB_ADDR_BITS_POS (16) +#define EHCI_QH_SPLIT_COMPLETION_MASK_BITS_POS (8) +#define EHCI_QH_SPLIT_COMPLETION_MASK (0xFF00) +#define EHCI_QH_INTR_SCHED_MASK (0xFF) +#define EHCI_QH_INACTIVATE_NEXT_TR_BIT_POS (7) +#define EHCI_QH_HORIZ_PHY_ADDRESS_MASK (0xFFFFFFE0) +#define EHCI_QH_TR_OVERLAY_DT_BIT (0x80000000) + +#define EHCI_SITD_SPLIT_COMPLETION_MASK_BITS_POS (8) + +#define EHCI_INTR_NO_THRESHOLD_IMMEDIATE (0x00010000) +#define EHCI_NEW_PERIODIC_FRAME_LIST_SIZE (1024) +#define EHCI_FRAME_LIST_SIZE_BITS_POS (2) +#define EHCI_HORIZ_PHY_ADDRESS_MASK (0xFFFFFFE0) + +#define DEFAULT_MAX_NAK_COUNT (15) + +/* OTG Status and control register bit masks */ + +/* OTG interrupt enable bit masks */ +#define VUSBHS_OTGSC_INTERRUPT_ENABLE_BITS_MASK (0x5F000000) +#define VUSBHS_OTGSC_DPIE (0x40000000) /* Data-line pulsing IE */ +#define VUSBHS_OTGSC_1MSIE (0x20000000) +#define VUSBHS_OTGSC_BSEIE (0x10000000) /* B-session end IE */ +#define VUSBHS_OTGSC_BSVIE (0x08000000) /* B-session valid IE */ +#define VUSBHS_OTGSC_ASVIE (0x04000000) /* A-session valid IE */ +#define VUSBHS_OTGSC_AVVIE (0x02000000) /* A-V-bus valid IE */ +#define VUSBHS_OTGSC_IDIE (0x01000000) /* OTG ID IE */ + +/* OTG interrupt status bit masks */ +#define VUSBHS_OTGSC_INTERRUPT_STATUS_BITS_MASK (0x005F0000) +#define VUSBHS_OTGSC_DPIS (0x00400000) /* Data-line pulsing IS */ +#define VUSBHS_OTGSC_1MSIS (0x00200000) +#define VUSBHS_OTGSC_BSEIS (0x00100000) /* B-session end IS */ +#define VUSBHS_OTGSC_BSVIS (0x00080000) /* B-session valid IS */ +#define VUSBHS_OTGSC_ASVIS (0x00040000) /* A-session valid IS */ +#define VUSBHS_OTGSC_AVVIS (0x00020000) /* A-Vbus valid IS */ +#define VUSBHS_OTGSC_IDIS (0x00010000) /* OTG ID IS */ + +/* OTG status bit masks */ +#define VUSBHS_OTGSC_DPS (0x00004000) +#define VUSBHS_OTGSC_BSE (0x00001000) /* B-session end */ +#define VUSBHS_OTGSC_BSV (0x00000800) /* B-session valid */ +#define VUSBHS_OTGSC_ASV (0x00000400) /* A-session valid */ +#define VUSBHS_OTGSC_AVV (0x00000200) /* A-Vbus Valid */ +#define VUSBHS_OTGSC_ID (0x00000100) /* OTG ID */ + +/* OTG control bit masks */ +#define VUSBHS_OTGSC_CTL_BITS (0x2F) +#define VUSBHS_OTGSC_HABA (0x00000080) /* hardware assisted data pulse bits*/ +#define VUSBHS_OTGSC_HADP (0x00000040) /* hardware assisted data pulse bits*/ + +/*#include */ diff --git a/drivers/usb/host/ehci-ci13612.c b/drivers/usb/host/ehci-ci13612.c new file mode 100644 index 0000000..82ff48a --- /dev/null +++ b/drivers/usb/host/ehci-ci13612.c @@ -0,0 +1,215 @@ + /* + * drivers/usb/host/ehci-ci13612.c + * + * USB Host Controller Driver for LSI's ACP + * + * Copyright (C) 2010 LSI Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include "ehci-ci13612.h" + + +/* Patch the code to fix the bugs in Bugzilla */ +static void ci13612_usb_setup(struct usb_hcd *hcd) +{ + int USB_TXFIFOTHRES, VUSB_HS_TX_BURST; + + /* fix Bugzilla #31874 */ + /* fix Bugzilla #32212 */ + VUSB_HS_TX_BURST = inl(USB_HWTXBUF) & 0x0f; + USB_TXFIFOTHRES = (inl(USB_TXFILLTUNING) & 0x3f0000) >> 16; + + printk(KERN_INFO "ehci-ci13612 (ci13612_usb_setup): " + "VUSB_HS_TX_BURST = 0x%x, USB_TXFIFOTHRES = 0x%x\n", + VUSB_HS_TX_BURST, USB_TXFIFOTHRES); + + return; +} + +/* called after powerup, by probe or system-pm "wakeup" */ +static int ehci_ci13612_reinit(struct ehci_hcd *ehci) +{ + ci13612_usb_setup(ehci_to_hcd(ehci)); + ehci_port_power(ehci, 0); + + return 0; +} + + +static int ci13612_ehci_init(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval = 0; + int len; + + + /* EHCI registers start at offset 0x100 */ + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); + len = HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); + + /* configure other settings */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + hcd->has_tt = 1; + + ehci->sbrn = 0x20; + + /* reset and halt controller */ + ehci_reset(ehci); + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + hcd->self.sg_tablesize = 0; + + retval = ehci_ci13612_reinit(ehci); + + return retval; +} + +static int ehci_run_fix(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 port_status; + unsigned burst_size; + int retval; + + /* fix Bugzilla 33669 */ + port_status = ehci_readl(ehci, &ehci->regs->port_status[0]); + printk(KERN_INFO "ehci_run: port_status = 0x%x\n", port_status); + if (port_status & 0x100) { + printk(KERN_ERR "USB port is in reset status, not able to " + "change host controller status to run\n"); + return -EFAULT; + } + + retval = ehci_run(hcd); + if (retval) + return retval; + + burst_size = ehci_readl(ehci, &ehci->regs->reserved[1]); + burst_size = (burst_size & 0xffff00ff) | 0x4000; /* TXPBURST */ + ehci_writel(ehci, burst_size, &ehci->regs->reserved[1]); + + return 0; +} + +static const struct hc_driver ci13612_hc_driver = { + .description = "ci13612_hcd", + .product_desc = "CI13612A EHCI USB Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2 | HCD_LOCAL_MEM, + .reset = ci13612_ehci_init, + .start = ehci_run_fix, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .get_frame_number = ehci_get_frame, + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#if defined(CONFIG_PM) + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, +}; + +static int ci13612_ehci_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + const struct hc_driver *driver = &ci13612_hc_driver; + void __iomem *USB_base = (void __iomem *) 0xF00A0000; + void __iomem *gpreg_base = (void __iomem *) 0xF000C000; + int irq; + int retval; + + + if (usb_disabled()) + return -ENODEV; + + /* Map the irq in the PPC476 to get the irq number */ + irq = irq_create_mapping(NULL, 31); + + if (NO_IRQ == irq) { + dev_dbg(&pdev->dev, "error mapping irq number\n"); + retval = -EBUSY; + goto fail_create_hcd; + } + + if (0 != irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH)) { + dev_dbg(&pdev->dev, "set_irq_type() failed\n"); + retval = -EBUSY; + goto fail_create_hcd; + } + + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) { + retval = -ENOMEM; + goto fail_create_hcd; + } + + hcd->rsrc_start = ci13612_PHY_ADDR; + hcd->rsrc_len = 0x20000; + + hcd->regs = USB_base; + + /* Setup GPREG for USB to enable the 6-bit address line */ + writel(0x0, gpreg_base + 0x8); + + retval = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (retval == 0) { + platform_set_drvdata(pdev, hcd); + return retval; + } + + usb_put_hcd(hcd); +fail_create_hcd: + dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); + return retval; +} + +static int ci13612_ehci_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + usb_put_hcd(hcd); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +// MODULE_ALIAS("platform:ci13612-ehci"); +MODULE_ALIAS("platform:20004a4000.usb"); + +static struct platform_driver ci13612_ehci_driver = { + .probe = ci13612_ehci_probe, + .remove = ci13612_ehci_remove, + .driver = { +// .name = "ci13612-ehci", + .name = "20004a4000.usb", + }, +}; diff --git a/drivers/usb/host/ehci-ci13612.h b/drivers/usb/host/ehci-ci13612.h new file mode 100644 index 0000000..bbba3f4 --- /dev/null +++ b/drivers/usb/host/ehci-ci13612.h @@ -0,0 +1,54 @@ +/* + * System definitions + */ +#define ci13612_PHY_ADDR 0x0020004A0000ULL +#define ci13162_PHY_ADDR_SIZE 0x20000 + +/* + * Host interface registers + */ + +/* define CI13612 USB registers here */ +#define CI13612_USB_BASE ((unsigned) hcd->regs) + +#define USB_ID (CI13612_USB_BASE + 0x0000) +#define USB_HWGENERAL (CI13612_USB_BASE + 0x0004) +#define USB_HWHOST (CI13612_USB_BASE + 0x0008) +#define USB_HWDEVICE (CI13612_USB_BASE + 0x000C) +#define USB_HWTXBUF (CI13612_USB_BASE + 0x0010) +#define USB_HWRXBUF (CI13612_USB_BASE + 0x0014) +#define USB_GPTIMER0LD (CI13612_USB_BASE + 0x0080) +#define USB_GPTIMER0CTRL (CI13612_USB_BASE + 0x0084) +#define USB_GPTIMER1LD (CI13612_USB_BASE + 0x0088) +#define USB_GPTIMER1CTRL (CI13612_USB_BASE + 0x008c) +#define USB_SBUSCFG (CI13612_USB_BASE + 0x0090) + +#define USB_CAPLENGTH (CI13612_USB_BASE + 0x0100) /* 8 bit */ +#define USB_HCIVERSION (CI13612_USB_BASE + 0x0102) /* 16 bit */ +#define USB_HCSPARAMS (CI13612_USB_BASE + 0x0104) +#define USB_HCCPARAMS (CI13612_USB_BASE + 0x0108) +#define USB_DCIVERSION (CI13612_USB_BASE + 0x0120) /* 16 bit */ +#define USB_DCCPARAMS (CI13612_USB_BASE + 0x0124) +#define USB_USBCMD (CI13612_USB_BASE + 0x0140) +#define USB_USBSTS (CI13612_USB_BASE + 0x0144) +#define USB_USBINTR (CI13612_USB_BASE + 0x0148) +#define USB_FRINDEX (CI13612_USB_BASE + 0x014C) +#define USB_DEVICEADDR (CI13612_USB_BASE + 0x0154) +#define USB_ENDPOINTLISTADDR (CI13612_USB_BASE + 0x0158) +#define USB_TTCTRL (CI13612_USB_BASE + 0x015C) +#define USB_BURSTSIZE (CI13612_USB_BASE + 0x0160) +#define USB_TXFILLTUNING (CI13612_USB_BASE + 0x0164) +#define USB_ICUSB (CI13612_USB_BASE + 0x016C) +#define USB_ULPI_VIEWPORT (CI13612_USB_BASE + 0x0170) +#define USB_ENDPTNAK (CI13612_USB_BASE + 0x0178) +#define USB_ENDPTNAKEN (CI13612_USB_BASE + 0x017C) +#define USB_CONFIGFLAG (CI13612_USB_BASE + 0x0180) +#define USB_PORTSC (CI13612_USB_BASE + 0x0184) +#define USB_OTGSC (CI13612_USB_BASE + 0x01A4) +#define USB_USBMODE (CI13612_USB_BASE + 0x01A8) +#define USB_ENDPTSETUPSTAT (CI13612_USB_BASE + 0x01AC) +#define USB_ENDPTPRIME (CI13612_USB_BASE + 0x01B0) +#define USB_ENDPTFLUSH (CI13612_USB_BASE + 0x01B4) +#define USB_ENDPTSTAT (CI13612_USB_BASE + 0x01B8) +#define USB_ENDPTCOMPLETE (CI13612_USB_BASE + 0x01BC) +#define USB_ENDPTCTRL(n) (CI13612_USB_BASE + 0x01C0 + (4 * (n))) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 9ff9abc..d460db7 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1284,12 +1284,34 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_grlib_driver #endif + +#ifdef CONFIG_USB_CI13612_HCD +#include "ehci-ci13612.c" +#define PLATFORM_DRIVER ci13612_ehci_driver +#endif + + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) #error "missing bus glue for ehci-hcd" #endif + +static void ci13612_device_release(struct device *dev) +{ +} + +static struct platform_device ci13612_device = { + .name = "ci13612-ehci", + .id = -1, + .dev = { + .release = ci13612_device_release, + }, +}; + + + static int __init ehci_hcd_init(void) { int retval = 0; @@ -1341,6 +1363,11 @@ static int __init ehci_hcd_init(void) goto clean3; #endif + + retval = platform_device_register(&ci13612_device); + if (retval < 0) + goto err_device_register; + #ifdef XILINX_OF_PLATFORM_DRIVER retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); if (retval < 0) @@ -1348,6 +1375,7 @@ static int __init ehci_hcd_init(void) #endif return retval; +err_device_register: #ifdef XILINX_OF_PLATFORM_DRIVER /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ clean4: @@ -1380,6 +1408,9 @@ module_init(ehci_hcd_init); static void __exit ehci_hcd_cleanup(void) { + +platform_device_unregister(&ci13612_device); + #ifdef XILINX_OF_PLATFORM_DRIVER platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); #endif diff --git a/include/linux/rio.h b/include/linux/rio.h index 4d50611..8fb185a 100644 --- a/include/linux/rio.h +++ b/include/linux/rio.h @@ -304,6 +304,17 @@ struct rio_ops { int (*cwrite) (struct rio_mport *mport, int index, u16 destid, u8 hopcount, u32 offset, int len, u32 data); int (*dsend) (struct rio_mport *mport, int index, u16 destid, u16 data); + + /* Functions to access port's mailbox routines (may be NULL if not supported) */ + // int (*hw_add_outb_message)(struct rio_mport *mport, struct rio_dev *rdev, int mbox, void *buffer, size_t len); + // int (*hw_add_inb_buffer)(struct rio_mport *mport, int mbox, void *buf); + // void* (*hw_get_inb_message)(struct rio_mport *mport, int mbox); + + /* Functions that support ioremap style access to endpoints + * (may be NULL if not supported) */ + void* (*rio_ioremap)(void* rio_address, u16 destid, unsigned int length); + void (*rio_unmap)(void* address); + int (*pwenable) (struct rio_mport *mport, int enable); int (*open_outb_mbox)(struct rio_mport *mport, void *dev_id, int mbox, int entries); @@ -402,4 +413,7 @@ extern void rio_close_inb_mbox(struct rio_mport *, int); extern int rio_open_outb_mbox(struct rio_mport *, void *, int, int); extern void rio_close_outb_mbox(struct rio_mport *, int); +extern void* rio_ioremap(struct rio_mport *mport, void* rio_address, u16 destid, unsigned int length); +extern void rio_unmap(struct rio_mport *mport, void* address); + #endif /* LINUX_RIO_H */ diff --git a/kernel/smp.c b/kernel/smp.c index fb67dfa..7370bda 100644 --- a/kernel/smp.c +++ b/kernel/smp.c @@ -25,6 +25,7 @@ static struct { enum { CSD_FLAG_LOCK = 0x01, + CSD_FLAG_NOWAIT = 0x02, }; struct call_function_data { @@ -263,6 +264,8 @@ void generic_smp_call_function_single_interrupt(void) while (!list_empty(&list)) { struct call_single_data *data; + void (*func)(void *); + void *info; data = list_entry(list.next, struct call_single_data, list); list_del(&data->list); @@ -273,12 +276,21 @@ void generic_smp_call_function_single_interrupt(void) * so save them away before making the call: */ data_flags = data->flags; - - data->func(data->info); + func = data->func; + info = data->info; /* + * Unlock before calling func so that func never has + * to return. + * * Unlocked CSDs are valid through generic_exec_single(): */ + if ((data_flags & CSD_FLAG_LOCK) && + (data_flags & CSD_FLAG_NOWAIT)) + csd_unlock(data); + + func(info); + if (data_flags & CSD_FLAG_LOCK) csd_unlock(data); } @@ -332,6 +344,9 @@ int smp_call_function_single(int cpu, smp_call_func_t func, void *info, csd_lock(data); + if (!wait) + data->flags |= CSD_FLAG_NOWAIT; + data->func = func; data->info = info; generic_exec_single(cpu, data, wait); diff --git a/scripts/rw.sh b/scripts/rw.sh new file mode 100644 index 0000000..a393a7c --- /dev/null +++ b/scripts/rw.sh @@ -0,0 +1,120 @@ +#!/bin/sh +# Generate tags or cscope files +# Usage tags.sh +# +# mode may be any of: tags, TAGS, cscope +# +# Uses the following environment variables: +# ARCH, SUBARCH, srctree, src, obj + +if [ "$KBUILD_VERBOSE" = "1" ]; then + set -x +fi + +# This is a duplicate of RCS_FIND_IGNORE without escaped '()' +ignore="( -name SCCS -o -name BitKeeper -o -name .svn -o \ + -name CVS -o -name .pc -o -name .hg -o \ + -name .git ) \ + -prune -o" + +# Do not use full path is we do not use O=.. builds +if [ "${KBUILD_SRC}" = "" ]; then + tree= +else + tree=${srctree}/ +fi + +# Detect if ALLSOURCE_ARCHS is set. If not, we assume SRCARCH +if [ "${ALLSOURCE_ARCHS}" = "" ]; then + ALLSOURCE_ARCHS=${SRCARCH} +fi + +# find sources in arch/$ARCH +find_arch_sources() +{ + find ${tree}arch/$1 $ignore -name "$2" -print; +} + +# find sources in arch/$1/include +find_arch_include_sources() +{ + find ${tree}arch/$1/include $ignore -name "$2" -print; +} + +# find sources in include/ +find_include_sources() +{ + find ${tree}include $ignore -name config -prune -o -name "$1" -print; +} + +# find sources in rest of tree +# we could benefit from a list of dirs to search in here +find_other_sources() +{ + find ${tree}* $ignore \ + \( -name include -o -name arch -o -name '.tmp_*' \) -prune -o \ + -name "$1" -print; +} + +find_sources() +{ + find_arch_sources $1 "$2" +} + +all_sources() +{ + for arch in $ALLSOURCE_ARCHS + do + find_sources $arch '*.[chS]' + done + if [ ! -z "$archinclude" ]; then + find_arch_include_sources $archinclude '*.[chS]' + fi + find_include_sources '*.[chS]' + find_other_sources '*.[chS]' +} + +all_kconfigs() +{ + for arch in $ALLSOURCE_ARCHS; do + find_sources $arch 'Kconfig*' + done + find_other_sources 'Kconfig*' +} + +all_defconfigs() +{ + find_sources $ALLSOURCE_ARCHS "defconfig" +} + +#docscope() +#{ +# (echo \-k; echo \-q; all_sources) > cscope.files +# cscope -b +#} +# +#case "$1" in +# "cscope") +# docscope +# ;; +# +# "tags") +# xtags ctags +# ;; +# +# "TAGS") +# xtags etags +# ;; +#esac + +TEMP=`mktemp rw.path.XXXXXXXXXXXX` || exit 1 +echo srchpath add linux > $TEMP + +for file in `all_sources` + do + echo srchpath add linux/`dirname $file` >> $TEMP +done + +cat $TEMP | uniq > rw.path + +rm -f $TEMP diff --git a/scripts/tags.sh b/scripts/tags.sh index 75c5d24..7935fa5 100755 --- a/scripts/tags.sh +++ b/scripts/tags.sh @@ -93,6 +93,7 @@ all_sources() find_sources $arch '*.[chS]' done find_other_sources '*.[chS]' + find arch/${SRCARCH} -type f | egrep '(\.c$|\.h$|\.s$|\.S$|\.java$)' } all_kconfigs() @@ -111,7 +112,7 @@ all_defconfigs() docscope() { (echo \-k; echo \-q; all_sources) > cscope.files - cscope -b -f cscope.out + cscope -b } dogtags() -- 1.7.0.4