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author | Sona Sarmadi <sona.sarmadi@enea.com> | 2018-09-20 09:34:05 +0200 |
---|---|---|
committer | Martin Borg <martin.borg@enea.com> | 2018-09-21 14:42:14 +0200 |
commit | 7954c83819f78fd8baf68615d592eb0886a8af65 (patch) | |
tree | 476a990f4c018acdd8d44b0bf66d685c4287826f /recipes-kernel | |
parent | e862c3d668979a42caacee10847b39b5827a20fb (diff) | |
download | meta-enea-bsp-x86-7954c83819f78fd8baf68615d592eb0886a8af65.tar.gz |
linux-intel-rt: Fix for CVE-2018-15572
References:
https://github.com/nluedtke/linux_kernel_cves/blob/master/4.14/4.14_security.txt
https://nvd.nist.gov/vuln/detail/CVE-2018-15572
Change-Id: Ice34aee00bfc9b05326422dbc2ebd68326e34e55
Signed-off-by: Sona Sarmadi <sona.sarmadi@enea.com>
Diffstat (limited to 'recipes-kernel')
-rw-r--r-- | recipes-kernel/linux/linux-intel-rt_4.14.bbappend | 1 | ||||
-rw-r--r-- | recipes-kernel/linux/linux-intel/CVE-2018-15572.patch | 99 |
2 files changed, 100 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-intel-rt_4.14.bbappend b/recipes-kernel/linux/linux-intel-rt_4.14.bbappend index 53ed430..530ea31 100644 --- a/recipes-kernel/linux/linux-intel-rt_4.14.bbappend +++ b/recipes-kernel/linux/linux-intel-rt_4.14.bbappend | |||
@@ -10,6 +10,7 @@ SRC_URI_append = " git://git@git.enea.com/linux/enea-kernel-cache.git;protocol=s | |||
10 | file://CVE-2018-12233.patch \ | 10 | file://CVE-2018-12233.patch \ |
11 | file://CVE-2018-13093.patch \ | 11 | file://CVE-2018-13093.patch \ |
12 | file://CVE-2018-13094.patch \ | 12 | file://CVE-2018-13094.patch \ |
13 | file://CVE-2018-15572.patch \ | ||
13 | " | 14 | " |
14 | 15 | ||
15 | # Debug tools support | 16 | # Debug tools support |
diff --git a/recipes-kernel/linux/linux-intel/CVE-2018-15572.patch b/recipes-kernel/linux/linux-intel/CVE-2018-15572.patch new file mode 100644 index 0000000..27722af --- /dev/null +++ b/recipes-kernel/linux/linux-intel/CVE-2018-15572.patch | |||
@@ -0,0 +1,99 @@ | |||
1 | From f374b5593e44c01265156b4c4070b618097f401b Mon Sep 17 00:00:00 2001 | ||
2 | From: Jiri Kosina <jkosina@suse.cz> | ||
3 | Date: Thu, 26 Jul 2018 13:14:55 +0200 | ||
4 | Subject: [PATCH] x86/speculation: Protect against userspace-userspace | ||
5 | spectreRSB | ||
6 | |||
7 | commit fdf82a7856b32d905c39afc85e34364491e46346 upstream. | ||
8 | |||
9 | The article "Spectre Returns! Speculation Attacks using the Return Stack | ||
10 | Buffer" [1] describes two new (sub-)variants of spectrev2-like attacks, | ||
11 | making use solely of the RSB contents even on CPUs that don't fallback to | ||
12 | BTB on RSB underflow (Skylake+). | ||
13 | |||
14 | Mitigate userspace-userspace attacks by always unconditionally filling RSB on | ||
15 | context switch when the generic spectrev2 mitigation has been enabled. | ||
16 | |||
17 | [1] https://arxiv.org/pdf/1807.07940.pdf | ||
18 | |||
19 | CVE: CVE-2018-15572 | ||
20 | Upstream-Status: Backport | ||
21 | |||
22 | Signed-off-by: Jiri Kosina <jkosina@suse.cz> | ||
23 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | ||
24 | Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> | ||
25 | Acked-by: Tim Chen <tim.c.chen@linux.intel.com> | ||
26 | Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | ||
27 | Cc: Borislav Petkov <bp@suse.de> | ||
28 | Cc: David Woodhouse <dwmw@amazon.co.uk> | ||
29 | Cc: Peter Zijlstra <peterz@infradead.org> | ||
30 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | ||
31 | Cc: stable@vger.kernel.org | ||
32 | Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1807261308190.997@cbobk.fhfr.pm | ||
33 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | ||
34 | Signed-off-by: Sona Sarmadi <sona.sarmadi@enea.com> | ||
35 | --- | ||
36 | arch/x86/kernel/cpu/bugs.c | 38 +++++++------------------------------- | ||
37 | 1 file changed, 7 insertions(+), 31 deletions(-) | ||
38 | |||
39 | diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c | ||
40 | index 7416fc2..1d3bbaa 100644 | ||
41 | --- a/arch/x86/kernel/cpu/bugs.c | ||
42 | +++ b/arch/x86/kernel/cpu/bugs.c | ||
43 | @@ -311,23 +311,6 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) | ||
44 | return cmd; | ||
45 | } | ||
46 | |||
47 | -/* Check for Skylake-like CPUs (for RSB handling) */ | ||
48 | -static bool __init is_skylake_era(void) | ||
49 | -{ | ||
50 | - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | ||
51 | - boot_cpu_data.x86 == 6) { | ||
52 | - switch (boot_cpu_data.x86_model) { | ||
53 | - case INTEL_FAM6_SKYLAKE_MOBILE: | ||
54 | - case INTEL_FAM6_SKYLAKE_DESKTOP: | ||
55 | - case INTEL_FAM6_SKYLAKE_X: | ||
56 | - case INTEL_FAM6_KABYLAKE_MOBILE: | ||
57 | - case INTEL_FAM6_KABYLAKE_DESKTOP: | ||
58 | - return true; | ||
59 | - } | ||
60 | - } | ||
61 | - return false; | ||
62 | -} | ||
63 | - | ||
64 | static void __init spectre_v2_select_mitigation(void) | ||
65 | { | ||
66 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | ||
67 | @@ -388,22 +371,15 @@ static void __init spectre_v2_select_mitigation(void) | ||
68 | pr_info("%s\n", spectre_v2_strings[mode]); | ||
69 | |||
70 | /* | ||
71 | - * If neither SMEP nor PTI are available, there is a risk of | ||
72 | - * hitting userspace addresses in the RSB after a context switch | ||
73 | - * from a shallow call stack to a deeper one. To prevent this fill | ||
74 | - * the entire RSB, even when using IBRS. | ||
75 | + * If spectre v2 protection has been enabled, unconditionally fill | ||
76 | + * RSB during a context switch; this protects against two independent | ||
77 | + * issues: | ||
78 | * | ||
79 | - * Skylake era CPUs have a separate issue with *underflow* of the | ||
80 | - * RSB, when they will predict 'ret' targets from the generic BTB. | ||
81 | - * The proper mitigation for this is IBRS. If IBRS is not supported | ||
82 | - * or deactivated in favour of retpolines the RSB fill on context | ||
83 | - * switch is required. | ||
84 | + * - RSB underflow (and switch to BTB) on Skylake+ | ||
85 | + * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | ||
86 | */ | ||
87 | - if ((!boot_cpu_has(X86_FEATURE_PTI) && | ||
88 | - !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | ||
89 | - setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | ||
90 | - pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); | ||
91 | - } | ||
92 | + setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | ||
93 | + pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | ||
94 | |||
95 | /* Initialize Indirect Branch Prediction Barrier if supported */ | ||
96 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | ||
97 | -- | ||
98 | 1.9.1 | ||
99 | |||