/dts-v1/;

/ {
	#size-cells = <0x2>;
	#address-cells = <0x2>;
	interrupt-parent = <0x1>;
	compatible = "apm,mustang", "apm,xgene-storm";
	model = "HP ProLiant m400 Server Cartridge";
	copyright = "Hewlett-Packard Development Company, L.P.";
	serial-number = "CN7416V02J";

	memory {
		reg = <0x40 0x0 0x8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
		device_type = "memory";
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 ro";
		linux,initrd-start = <0x47 0xeef28000>;
		linux,initrd-end = <0x47 0xeffffaf6>;
	};

	soc {
		ranges;
		#size-cells = <0x2>;
		#address-cells = <0x2>;
		compatible = "simple-bus";

		crypto@1f250000 {
			interrupts = <0x0 0x85 0x4>;
			slave_info = <0x1 0x0 0x2 0x20 0x8>;
			slave_name = "SEC";
			clocks = <0x10 0x0>;
			#clock-cells = <0x1>;
			reg = <0x0 0x1f250000 0x0 0x10000>;
			compatible = "apm,xgene-crypto";
			device_type = "crypto";
		};

		gpio_keys_polled {
			autorepeat;
			poll-interval = <0x64>;
			#size-cells = <0x0>;
			#address-cells = <0x1>;
			compatible = "gpio-keys-polled";

			button@1 {
				gpios = <0x18 0x17 0x1>;
				linux,input-type = <0x1>;
				linux,code = <0x74>;
				label = "Power button";
			};
		};

		gpio_poweroff {
			gpios = <0x18 0x18 0x0>;
			compatible = "gpio-poweroff";
		};

		dwgpio@1c024000 {
			reg-io-width = <0x4>;
			#size-cells = <0x0>;
			#address-cells = <0x1>;
			reg = <0x0 0x1c024000 0x0 0x1000>;
			compatible = "snps,dw-apb-gpio";

			gpio-controller@0 {
				phandle = <0x18>;
				linux,phandle = <0x18>;
				reg = <0x0>;
				snps,nr-gpios = <0x20>;
				#gpio-cells = <0x2>;
				gpio-controller;
				compatible = "snps,dw-apb-gpio-port";
			};
		};

		ethernet@17020000 {
			phy-mode = "rgmii";
			phyid = <0x3>;
			max-frame-size = <0x233a>;
			local-mac-address = <0x0 0x11 0x3a 0x8a 0x5a 0x78>;
			clocks = <0x17 0x0>;
			#clock-cells = <0x1>;
			interrupts = <0x0 0x38 0x4 0x0 0x39 0x4 0x0 0x3a 0x4>;
			slave-name = "RGMII";
			reg = <0x0 0x17020000 0x0 0x30 0x0 0x17020000 0x0 0x10000 0x0 0x17020000 0x0 0x20>;
			status = "na";
			compatible = "apm,xgene-enet";
		};

		qmtm@17030000 {
			clocks = <0x16 0x0>;
			#clock-cells = <0x1>;
			status = "ok";
			interrupts = <0x0 0x40 0x4 0x0 0x3c 0x4>;
			slave-name = "CPU_QMTM3";
			reg = <0x0 0x17030000 0x0 0x10000 0x0 0x10000000 0x0 0x400000>;
			compatible = "apm,xgene-qmtm-lite";
		};

		sata@1a800000 {
			phy-names = "sata-phy";
			phys = <0x15 0x0>;
			clocks = <0x14 0x0>;
			status = "ok";
			interrupts = <0x0 0x88 0x4>;
			reg = <0x0 0x1a800000 0x0 0x1000 0x0 0x1f230000 0x0 0x1000 0x0 0x1f23d000 0x0 0x1000 0x0 0x1f23e000 0x0 0x1000 0x0 0x1c000200 0x0 0x100>;
			compatible = "apm,xgene-ahci";
		};

		sata@1a400000 {
			phy-names = "sata-phy";
			phys = <0x13 0x0>;
			clocks = <0x12 0x0>;
			status = "disabled";
			interrupts = <0x0 0x87 0x4>;
			reg = <0x0 0x1a400000 0x0 0x1000 0x0 0x1f220000 0x0 0x1000 0x0 0x1f22d000 0x0 0x1000 0x0 0x1f22e000 0x0 0x1000 0x0 0x1c000200 0x0 0x100 0x0 0x1f227000 0x0 0x1000>;
			compatible = "apm,xgene-ahci";
		};

		sata@1a000000 {
			phy-names = "sata-phy";
			phys = <0x11 0x0>;
			clocks = <0x10 0x0>;
			status = "disabled";
			interrupts = <0x0 0x86 0x4>;
			reg = <0x0 0x1a000000 0x0 0x1000 0x0 0x1f210000 0x0 0x1000 0x0 0x1f21d000 0x0 0x1000 0x0 0x1f21e000 0x0 0x1000 0x0 0x1f217000 0x0 0x1000>;
			compatible = "apm,xgene-ahci";
		};

		phy@1f23a000 {
			phandle = <0x15>;
			linux,phandle = <0x15>;
			apm,tx-amplitude-A3 = <0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0>;
			apm,tx-post-cursor-A3 = <0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0>;
			apm,tx-pre-cursor2-A3 = <0x0 0x0 0x0 0x0 0x0 0x0>;
			apm,tx-pre-cursor1-A3 = <0x8e30 0x8e30 0x8e30 0x8e30 0x8e30 0x8e30>;
			apm,tx-equalizer-A3 = <0x1 0x1 0x1 0x1 0x1 0x1>;
			apm,tx-eye-tuning-A3 = <0x1 0xa 0xa 0x2 0xa 0xa>;
			apm,tx-boost-gain-A3 = <0x1e 0x1e 0x1e 0x1e 0x1e 0x1e>;
			apm,tx-boost-gain-ssd-A3 = <0x2 0x2 0x2 0x2 0x2 0x2>;
			status = "ok";
			clocks = <0xf 0x0>;
			#phy-cells = <0x1>;
			reg = <0x0 0x1f23a000 0x0 0x100>;
			compatible = "apm,xgene-phy";
		};

		phy@1f22a000 {
			phandle = <0x13>;
			linux,phandle = <0x13>;
			apm,tx-amplitude-A3 = <0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0>;
			apm,tx-post-cursor-A3 = <0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0>;
			apm,tx-pre-cursor2-A3 = <0x0 0x0 0x0 0x0 0x0 0x0>;
			apm,tx-pre-cursor1-A3 = <0x8e30 0x8e30 0x8e30 0x8e30 0x8e30 0x8e30>;
			apm,tx-equalizer-A3 = <0x1 0x1 0x1 0x1 0x1 0x1>;
			apm,tx-eye-tuning-A3 = <0x1 0xa 0xa 0x2 0xa 0xa>;
			apm,tx-boost-gain-A3 = <0x1e 0x1e 0x1e 0x1e 0x1e 0x1e>;
			apm,tx-boost-gain-ssd-A3 = <0x2 0x2 0x2 0x2 0x2 0x2>;
			status = "disabled";
			clocks = <0xe 0x0>;
			#phy-cells = <0x1>;
			reg = <0x0 0x1f22a000 0x0 0x100>;
			compatible = "apm,xgene-phy";
		};

		phy@1f21a000 {
			phandle = <0x11>;
			linux,phandle = <0x11>;
			apm,tx-amplitude-A3 = <0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0>;
			apm,tx-post-cursor-A3 = <0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0>;
			apm,tx-pre-cursor2-A3 = <0x0 0x0 0x0 0x0 0x0 0x0>;
			apm,tx-pre-cursor1-A3 = <0x8e30 0x8e30 0x8e30 0x8e30 0x8e30 0x8e30>;
			apm,tx-equalizer-A3 = <0x1 0x1 0x1 0x1 0x1 0x1>;
			apm,tx-eye-tuning-A3 = <0xa 0xa 0xa 0xa 0xa 0xa>;
			apm,tx-boost-gain-A3 = <0x1e 0x1e 0x1e 0x1e 0x1e 0x1e>;
			apm,tx-boost-gain-ssd-A3 = <0x2 0x2 0x2 0x2 0x2 0x2>;
			status = "disabled";
			clocks = <0xd 0x0>;
			#phy-cells = <0x1>;
			reg = <0x0 0x1f21a000 0x0 0x100>;
			compatible = "apm,xgene-phy";
		};

		reboot@17000014 {
			mask = <0x1>;
			offset = <0x14>;
			regmap = <0xc>;
			compatible = "syscon-reboot";
		};

		slimpro@10540000 {
			interrupts = <0x0 0x0 0x4 0x0 0x1 0x4 0x0 0x2 0x4 0x0 0x3 0x4 0x0 0x4 0x4 0x0 0x5 0x4 0x0 0x6 0x4 0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4>;
			reg = <0x0 0x10540000 0x0 0xa000>;
			compatible = "apm,xgene-slimpro-mbox";
		};

		serial@1c021000 {
			status = "ok";
			interrupts = <0x0 0x4d 0x4>;
			interrupt-parent = <0x1>;
			clock-frequency = <0x2faf080>;
			reg-shift = <0x2>;
			reg = <0x0 0x1c021000 0x0 0x1000>;
			hw-flow-control;
			auto-flow-control;
			fifo-size = <0x10>;
			compatible = "snps,dw-apb-uart", "ns16550a";
			device_type = "serial";
		};

		serial@1c020000 {
			status = "disabled";
			interrupts = <0x0 0x4c 0x4>;
			interrupt-parent = <0x1>;
			clock-frequency = <0x2faf080>;
			reg-shift = <0x2>;
			reg = <0x0 0x1c020000 0x0 0x1000>;
			auto-flow-control;
			fifo-size = <0x10>;
			compatible = "snps,dw-apb-uart", "ns16550a";
			device_type = "serial";
		};

		rtc@10510000 {
			clocks = <0xb 0x0>;
			#clock-cells = <0x1>;
			interrupts = <0x0 0x46 0x4>;
			reg = <0x0 0x10510000 0x0 0x400>;
			compatible = "apm,xgene-rtc";
			device_type = "rtc";
		};

		pcie@1f510000 {
			clocks = <0xa 0x0>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xda 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xdb 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xdc 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xdd 0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupts = <0x0 0x10 0x4>;
			ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
			ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			ranges = <0x1000000 0x0 0x0 0xc0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xc0 0x10000000 0x0 0x80000000>;
			reg-names = "csr", "cfg";
			reg = <0x0 0x1f510000 0x0 0x10000 0xc0 0xd0000000 0x0 0x200000>;
			serdes-diff-clk = <0x0>;
			link_speed = <0x2>;
			link_width = <0x4>;
			port = <0x4>;
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			#interrupt-cells = <0x1>;
			compatible = "apm,xgene-pcie";
			device_type = "pci";
			status = "na";
		};

		pcie@1f500000 {
			clocks = <0x9 0x0>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xd4 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xd5 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xd6 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xd7 0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupts = <0x0 0x10 0x4>;
			ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
			ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			ranges = <0x1000000 0x0 0x0 0xa0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xa0 0x10000000 0x0 0x80000000>;
			reg-names = "csr", "cfg";
			reg = <0x0 0x1f500000 0x0 0x10000 0xa0 0xd0000000 0x0 0x200000>;
			serdes-diff-clk = <0x0>;
			link_speed = <0x2>;
			link_width = <0x8>;
			port = <0x3>;
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			#interrupt-cells = <0x1>;
			compatible = "apm,xgene-pcie";
			device_type = "pci";
			status = "ok";
			reset_gpio = <0xffffffff>;
		};

		pcie@1f2d0000 {
			clocks = <0x8 0x0>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xce 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xcf 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xd0 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xd1 0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupts = <0x0 0x10 0x4>;
			ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
			ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			ranges = <0x1000000 0x0 0x0 0x90 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0x90 0x10000000 0x0 0x80000000>;
			reg-names = "csr", "cfg";
			reg = <0x0 0x1f2d0000 0x0 0x10000 0x90 0xd0000000 0x0 0x200000>;
			serdes-diff-clk = <0x0>;
			link_speed = <0x2>;
			link_width = <0x1>;
			port = <0x2>;
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			#interrupt-cells = <0x1>;
			compatible = "apm,xgene-pcie";
			device_type = "pci";
			status = "na";
		};

		pcie@1f2c0000 {
			clocks = <0x7 0x0>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xc8 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xc9 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xca 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xcb 0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupts = <0x0 0x10 0x4>;
			ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
			ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			ranges = <0x1000000 0x0 0x0 0xd0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xd0 0x10000000 0x0 0x80000000>;
			reg-names = "csr", "cfg";
			reg = <0x0 0x1f2c0000 0x0 0x10000 0xd0 0xd0000000 0x0 0x200000>;
			serdes-diff-clk = <0x0>;
			link_speed = <0x3>;
			link_width = <0x4>;
			port = <0x1>;
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			#interrupt-cells = <0x1>;
			compatible = "apm,xgene-pcie";
			device_type = "pci";
			status = "na";
		};

		pcie@1f2b0000 {
			clocks = <0x6 0x0>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xc2 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xc3 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xc4 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xc5 0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupts = <0x0 0x10 0x4>;
			ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
			ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
			ranges = <0x1000000 0x0 0x0 0xe0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xe0 0x10000000 0x0 0x80000000>;
			reg-names = "csr", "cfg";
			reg = <0x0 0x1f2b0000 0x0 0x10000 0xe0 0xd0000000 0x0 0x200000>;
			serdes-diff-clk = <0x0>;
			link_speed = <0x3>;
			link_width = <0x4>;
			reset_gpio = <0x19>;
			port = <0x0>;
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			#interrupt-cells = <0x1>;
			compatible = "apm,xgene-pcie";
			device_type = "pci";
			status = "na";
		};

		msi@79000000 {
			interrupts = <0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x12 0x4 0x0 0x13 0x4 0x0 0x14 0x4 0x0 0x15 0x4 0x0 0x16 0x4 0x0 0x17 0x4 0x0 0x18 0x4 0x0 0x19 0x4 0x0 0x1a 0x4 0x0 0x1b 0x4 0x0 0x1c 0x4 0x0 0x1d 0x4 0x0 0x1e 0x4 0x0 0x1f 0x4>;
			msi-available-ranges = <0x0 0x1000>;
			reg = <0x0 0x79000000 0x0 0x900000>;
			compatible = "xgene,gic-msi";
		};

		clocks {
			ranges;
			#size-cells = <0x2>;
			#address-cells = <0x2>;

			gpioclk@1f2ac000 {
				phandle = <0x27>;
				linux,phandle = <0x27>;
				clock-output-names = "gpioclk";
				enable-mask = <0x4>;
				enable-offset = <0x8>;
				csr-mask = <0x4>;
				csr-offset = <0x0>;
				reg-names = "csr-reg";
				reg = <0x0 0x1f2ac000 0x0 0x1000>;
				clock-names = "ahbclk";
				clocks = <0x6 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			pcie4clk@1f51c000 {
				phandle = <0xa>;
				linux,phandle = <0xa>;
				clock-output-names = "pcie4clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f51c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
				status = "disabled";
			};

			pcie3clk@1f50c000 {
				phandle = <0x9>;
				linux,phandle = <0x9>;
				clock-output-names = "pcie3clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f50c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
				status = "ok";
			};

			pcie2clk@1f2dc000 {
				phandle = <0x8>;
				linux,phandle = <0x8>;
				clock-output-names = "pcie2clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f2dc000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
				status = "disabled";
			};

			pcie1clk@1f2cc000 {
				phandle = <0x7>;
				linux,phandle = <0x7>;
				clock-output-names = "pcie1clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f2cc000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
				status = "ok";
			};

			pcie0clk@1f2bc000 {
				phandle = <0x6>;
				linux,phandle = <0x6>;
				clock-output-names = "pcie0clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f2bc000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
				status = "ok";
			};

			rtcclk@17000000 {
				phandle = <0xb>;
				linux,phandle = <0xb>;
				clock-output-names = "rtcclk";
				enable-mask = <0x2>;
				enable-offset = <0x10>;
				csr-mask = <0x2>;
				csr-offset = <0xc>;
				reg-names = "csr-reg";
				reg = <0x0 0x17000000 0x0 0x2000>;
				clock-names = "socplldiv2";
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			sata45clk@1f23c000 {
				phandle = <0x14>;
				linux,phandle = <0x14>;
				enable-mask = <0x39>;
				enable-offset = <0x0>;
				csr-mask = <0x5>;
				csr-offset = <0x4>;
				clock-output-names = "sata45clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			sata23clk@1f22c000 {
				phandle = <0x12>;
				linux,phandle = <0x12>;
				enable-mask = <0x39>;
				enable-offset = <0x0>;
				csr-mask = <0x5>;
				csr-offset = <0x4>;
				clock-output-names = "sata23clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			sata01clk@1f21c000 {
				phandle = <0x10>;
				linux,phandle = <0x10>;
				enable-mask = <0x39>;
				enable-offset = <0x0>;
				csr-mask = <0x5>;
				csr-offset = <0x4>;
				clock-output-names = "sata01clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			sataphy1clk@1f23c000 {
				phandle = <0xf>;
				linux,phandle = <0xf>;
				enable-mask = <0x6>;
				enable-offset = <0x0>;
				csr-mask = <0x3a>;
				csr-offset = <0x4>;
				status = "ok";
				clock-output-names = "sataphy3clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			sataphy1clk@1f22c000 {
				phandle = <0xe>;
				linux,phandle = <0xe>;
				enable-mask = <0x6>;
				enable-offset = <0x0>;
				csr-mask = <0x3a>;
				csr-offset = <0x4>;
				status = "ok";
				clock-output-names = "sataphy2clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			sataphy1clk@1f21c000 {
				phandle = <0xd>;
				linux,phandle = <0xd>;
				enable-mask = <0x6>;
				enable-offset = <0x0>;
				csr-mask = <0x0>;
				csr-offset = <0x4>;
				status = "disabled";
				clock-output-names = "sataphy1clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			eth8clk {
				phandle = <0x17>;
				linux,phandle = <0x17>;
				clock-output-names = "eth8clk";
				reg-names = "csr-reg";
				reg = <0x0 0x1702c000 0x0 0x1000>;
				clock-names = "eth8clk";
				clocks = <0x5 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			ethclk {
				phandle = <0x5>;
				linux,phandle = <0x5>;
				clock-output-names = "ethclk";
				divider-shift = <0x0>;
				divider-width = <0x9>;
				divider-offset = <0x238>;
				reg-names = "div-reg";
				reg = <0x0 0x17000000 0x0 0x1000>;
				clock-names = "ethclk";
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			qmlclk {
				phandle = <0x16>;
				linux,phandle = <0x16>;
				enable-mask = <0x3>;
				enable-offset = <0x8>;
				csr-mask = <0x3>;
				csr-offset = <0x0>;
				status = "ok";
				clock-output-names = "qmlclk";
				reg-names = "csr-reg";
				reg = <0x0 0x1703c000 0x0 0x1000>;
				clock-names = "socplldiv2";
				clocks = <0x4 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-device-clock";
			};

			socplldiv2 {
				phandle = <0x4>;
				linux,phandle = <0x4>;
				clock-output-names = "socpll";
				clock-div = <0x2>;
				clock-mult = <0x1>;
				clock-names = "socplldiv2";
				clocks = <0x3 0x0>;
				#clock-cells = <0x1>;
				compatible = "fixed-factor-clock";
			};

			socpll@17000120 {
				phandle = <0x3>;
				linux,phandle = <0x3>;
				type = <0x1>;
				clock-output-names = "socpll";
				reg = <0x0 0x17000120 0x0 0x1000>;
				clock-names = "refclk";
				clocks = <0x2 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-socpll-clock";
			};

			pcppll@17000100 {
				type = <0x0>;
				clock-output-names = "pcppll";
				reg = <0x0 0x17000100 0x0 0x1000>;
				clock-names = "refclk";
				clocks = <0x2 0x0>;
				#clock-cells = <0x1>;
				compatible = "apm,xgene-pcppll-clock";
			};

			refclk {
				phandle = <0x2>;
				linux,phandle = <0x2>;
				clock-output-names = "refclk";
				clock-frequency = <0x5f5e100>;
				#clock-cells = <0x1>;
				compatible = "fixed-clock";
			};
		};

		system-clk-controller@17000000 {
			phandle = <0xc>;
			linux,phandle = <0xc>;
			reg = <0x0 0x17000000 0x0 0x400>;
			compatible = "apm,xgene-scu", "syscon";
		};
	};

	timer {
		clock-frequency = <0x2faf080>;
		interrupts = <0x1 0x0 0xff04 0x1 0xd 0xff04 0x1 0xe 0xff04 0x1 0xf 0xff04>;
		compatible = "arm,armv8-timer";
	};

	pmu {
		interrupts = <0x1 0xc 0xff04>;
		compatible = "arm,armv8-pmuv3";
	};

	interrupt-controller@78010000 {
		phandle = <0x1>;
		linux,phandle = <0x1>;
		interrupts = <0x1 0x9 0xf04>;
		reg = <0x0 0x78010000 0x0 0x1000 0x0 0x78020000 0x0 0x1000 0x0 0x78040000 0x0 0x2000 0x0 0x78060000 0x0 0x2000>;
		interrupt-controller;
		#interrupt-cells = <0x3>;
		compatible = "arm,cortex-a15-gic";
	};

	cpus {
		#size-cells = <0x0>;
		#address-cells = <0x2>;

		cpu@301 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x301>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};

		cpu@300 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x300>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};

		cpu@201 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x201>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};

		cpu@200 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x200>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};

		cpu@101 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x101>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};

		cpu@100 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x100>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};

		cpu@001 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x1>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};

		cpu@000 {
			cpu-release-addr = <0x40 0xfff8>;
			enable-method = "spin-table";
			reg = <0x0 0x0>;
			compatible = "apm,potenza", "arm,armv8";
			device_type = "cpu";
		};
	};

	rom {

		boot-rom {
			BootROM-version = "U02";
		};
	};

	sl1500 {
		compatible = "hp,moonshot";

		node {
			device_type = "hp,sl1500-node";
			id = [31 00];
			serial-number = "CN7416V02J";
			uuid = "C69C5311-CB25-594A-9D73-56064A71BF4C";
			boot-time = "2014-11-13T06:03:45";
			boot-adjust = "47";
		};

		cartridge {
			device_type = "hp,sl1500-cartridge";
			id = "37";
			serial-number = "CN7416V02J";
			product-name = "ProLiant m400 Server Cartridge";
			product-id = "721717-B21";
			asset-tag = [00];
			cpld = "04";
			rom-sysid = "U02";
			rom-date = "07/14/2014";
		};

		chassis {
			device_type = "hp,sl1500-chassis";
			serial-number = "MX241200GX";
			asset-tag = [00];
			timezone-gmtoff = [30 00];
			timezone = "Europe/London";
			timezone-data = "GMT-0:00BST-01:00:00,M3.5.0/01:00:00,M10.5.0/01:00:00";
		};
	};
};