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1/*
2 * Cavium Thunder DTS file - Thunder SoC description
3 *
4 * Copyright (C) 2014-2016, Cavium Inc.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/ {
51 model = "Cavium ThunderX CN88XX board";
52 compatible = "cavium,thunder-88xx";
53 interrupt-parent = <&gic0>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 cpus {
63 #address-cells = <2>;
64 #size-cells = <0>;
65
66 cpu-map {
67 cluster0 {
68 core0 {
69 cpu = <&CPU0>;
70 };
71 core1 {
72 cpu = <&CPU1>;
73 };
74 core2 {
75 cpu = <&CPU2>;
76 };
77 core3 {
78 cpu = <&CPU3>;
79 };
80 core4 {
81 cpu = <&CPU4>;
82 };
83 core5 {
84 cpu = <&CPU5>;
85 };
86 core6 {
87 cpu = <&CPU6>;
88 };
89 core7 {
90 cpu = <&CPU7>;
91 };
92 core8 {
93 cpu = <&CPU8>;
94 };
95 core9 {
96 cpu = <&CPU9>;
97 };
98 core10 {
99 cpu = <&CPU10>;
100 };
101 core11 {
102 cpu = <&CPU11>;
103 };
104 core12 {
105 cpu = <&CPU12>;
106 };
107 core13 {
108 cpu = <&CPU13>;
109 };
110 core14 {
111 cpu = <&CPU14>;
112 };
113 core15 {
114 cpu = <&CPU15>;
115 };
116 core16 {
117 cpu = <&CPU16>;
118 };
119 core17 {
120 cpu = <&CPU17>;
121 };
122 core18 {
123 cpu = <&CPU18>;
124 };
125 core19 {
126 cpu = <&CPU19>;
127 };
128 core20 {
129 cpu = <&CPU20>;
130 };
131 core21 {
132 cpu = <&CPU21>;
133 };
134 core22 {
135 cpu = <&CPU22>;
136 };
137 core23 {
138 cpu = <&CPU23>;
139 };
140 core24 {
141 cpu = <&CPU24>;
142 };
143 core25 {
144 cpu = <&CPU25>;
145 };
146 core26 {
147 cpu = <&CPU26>;
148 };
149 core27 {
150 cpu = <&CPU27>;
151 };
152 core28 {
153 cpu = <&CPU28>;
154 };
155 core29 {
156 cpu = <&CPU29>;
157 };
158 core30 {
159 cpu = <&CPU30>;
160 };
161 core31 {
162 cpu = <&CPU31>;
163 };
164 core32 {
165 cpu = <&CPU32>;
166 };
167 core33 {
168 cpu = <&CPU33>;
169 };
170 core34 {
171 cpu = <&CPU34>;
172 };
173 core35 {
174 cpu = <&CPU35>;
175 };
176 core36 {
177 cpu = <&CPU36>;
178 };
179 core37 {
180 cpu = <&CPU37>;
181 };
182 core38 {
183 cpu = <&CPU38>;
184 };
185 core39 {
186 cpu = <&CPU39>;
187 };
188 core40 {
189 cpu = <&CPU40>;
190 };
191 core41 {
192 cpu = <&CPU41>;
193 };
194 core42 {
195 cpu = <&CPU42>;
196 };
197 core43 {
198 cpu = <&CPU43>;
199 };
200 core44 {
201 cpu = <&CPU44>;
202 };
203 core45 {
204 cpu = <&CPU45>;
205 };
206 core46 {
207 cpu = <&CPU46>;
208 };
209 core47 {
210 cpu = <&CPU47>;
211 };
212 };
213
214 cluster1 {
215 core0 {
216 cpu = <&CPU48>;
217 };
218 core1 {
219 cpu = <&CPU49>;
220 };
221 core2 {
222 cpu = <&CPU50>;
223 };
224 core3 {
225 cpu = <&CPU51>;
226 };
227 core4 {
228 cpu = <&CPU52>;
229 };
230 core5 {
231 cpu = <&CPU53>;
232 };
233 core6 {
234 cpu = <&CPU54>;
235 };
236 core7 {
237 cpu = <&CPU55>;
238 };
239 core8 {
240 cpu = <&CPU56>;
241 };
242 core9 {
243 cpu = <&CPU57>;
244 };
245 core10 {
246 cpu = <&CPU58>;
247 };
248 core11 {
249 cpu = <&CPU59>;
250 };
251 core12 {
252 cpu = <&CPU60>;
253 };
254 core13 {
255 cpu = <&CPU61>;
256 };
257 core14 {
258 cpu = <&CPU62>;
259 };
260 core15 {
261 cpu = <&CPU63>;
262 };
263 core16 {
264 cpu = <&CPU64>;
265 };
266 core17 {
267 cpu = <&CPU65>;
268 };
269 core18 {
270 cpu = <&CPU66>;
271 };
272 core19 {
273 cpu = <&CPU67>;
274 };
275 core20 {
276 cpu = <&CPU68>;
277 };
278 core21 {
279 cpu = <&CPU69>;
280 };
281 core22 {
282 cpu = <&CPU70>;
283 };
284 core23 {
285 cpu = <&CPU71>;
286 };
287 core24 {
288 cpu = <&CPU72>;
289 };
290 core25 {
291 cpu = <&CPU73>;
292 };
293 core26 {
294 cpu = <&CPU74>;
295 };
296 core27 {
297 cpu = <&CPU75>;
298 };
299 core28 {
300 cpu = <&CPU76>;
301 };
302 core29 {
303 cpu = <&CPU77>;
304 };
305 core30 {
306 cpu = <&CPU78>;
307 };
308 core31 {
309 cpu = <&CPU79>;
310 };
311 core32 {
312 cpu = <&CPU80>;
313 };
314 core33 {
315 cpu = <&CPU81>;
316 };
317 core34 {
318 cpu = <&CPU82>;
319 };
320 core35 {
321 cpu = <&CPU83>;
322 };
323 core36 {
324 cpu = <&CPU84>;
325 };
326 core37 {
327 cpu = <&CPU85>;
328 };
329 core38 {
330 cpu = <&CPU86>;
331 };
332 core39 {
333 cpu = <&CPU87>;
334 };
335 core40 {
336 cpu = <&CPU88>;
337 };
338 core41 {
339 cpu = <&CPU89>;
340 };
341 core42 {
342 cpu = <&CPU90>;
343 };
344 core43 {
345 cpu = <&CPU91>;
346 };
347 core44 {
348 cpu = <&CPU92>;
349 };
350 core45 {
351 cpu = <&CPU93>;
352 };
353 core46 {
354 cpu = <&CPU94>;
355 };
356 core47 {
357 cpu = <&CPU95>;
358 };
359 };
360 };
361
362 CPU0: cpu@0 {
363 device_type = "cpu";
364 compatible = "cavium,thunder", "arm,armv8";
365 reg = <0x0 0x000>;
366 enable-method = "psci";
367 /* socket 0 */
368 numa-node-id = <0>;
369 next-level-cache = <&thunderx_L2_0>;
370 };
371 CPU1: cpu@1 {
372 device_type = "cpu";
373 compatible = "cavium,thunder", "arm,armv8";
374 reg = <0x0 0x001>;
375 enable-method = "psci";
376 numa-node-id = <0>;
377 next-level-cache = <&thunderx_L2_0>;
378 };
379 CPU2: cpu@2 {
380 device_type = "cpu";
381 compatible = "cavium,thunder", "arm,armv8";
382 reg = <0x0 0x002>;
383 enable-method = "psci";
384 numa-node-id = <0>;
385 next-level-cache = <&thunderx_L2_0>;
386 };
387 CPU3: cpu@3 {
388 device_type = "cpu";
389 compatible = "cavium,thunder", "arm,armv8";
390 reg = <0x0 0x003>;
391 enable-method = "psci";
392 numa-node-id = <0>;
393 next-level-cache = <&thunderx_L2_0>;
394 };
395 CPU4: cpu@4 {
396 device_type = "cpu";
397 compatible = "cavium,thunder", "arm,armv8";
398 reg = <0x0 0x004>;
399 enable-method = "psci";
400 numa-node-id = <0>;
401 next-level-cache = <&thunderx_L2_0>;
402 };
403 CPU5: cpu@5 {
404 device_type = "cpu";
405 compatible = "cavium,thunder", "arm,armv8";
406 reg = <0x0 0x005>;
407 enable-method = "psci";
408 numa-node-id = <0>;
409 next-level-cache = <&thunderx_L2_0>;
410 };
411 CPU6: cpu@6 {
412 device_type = "cpu";
413 compatible = "cavium,thunder", "arm,armv8";
414 reg = <0x0 0x006>;
415 enable-method = "psci";
416 numa-node-id = <0>;
417 next-level-cache = <&thunderx_L2_0>;
418 };
419 CPU7: cpu@7 {
420 device_type = "cpu";
421 compatible = "cavium,thunder", "arm,armv8";
422 reg = <0x0 0x007>;
423 enable-method = "psci";
424 numa-node-id = <0>;
425 next-level-cache = <&thunderx_L2_0>;
426 };
427 CPU8: cpu@8 {
428 device_type = "cpu";
429 compatible = "cavium,thunder", "arm,armv8";
430 reg = <0x0 0x008>;
431 enable-method = "psci";
432 numa-node-id = <0>;
433 next-level-cache = <&thunderx_L2_0>;
434 };
435 CPU9: cpu@9 {
436 device_type = "cpu";
437 compatible = "cavium,thunder", "arm,armv8";
438 reg = <0x0 0x009>;
439 enable-method = "psci";
440 numa-node-id = <0>;
441 next-level-cache = <&thunderx_L2_0>;
442 };
443 CPU10: cpu@a {
444 device_type = "cpu";
445 compatible = "cavium,thunder", "arm,armv8";
446 reg = <0x0 0x00a>;
447 enable-method = "psci";
448 numa-node-id = <0>;
449 next-level-cache = <&thunderx_L2_0>;
450 };
451 CPU11: cpu@b {
452 device_type = "cpu";
453 compatible = "cavium,thunder", "arm,armv8";
454 reg = <0x0 0x00b>;
455 enable-method = "psci";
456 numa-node-id = <0>;
457 next-level-cache = <&thunderx_L2_0>;
458 };
459 CPU12: cpu@c {
460 device_type = "cpu";
461 compatible = "cavium,thunder", "arm,armv8";
462 reg = <0x0 0x00c>;
463 enable-method = "psci";
464 numa-node-id = <0>;
465 next-level-cache = <&thunderx_L2_0>;
466 };
467 CPU13: cpu@d {
468 device_type = "cpu";
469 compatible = "cavium,thunder", "arm,armv8";
470 reg = <0x0 0x00d>;
471 enable-method = "psci";
472 numa-node-id = <0>;
473 next-level-cache = <&thunderx_L2_0>;
474 };
475 CPU14: cpu@e {
476 device_type = "cpu";
477 compatible = "cavium,thunder", "arm,armv8";
478 reg = <0x0 0x00e>;
479 enable-method = "psci";
480 numa-node-id = <0>;
481 next-level-cache = <&thunderx_L2_0>;
482 };
483 CPU15: cpu@f {
484 device_type = "cpu";
485 compatible = "cavium,thunder", "arm,armv8";
486 reg = <0x0 0x00f>;
487 enable-method = "psci";
488 numa-node-id = <0>;
489 next-level-cache = <&thunderx_L2_0>;
490 };
491 CPU16: cpu@100 {
492 device_type = "cpu";
493 compatible = "cavium,thunder", "arm,armv8";
494 reg = <0x0 0x100>;
495 enable-method = "psci";
496 numa-node-id = <0>;
497 next-level-cache = <&thunderx_L2_0>;
498 };
499 CPU17: cpu@101 {
500 device_type = "cpu";
501 compatible = "cavium,thunder", "arm,armv8";
502 reg = <0x0 0x101>;
503 enable-method = "psci";
504 numa-node-id = <0>;
505 next-level-cache = <&thunderx_L2_0>;
506 };
507 CPU18: cpu@102 {
508 device_type = "cpu";
509 compatible = "cavium,thunder", "arm,armv8";
510 reg = <0x0 0x102>;
511 enable-method = "psci";
512 numa-node-id = <0>;
513 next-level-cache = <&thunderx_L2_0>;
514 };
515 CPU19: cpu@103 {
516 device_type = "cpu";
517 compatible = "cavium,thunder", "arm,armv8";
518 reg = <0x0 0x103>;
519 enable-method = "psci";
520 numa-node-id = <0>;
521 next-level-cache = <&thunderx_L2_0>;
522 };
523 CPU20: cpu@104 {
524 device_type = "cpu";
525 compatible = "cavium,thunder", "arm,armv8";
526 reg = <0x0 0x104>;
527 enable-method = "psci";
528 numa-node-id = <0>;
529 next-level-cache = <&thunderx_L2_0>;
530 };
531 CPU21: cpu@105 {
532 device_type = "cpu";
533 compatible = "cavium,thunder", "arm,armv8";
534 reg = <0x0 0x105>;
535 enable-method = "psci";
536 numa-node-id = <0>;
537 next-level-cache = <&thunderx_L2_0>;
538 };
539 CPU22: cpu@106 {
540 device_type = "cpu";
541 compatible = "cavium,thunder", "arm,armv8";
542 reg = <0x0 0x106>;
543 enable-method = "psci";
544 numa-node-id = <0>;
545 next-level-cache = <&thunderx_L2_0>;
546 };
547 CPU23: cpu@107 {
548 device_type = "cpu";
549 compatible = "cavium,thunder", "arm,armv8";
550 reg = <0x0 0x107>;
551 enable-method = "psci";
552 numa-node-id = <0>;
553 next-level-cache = <&thunderx_L2_0>;
554 };
555 CPU24: cpu@108 {
556 device_type = "cpu";
557 compatible = "cavium,thunder", "arm,armv8";
558 reg = <0x0 0x108>;
559 enable-method = "psci";
560 numa-node-id = <0>;
561 next-level-cache = <&thunderx_L2_0>;
562 };
563 CPU25: cpu@109 {
564 device_type = "cpu";
565 compatible = "cavium,thunder", "arm,armv8";
566 reg = <0x0 0x109>;
567 enable-method = "psci";
568 numa-node-id = <0>;
569 next-level-cache = <&thunderx_L2_0>;
570 };
571 CPU26: cpu@10a {
572 device_type = "cpu";
573 compatible = "cavium,thunder", "arm,armv8";
574 reg = <0x0 0x10a>;
575 enable-method = "psci";
576 numa-node-id = <0>;
577 next-level-cache = <&thunderx_L2_0>;
578 };
579 CPU27: cpu@10b {
580 device_type = "cpu";
581 compatible = "cavium,thunder", "arm,armv8";
582 reg = <0x0 0x10b>;
583 enable-method = "psci";
584 numa-node-id = <0>;
585 next-level-cache = <&thunderx_L2_0>;
586 };
587 CPU28: cpu@10c {
588 device_type = "cpu";
589 compatible = "cavium,thunder", "arm,armv8";
590 reg = <0x0 0x10c>;
591 enable-method = "psci";
592 numa-node-id = <0>;
593 next-level-cache = <&thunderx_L2_0>;
594 };
595 CPU29: cpu@10d {
596 device_type = "cpu";
597 compatible = "cavium,thunder", "arm,armv8";
598 reg = <0x0 0x10d>;
599 enable-method = "psci";
600 numa-node-id = <0>;
601 next-level-cache = <&thunderx_L2_0>;
602 };
603 CPU30: cpu@10e {
604 device_type = "cpu";
605 compatible = "cavium,thunder", "arm,armv8";
606 reg = <0x0 0x10e>;
607 enable-method = "psci";
608 numa-node-id = <0>;
609 next-level-cache = <&thunderx_L2_0>;
610 };
611 CPU31: cpu@10f {
612 device_type = "cpu";
613 compatible = "cavium,thunder", "arm,armv8";
614 reg = <0x0 0x10f>;
615 enable-method = "psci";
616 numa-node-id = <0>;
617 next-level-cache = <&thunderx_L2_0>;
618 };
619 CPU32: cpu@200 {
620 device_type = "cpu";
621 compatible = "cavium,thunder", "arm,armv8";
622 reg = <0x0 0x200>;
623 enable-method = "psci";
624 numa-node-id = <0>;
625 next-level-cache = <&thunderx_L2_0>;
626 };
627 CPU33: cpu@201 {
628 device_type = "cpu";
629 compatible = "cavium,thunder", "arm,armv8";
630 reg = <0x0 0x201>;
631 enable-method = "psci";
632 numa-node-id = <0>;
633 next-level-cache = <&thunderx_L2_0>;
634 };
635 CPU34: cpu@202 {
636 device_type = "cpu";
637 compatible = "cavium,thunder", "arm,armv8";
638 reg = <0x0 0x202>;
639 enable-method = "psci";
640 numa-node-id = <0>;
641 next-level-cache = <&thunderx_L2_0>;
642 };
643 CPU35: cpu@203 {
644 device_type = "cpu";
645 compatible = "cavium,thunder", "arm,armv8";
646 reg = <0x0 0x203>;
647 enable-method = "psci";
648 numa-node-id = <0>;
649 next-level-cache = <&thunderx_L2_0>;
650 };
651 CPU36: cpu@204 {
652 device_type = "cpu";
653 compatible = "cavium,thunder", "arm,armv8";
654 reg = <0x0 0x204>;
655 enable-method = "psci";
656 numa-node-id = <0>;
657 next-level-cache = <&thunderx_L2_0>;
658 };
659 CPU37: cpu@205 {
660 device_type = "cpu";
661 compatible = "cavium,thunder", "arm,armv8";
662 reg = <0x0 0x205>;
663 enable-method = "psci";
664 numa-node-id = <0>;
665 next-level-cache = <&thunderx_L2_0>;
666 };
667 CPU38: cpu@206 {
668 device_type = "cpu";
669 compatible = "cavium,thunder", "arm,armv8";
670 reg = <0x0 0x206>;
671 enable-method = "psci";
672 numa-node-id = <0>;
673 next-level-cache = <&thunderx_L2_0>;
674 };
675 CPU39: cpu@207 {
676 device_type = "cpu";
677 compatible = "cavium,thunder", "arm,armv8";
678 reg = <0x0 0x207>;
679 enable-method = "psci";
680 numa-node-id = <0>;
681 next-level-cache = <&thunderx_L2_0>;
682 };
683 CPU40: cpu@208 {
684 device_type = "cpu";
685 compatible = "cavium,thunder", "arm,armv8";
686 reg = <0x0 0x208>;
687 enable-method = "psci";
688 numa-node-id = <0>;
689 next-level-cache = <&thunderx_L2_0>;
690 };
691 CPU41: cpu@209 {
692 device_type = "cpu";
693 compatible = "cavium,thunder", "arm,armv8";
694 reg = <0x0 0x209>;
695 enable-method = "psci";
696 numa-node-id = <0>;
697 next-level-cache = <&thunderx_L2_0>;
698 };
699 CPU42: cpu@20a {
700 device_type = "cpu";
701 compatible = "cavium,thunder", "arm,armv8";
702 reg = <0x0 0x20a>;
703 enable-method = "psci";
704 numa-node-id = <0>;
705 next-level-cache = <&thunderx_L2_0>;
706 };
707 CPU43: cpu@20b {
708 device_type = "cpu";
709 compatible = "cavium,thunder", "arm,armv8";
710 reg = <0x0 0x20b>;
711 enable-method = "psci";
712 numa-node-id = <0>;
713 next-level-cache = <&thunderx_L2_0>;
714 };
715 CPU44: cpu@20c {
716 device_type = "cpu";
717 compatible = "cavium,thunder", "arm,armv8";
718 reg = <0x0 0x20c>;
719 enable-method = "psci";
720 numa-node-id = <0>;
721 next-level-cache = <&thunderx_L2_0>;
722 };
723 CPU45: cpu@20d {
724 device_type = "cpu";
725 compatible = "cavium,thunder", "arm,armv8";
726 reg = <0x0 0x20d>;
727 enable-method = "psci";
728 numa-node-id = <0>;
729 next-level-cache = <&thunderx_L2_0>;
730 };
731 CPU46: cpu@20e {
732 device_type = "cpu";
733 compatible = "cavium,thunder", "arm,armv8";
734 reg = <0x0 0x20e>;
735 enable-method = "psci";
736 numa-node-id = <0>;
737 next-level-cache = <&thunderx_L2_0>;
738 };
739 CPU47: cpu@20f {
740 device_type = "cpu";
741 compatible = "cavium,thunder", "arm,armv8";
742 reg = <0x0 0x20f>;
743 enable-method = "psci";
744 numa-node-id = <0>;
745 next-level-cache = <&thunderx_L2_0>;
746 };
747 CPU48: cpu@10000 {
748 device_type = "cpu";
749 compatible = "cavium,thunder", "arm,armv8";
750 reg = <0x0 0x10000>;
751 enable-method = "psci";
752 /* socket 1 */
753 numa-node-id = <1>;
754 next-level-cache = <&thunderx_L2_1>;
755 };
756 CPU49: cpu@10001 {
757 device_type = "cpu";
758 compatible = "cavium,thunder", "arm,armv8";
759 reg = <0x0 0x10001>;
760 enable-method = "psci";
761 numa-node-id = <1>;
762 next-level-cache = <&thunderx_L2_1>;
763 };
764 CPU50: cpu@10002 {
765 device_type = "cpu";
766 compatible = "cavium,thunder", "arm,armv8";
767 reg = <0x0 0x10002>;
768 enable-method = "psci";
769 numa-node-id = <1>;
770 next-level-cache = <&thunderx_L2_1>;
771 };
772 CPU51: cpu@10003 {
773 device_type = "cpu";
774 compatible = "cavium,thunder", "arm,armv8";
775 reg = <0x0 0x10003>;
776 enable-method = "psci";
777 numa-node-id = <1>;
778 next-level-cache = <&thunderx_L2_1>;
779 };
780 CPU52: cpu@10004 {
781 device_type = "cpu";
782 compatible = "cavium,thunder", "arm,armv8";
783 reg = <0x0 0x10004>;
784 enable-method = "psci";
785 numa-node-id = <1>;
786 next-level-cache = <&thunderx_L2_1>;
787 };
788 CPU53: cpu@10005 {
789 device_type = "cpu";
790 compatible = "cavium,thunder", "arm,armv8";
791 reg = <0x0 0x10005>;
792 enable-method = "psci";
793 numa-node-id = <1>;
794 next-level-cache = <&thunderx_L2_1>;
795 };
796 CPU54: cpu@10006 {
797 device_type = "cpu";
798 compatible = "cavium,thunder", "arm,armv8";
799 reg = <0x0 0x10006>;
800 enable-method = "psci";
801 numa-node-id = <1>;
802 next-level-cache = <&thunderx_L2_1>;
803 };
804 CPU55: cpu@10007 {
805 device_type = "cpu";
806 compatible = "cavium,thunder", "arm,armv8";
807 reg = <0x0 0x10007>;
808 enable-method = "psci";
809 numa-node-id = <1>;
810 next-level-cache = <&thunderx_L2_1>;
811 };
812 CPU56: cpu@10008 {
813 device_type = "cpu";
814 compatible = "cavium,thunder", "arm,armv8";
815 reg = <0x0 0x10008>;
816 enable-method = "psci";
817 numa-node-id = <1>;
818 next-level-cache = <&thunderx_L2_1>;
819 };
820 CPU57: cpu@10009 {
821 device_type = "cpu";
822 compatible = "cavium,thunder", "arm,armv8";
823 reg = <0x0 0x10009>;
824 enable-method = "psci";
825 numa-node-id = <1>;
826 next-level-cache = <&thunderx_L2_1>;
827 };
828 CPU58: cpu@1000a {
829 device_type = "cpu";
830 compatible = "cavium,thunder", "arm,armv8";
831 reg = <0x0 0x1000a>;
832 enable-method = "psci";
833 numa-node-id = <1>;
834 next-level-cache = <&thunderx_L2_1>;
835 };
836 CPU59: cpu@1000b {
837 device_type = "cpu";
838 compatible = "cavium,thunder", "arm,armv8";
839 reg = <0x0 0x1000b>;
840 enable-method = "psci";
841 numa-node-id = <1>;
842 next-level-cache = <&thunderx_L2_1>;
843 };
844 CPU60: cpu@1000c {
845 device_type = "cpu";
846 compatible = "cavium,thunder", "arm,armv8";
847 reg = <0x0 0x1000c>;
848 enable-method = "psci";
849 numa-node-id = <1>;
850 next-level-cache = <&thunderx_L2_1>;
851 };
852 CPU61: cpu@1000d {
853 device_type = "cpu";
854 compatible = "cavium,thunder", "arm,armv8";
855 reg = <0x0 0x1000d>;
856 enable-method = "psci";
857 numa-node-id = <1>;
858 next-level-cache = <&thunderx_L2_1>;
859 };
860 CPU62: cpu@1000e {
861 device_type = "cpu";
862 compatible = "cavium,thunder", "arm,armv8";
863 reg = <0x0 0x1000e>;
864 enable-method = "psci";
865 numa-node-id = <1>;
866 next-level-cache = <&thunderx_L2_1>;
867 };
868 CPU63: cpu@1000f {
869 device_type = "cpu";
870 compatible = "cavium,thunder", "arm,armv8";
871 reg = <0x0 0x1000f>;
872 enable-method = "psci";
873 numa-node-id = <1>;
874 next-level-cache = <&thunderx_L2_1>;
875 };
876 CPU64: cpu@10100 {
877 device_type = "cpu";
878 compatible = "cavium,thunder", "arm,armv8";
879 reg = <0x0 0x10100>;
880 enable-method = "psci";
881 numa-node-id = <1>;
882 next-level-cache = <&thunderx_L2_1>;
883 };
884 CPU65: cpu@10101 {
885 device_type = "cpu";
886 compatible = "cavium,thunder", "arm,armv8";
887 reg = <0x0 0x10101>;
888 enable-method = "psci";
889 numa-node-id = <1>;
890 next-level-cache = <&thunderx_L2_1>;
891 };
892 CPU66: cpu@10102 {
893 device_type = "cpu";
894 compatible = "cavium,thunder", "arm,armv8";
895 reg = <0x0 0x10102>;
896 enable-method = "psci";
897 numa-node-id = <1>;
898 next-level-cache = <&thunderx_L2_1>;
899 };
900 CPU67: cpu@10103 {
901 device_type = "cpu";
902 compatible = "cavium,thunder", "arm,armv8";
903 reg = <0x0 0x10103>;
904 enable-method = "psci";
905 numa-node-id = <1>;
906 next-level-cache = <&thunderx_L2_1>;
907 };
908 CPU68: cpu@10104 {
909 device_type = "cpu";
910 compatible = "cavium,thunder", "arm,armv8";
911 reg = <0x0 0x10104>;
912 enable-method = "psci";
913 numa-node-id = <1>;
914 next-level-cache = <&thunderx_L2_1>;
915 };
916 CPU69: cpu@10105 {
917 device_type = "cpu";
918 compatible = "cavium,thunder", "arm,armv8";
919 reg = <0x0 0x10105>;
920 enable-method = "psci";
921 numa-node-id = <1>;
922 next-level-cache = <&thunderx_L2_1>;
923 };
924 CPU70: cpu@10106 {
925 device_type = "cpu";
926 compatible = "cavium,thunder", "arm,armv8";
927 reg = <0x0 0x10106>;
928 enable-method = "psci";
929 numa-node-id = <1>;
930 next-level-cache = <&thunderx_L2_1>;
931 };
932 CPU71: cpu@10107 {
933 device_type = "cpu";
934 compatible = "cavium,thunder", "arm,armv8";
935 reg = <0x0 0x10107>;
936 enable-method = "psci";
937 numa-node-id = <1>;
938 next-level-cache = <&thunderx_L2_1>;
939 };
940 CPU72: cpu@10108 {
941 device_type = "cpu";
942 compatible = "cavium,thunder", "arm,armv8";
943 reg = <0x0 0x10108>;
944 enable-method = "psci";
945 numa-node-id = <1>;
946 next-level-cache = <&thunderx_L2_1>;
947 };
948 CPU73: cpu@10109 {
949 device_type = "cpu";
950 compatible = "cavium,thunder", "arm,armv8";
951 reg = <0x0 0x10109>;
952 enable-method = "psci";
953 numa-node-id = <1>;
954 next-level-cache = <&thunderx_L2_1>;
955 };
956 CPU74: cpu@1010a {
957 device_type = "cpu";
958 compatible = "cavium,thunder", "arm,armv8";
959 reg = <0x0 0x1010a>;
960 enable-method = "psci";
961 numa-node-id = <1>;
962 next-level-cache = <&thunderx_L2_1>;
963 };
964 CPU75: cpu@1010b {
965 device_type = "cpu";
966 compatible = "cavium,thunder", "arm,armv8";
967 reg = <0x0 0x1010b>;
968 enable-method = "psci";
969 numa-node-id = <1>;
970 next-level-cache = <&thunderx_L2_1>;
971 };
972 CPU76: cpu@1010c {
973 device_type = "cpu";
974 compatible = "cavium,thunder", "arm,armv8";
975 reg = <0x0 0x1010c>;
976 enable-method = "psci";
977 numa-node-id = <1>;
978 next-level-cache = <&thunderx_L2_1>;
979 };
980 CPU77: cpu@1010d {
981 device_type = "cpu";
982 compatible = "cavium,thunder", "arm,armv8";
983 reg = <0x0 0x1010d>;
984 enable-method = "psci";
985 numa-node-id = <1>;
986 next-level-cache = <&thunderx_L2_1>;
987 };
988 CPU78: cpu@1010e {
989 device_type = "cpu";
990 compatible = "cavium,thunder", "arm,armv8";
991 reg = <0x0 0x1010e>;
992 enable-method = "psci";
993 numa-node-id = <1>;
994 next-level-cache = <&thunderx_L2_1>;
995 };
996 CPU79: cpu@1010f {
997 device_type = "cpu";
998 compatible = "cavium,thunder", "arm,armv8";
999 reg = <0x0 0x1010f>;
1000 enable-method = "psci";
1001 numa-node-id = <1>;
1002 next-level-cache = <&thunderx_L2_1>;
1003 };
1004 CPU80: cpu@10200 {
1005 device_type = "cpu";
1006 compatible = "cavium,thunder", "arm,armv8";
1007 reg = <0x0 0x10200>;
1008 enable-method = "psci";
1009 numa-node-id = <1>;
1010 next-level-cache = <&thunderx_L2_1>;
1011 };
1012 CPU81: cpu@10201 {
1013 device_type = "cpu";
1014 compatible = "cavium,thunder", "arm,armv8";
1015 reg = <0x0 0x10201>;
1016 enable-method = "psci";
1017 numa-node-id = <1>;
1018 next-level-cache = <&thunderx_L2_1>;
1019 };
1020 CPU82: cpu@10202 {
1021 device_type = "cpu";
1022 compatible = "cavium,thunder", "arm,armv8";
1023 reg = <0x0 0x10202>;
1024 enable-method = "psci";
1025 numa-node-id = <1>;
1026 next-level-cache = <&thunderx_L2_1>;
1027 };
1028 CPU83: cpu@10203 {
1029 device_type = "cpu";
1030 compatible = "cavium,thunder", "arm,armv8";
1031 reg = <0x0 0x10203>;
1032 enable-method = "psci";
1033 numa-node-id = <1>;
1034 next-level-cache = <&thunderx_L2_1>;
1035 };
1036 CPU84: cpu@10204 {
1037 device_type = "cpu";
1038 compatible = "cavium,thunder", "arm,armv8";
1039 reg = <0x0 0x10204>;
1040 enable-method = "psci";
1041 numa-node-id = <1>;
1042 next-level-cache = <&thunderx_L2_1>;
1043 };
1044 CPU85: cpu@10205 {
1045 device_type = "cpu";
1046 compatible = "cavium,thunder", "arm,armv8";
1047 reg = <0x0 0x10205>;
1048 enable-method = "psci";
1049 numa-node-id = <1>;
1050 next-level-cache = <&thunderx_L2_1>;
1051 };
1052 CPU86: cpu@10206 {
1053 device_type = "cpu";
1054 compatible = "cavium,thunder", "arm,armv8";
1055 reg = <0x0 0x10206>;
1056 enable-method = "psci";
1057 numa-node-id = <1>;
1058 next-level-cache = <&thunderx_L2_1>;
1059 };
1060 CPU87: cpu@10207 {
1061 device_type = "cpu";
1062 compatible = "cavium,thunder", "arm,armv8";
1063 reg = <0x0 0x10207>;
1064 enable-method = "psci";
1065 numa-node-id = <1>;
1066 next-level-cache = <&thunderx_L2_1>;
1067 };
1068 CPU88: cpu@10208 {
1069 device_type = "cpu";
1070 compatible = "cavium,thunder", "arm,armv8";
1071 reg = <0x0 0x10208>;
1072 enable-method = "psci";
1073 numa-node-id = <1>;
1074 next-level-cache = <&thunderx_L2_1>;
1075 };
1076 CPU89: cpu@10209 {
1077 device_type = "cpu";
1078 compatible = "cavium,thunder", "arm,armv8";
1079 reg = <0x0 0x10209>;
1080 enable-method = "psci";
1081 numa-node-id = <1>;
1082 next-level-cache = <&thunderx_L2_1>;
1083 };
1084 CPU90: cpu@1020a {
1085 device_type = "cpu";
1086 compatible = "cavium,thunder", "arm,armv8";
1087 reg = <0x0 0x1020a>;
1088 enable-method = "psci";
1089 numa-node-id = <1>;
1090 next-level-cache = <&thunderx_L2_1>;
1091 };
1092 CPU91: cpu@1020b {
1093 device_type = "cpu";
1094 compatible = "cavium,thunder", "arm,armv8";
1095 reg = <0x0 0x1020b>;
1096 enable-method = "psci";
1097 numa-node-id = <1>;
1098 next-level-cache = <&thunderx_L2_1>;
1099 };
1100 CPU92: cpu@1020c {
1101 device_type = "cpu";
1102 compatible = "cavium,thunder", "arm,armv8";
1103 reg = <0x0 0x1020c>;
1104 enable-method = "psci";
1105 numa-node-id = <1>;
1106 next-level-cache = <&thunderx_L2_1>;
1107 };
1108 CPU93: cpu@1020d {
1109 device_type = "cpu";
1110 compatible = "cavium,thunder", "arm,armv8";
1111 reg = <0x0 0x1020d>;
1112 enable-method = "psci";
1113 numa-node-id = <1>;
1114 next-level-cache = <&thunderx_L2_1>;
1115 };
1116 CPU94: cpu@1020e {
1117 device_type = "cpu";
1118 compatible = "cavium,thunder", "arm,armv8";
1119 reg = <0x0 0x1020e>;
1120 enable-method = "psci";
1121 numa-node-id = <1>;
1122 next-level-cache = <&thunderx_L2_1>;
1123 };
1124 CPU95: cpu@1020f {
1125 device_type = "cpu";
1126 compatible = "cavium,thunder", "arm,armv8";
1127 reg = <0x0 0x1020f>;
1128 enable-method = "psci";
1129 numa-node-id = <1>;
1130 next-level-cache = <&thunderx_L2_1>;
1131 };
1132 thunderx_L2_0: l2-cache0 {
1133 compatible = "cache";
1134 numa-node-id = <0>;
1135 };
1136 thunderx_L2_1: l2-cache1 {
1137 compatible = "cache";
1138 numa-node-id = <1>;
1139 };
1140 };
1141
1142 timer {
1143 compatible = "arm,armv8-timer";
1144 interrupts = <1 13 4>,
1145 <1 14 4>,
1146 <1 11 4>,
1147 <1 10 4>;
1148 };
1149
1150 pmu {
1151 compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
1152 interrupts = <1 7 4>;
1153 };
1154
1155 gic0: interrupt-controller@801000000000 {
1156 compatible = "arm,gic-v3";
1157 #interrupt-cells = <3>;
1158 #address-cells = <2>;
1159 #size-cells = <2>;
1160 #redistributor-regions = <2>;
1161 ranges;
1162 interrupt-controller;
1163 reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
1164 <0x8010 0x80000000 0x0 0x600000>, /* GICR Node 0 */
1165 <0x9010 0x80000000 0x0 0x600000>; /* GICR Node 1 */
1166 interrupts = <1 9 4>;
1167
1168 its: gic-its@801000020000 {
1169 compatible = "arm,gic-v3-its";
1170 reg = <0x8010 0x20000 0x0 0x200000>;
1171 msi-controller;
1172 numa-node-id = <0>;
1173 };
1174
1175 its1: gic-its@901000020000 {
1176 compatible = "arm,gic-v3-its";
1177 reg = <0x9010 0x20000 0x0 0x200000>;
1178 msi-controller;
1179 numa-node-id = <1>;
1180 };
1181 };
1182
1183 soc@0 {
1184 compatible = "simple-bus";
1185 #address-cells = <2>;
1186 #size-cells = <2>;
1187 ranges;
1188 numa-node-id = <0>;
1189
1190 gpio-keys {
1191 compatible = "gpio-keys";
1192 button@1 {
1193 lable = "GPIO Key Power";
1194 /* 116 is the value of KEY_POWER, which
1195 is defined in include/uapi/linux/input.h
1196 of Linux kernel code */
1197 linux,code = <116>;
1198 /* Interrupt type: SPI;
1199 Interrupt nunmber: 0, which corresponds to
1200 KEY_POWER_IRQ definition in
1201 plat/thunder/include/thunder_io.h of ATF code;
1202 Flag: 1, edge triggered */
1203 interrupts = <0 0 1>;
1204 };
1205 };
1206
1207 refclkuaa: refclkuaa {
1208 compatible = "fixed-clock";
1209 #clock-cells = <0>;
1210 clock-frequency = <116640000>;
1211 clock-output-names = "refclkuaa";
1212 };
1213
1214 sclk: sclk {
1215 compatible = "fixed-clock";
1216 #clock-cells = <0>;
1217 clock-frequency = <800000000>;
1218 clock-output-names = "sclk";
1219 };
1220
1221 uaa0: serial@87e024000000 {
1222 compatible = "arm,pl011", "arm,primecell";
1223 reg = <0x87e0 0x24000000 0x0 0x1000>;
1224 interrupts = <0 5 4>;
1225 clocks = <&refclkuaa>;
1226 clock-names = "apb_pclk";
1227 };
1228
1229 uaa1: serial@87e025000000 {
1230 compatible = "arm,pl011", "arm,primecell";
1231 reg = <0x87e0 0x25000000 0x0 0x1000>;
1232 interrupts = <0 6 4>;
1233 clocks = <&refclkuaa>;
1234 clock-names = "apb_pclk";
1235 };
1236
1237 smmu0@830000000000 {
1238 compatible = "cavium,smmu-v2";
1239 reg = <0x8300 0x0 0x0 0x2000000>;
1240 #global-interrupts = <1>;
1241 interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1242 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1243 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1244 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1245 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1246 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1247 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1248 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1249 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1250 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1251 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1252 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1253 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1254 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1255 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1256 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1257 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1258 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1259 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1260 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1261 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
1262 <0 69 4>, <0 69 4>, <0 69 4>;
1263
1264 mmu-masters = <&ecam0 0x100>;
1265 };
1266
1267 smmu1@831000000000 {
1268 compatible = "cavium,smmu-v2";
1269 reg = <0x8310 0x0 0x0 0x2000000>;
1270 #global-interrupts = <1>;
1271 interrupts = <0 70 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1272 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1273 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1274 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1275 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1276 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1277 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1278 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1279 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1280 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1281 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1282 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1283 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1284 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1285 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1286 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1287 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1288 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1289 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1290 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1291 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
1292 <0 71 4>, <0 71 4>, <0 71 4>;
1293
1294 mmu-masters = <&ecam1 0x100>,
1295 <&pem0 0x200>,
1296 <&pem1 0x300>,
1297 <&pem2 0x400>;
1298 };
1299
1300 smmu2@832000000000 {
1301 compatible = "cavium,smmu-v2";
1302 reg = <0x8320 0x0 0x0 0x2000000>;
1303 #global-interrupts = <1>;
1304 interrupts = <0 72 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1305 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1306 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1307 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1308 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1309 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1310 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1311 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1312 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1313 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1314 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1315 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1316 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1317 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1318 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1319 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1320 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1321 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1322 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1323 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1324 <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>, <0 73 4>,
1325 <0 73 4>, <0 73 4>, <0 73 4>;
1326
1327 mmu-masters = <&ecam2 0x100>;
1328 };
1329
1330 smmu3@833000000000 {
1331 compatible = "cavium,smmu-v2";
1332 reg = <0x8330 0x0 0x0 0x2000000>;
1333 #global-interrupts = <1>;
1334 interrupts = <0 74 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1335 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1336 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1337 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1338 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1339 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1340 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1341 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1342 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1343 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1344 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1345 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1346 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1347 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1348 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1349 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1350 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1351 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1352 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1353 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1354 <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>, <0 75 4>,
1355 <0 75 4>, <0 75 4>, <0 75 4>;
1356
1357 mmu-masters = <&ecam3 0x100>,
1358 <&pem3 0x200>,
1359 <&pem4 0x300>,
1360 <&pem5 0x400>;
1361 };
1362
1363 ecam0: pci@848000000000 {
1364 compatible = "cavium,pci-host-thunder-ecam";
1365 device_type = "pci";
1366 msi-parent = <&its>;
1367 msi-map = <0 &its 0 0x10000>;
1368 bus-range = <0 31>;
1369 #size-cells = <2>;
1370 #address-cells = <3>;
1371 #stream-id-cells = <1>;
1372 dma-coherent;
1373 reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */
1374 ranges = <0x03000000 0x8020 0x00000000 0x8020 0x00000000 0x060 0x00000000>, /* mem ranges */
1375 <0x03000000 0x8380 0x00000000 0x8380 0x00000000 0x0a0 0x00000000>, /* ZIP et al. */
1376 <0x03000000 0x8460 0x00000000 0x8460 0x00000000 0x020 0x00000000>, /* DFA et al. */
1377 <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x24000000>, /* hole for UARTs */
1378 <0x03000000 0x87e0 0x26000000 0x87e0 0x26000000 0x000 0x9a000000>, /* hole for PEMs */
1379 <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>;
1380
1381 mrml-bridge@1,0 {
1382 compatible = "cavium,thunder-8890-mrml-bridge";
1383 device_type = "pci";
1384 #size-cells = <2>;
1385 #address-cells = <3>;
1386 ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>;
1387 reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */
1388
1389 mdio-nexus@1,3 {
1390 compatible = "cavium,thunder-8890-mdio-nexus";
1391 #address-cells = <2>;
1392 #size-cells = <2>;
1393 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
1394 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
1395 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
1396
1397 mdio@87e005003800 {
1398 compatible = "cavium,thunder-8890-mdio";
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 reg = <0x87e0 0x05003800 0x0 0x30>;
1402
1403 xfi00: xfi@0 {
1404 qlm-mode = "0x000,xfi","0x000,xfi-10g-kr";
1405 reg = <0> ;
1406 compatible = "cortina,cs4223-slice";
1407 };
1408 xfi01: xfi@1 {
1409 qlm-mode = "0x001,xfi","0x001,xfi-10g-kr";
1410 reg = <1> ;
1411 compatible = "cortina,cs4223-slice";
1412 };
1413 xfi02: xfi@2 {
1414 qlm-mode = "0x002,xfi","0x002,xfi-10g-kr";
1415 reg = <2> ;
1416 compatible = "cortina,cs4223-slice";
1417 };
1418 xfi03: xfi@3 {
1419 qlm-mode = "0x003,xfi","0x003,xfi-10g-kr";
1420 reg = <3> ;
1421 compatible = "cortina,cs4223-slice";
1422 };
1423 xlaui00: xlaui@0 {
1424 qlm-mode = "0x000,xlaui","0x000,xlaui-40g-kr";
1425 reg = <0> ;
1426 compatible = "cortina,cs4223-slice";
1427 };
1428 };
1429
1430 mdio@87e005003880 {
1431 compatible = "cavium,thunder-8890-mdio";
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1434 reg = <0x87e0 0x05003880 0x0 0x30>;
1435
1436 xfi10: xfi@0 {
1437 qlm-mode = "0x010,xfi","0x010,xfi-10g-kr";
1438 reg = <0> ;
1439 compatible = "cortina,cs4223-slice";
1440 };
1441 xfi11: xfi@1 {
1442 qlm-mode = "0x011,xfi","0x011,xfi-10g-kr";
1443 reg = <1> ;
1444 compatible = "cortina,cs4223-slice";
1445 };
1446 xfi12: xfi@2 {
1447 qlm-mode = "0x012,xfi","0x012,xfi-10g-kr";
1448 reg = <2> ;
1449 compatible = "cortina,cs4223-slice";
1450 };
1451 xfi13: xfi@3 {
1452 qlm-mode = "0x013,xfi","0x013,xfi-10g-kr";
1453 reg = <3> ;
1454 compatible = "cortina,cs4223-slice";
1455 };
1456 xlaui10: xlaui@0 {
1457 qlm-mode = "0x010,xlaui","0x010,xlaui-40g-kr";
1458 reg = <0> ;
1459 compatible = "cortina,cs4223-slice";
1460 };
1461 };
1462 };
1463
1464// I2C configuration for EBB8800 testing
1465// i2c@9,0 {
1466// #address-cells = <1>;
1467// #size-cells = <0>;
1468// compatible = "cavium,thunder-8890-twsi";
1469// reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */
1470// clock-frequency = <100000>;
1471// clocks = <&sclk>;
1472//
1473// rtc@68 {
1474// compatible = "dallas,ds1337";
1475// reg = <0x68>;
1476// };
1477// };
1478//
1479 bgx0 {
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1482 reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */
1483 /* typename+qlm+typenumber eg :
1484 sgmii+bgx0+sgmmi0
1485 */
1486 // SGMII
1487 sgmii@0 {
1488 reg = <0>;
1489 qlm-mode = "0x000,sgmii";
1490 local-mac-address = [ 00 00 00 00 00 00 ];
1491 phy-handle = <&sgmii00>;
1492 };
1493 sgmii@1 {
1494 reg = <1>;
1495 qlm-mode = "0x001,sgmii";
1496 local-mac-address = [ 00 00 00 00 00 00 ];
1497 phy-handle = <&sgmii01>;
1498 };
1499 sgmii@2 {
1500 reg = <2>;
1501 qlm-mode = "0x002,sgmii";
1502 local-mac-address = [ 00 00 00 00 00 00 ];
1503 phy-handle = <&sgmii02>;
1504 };
1505 sgmii@3 {
1506 reg = <3>;
1507 qlm-mode = "0x003,sgmii";
1508 local-mac-address = [ 00 00 00 00 00 00 ];
1509 phy-handle = <&sgmii03>;
1510 };
1511 xfi@0 {
1512 reg = <0>;
1513 qlm-mode = "0x000,xfi";
1514 local-mac-address = [ 00 00 00 00 00 00 ];
1515 phy-handle = <&xfi00>;
1516 };
1517 xfi@1 {
1518 reg = <1>;
1519 qlm-mode = "0x001,xfi";
1520 local-mac-address = [ 00 00 00 00 00 00 ];
1521 phy-handle = <&xfi01>;
1522 };
1523 xfi@2 {
1524 reg = <2>;
1525 qlm-mode = "0x002,xfi";
1526 local-mac-address = [ 00 00 00 00 00 00 ];
1527 phy-handle = <&xfi02>;
1528 };
1529 xfi@3 {
1530 reg = <3>;
1531 qlm-mode = "0x003,xfi";
1532 local-mac-address = [ 00 00 00 00 00 00 ];
1533 phy-handle = <&xfi03>;
1534 };
1535 // 10g-kr
1536 xfi-10g-kr@0 {
1537 reg = <0>;
1538 qlm-mode = "0x000,xfi-10g-kr";
1539 local-mac-address = [ 00 00 00 00 00 00 ];
1540 phy-handle = <&xfi00>;
1541 };
1542 xfi-10g-kr@1 {
1543 reg = <1>;
1544 qlm-mode = "0x001,xfi-10g-kr";
1545 local-mac-address = [ 00 00 00 00 00 00 ];
1546 phy-handle = <&xfi01>;
1547 };
1548 xfi-10g-kr@2 {
1549 reg = <2>;
1550 qlm-mode = "0x002,xfi-10g-kr";
1551 local-mac-address = [ 00 00 00 00 00 00 ];
1552 phy-handle = <&xfi02>;
1553 };
1554 xfi-10g-kr@3 {
1555 reg = <3>;
1556 qlm-mode = "0x003,xfi-10g-kr";
1557 local-mac-address = [ 00 00 00 00 00 00 ];
1558 phy-handle = <&xfi03>;
1559 };
1560 xlaui@0 {
1561 reg = <0>;
1562 qlm-mode = "0x000,xlaui";
1563 local-mac-address = [ 00 00 00 00 00 00 ];
1564 phy-handle = <&xlaui00>;
1565 };
1566 xlaui-40g-kr@0 {
1567 reg = <0>;
1568 qlm-mode = "0x000,xlaui-40g-kr";
1569 local-mac-address = [ 00 00 00 00 00 00 ];
1570 phy-handle = <&xlaui00>;
1571 };
1572 xaui@0 {
1573 reg = <0>;
1574 qlm-mode = "0x000,xaui";
1575 local-mac-address = [ 00 00 00 00 00 00 ];
1576 phy-handle = <&xaui00>;
1577 };
1578 rxaui@0 {
1579 reg = <0>;
1580 qlm-mode = "0x000,rxaui";
1581 local-mac-address = [ 00 00 00 00 00 00 ];
1582 phy-handle = <&rxaui00>;
1583 };
1584 rxaui@2 {
1585 reg = <2>;
1586 qlm-mode = "0x002,rxaui";
1587 local-mac-address = [ 00 00 00 00 00 00 ];
1588 phy-handle = <&rxaui02>;
1589 };
1590 };
1591
1592 bgx1 {
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1595 reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */
1596
1597 sgmii@0 {
1598 reg = <0>;
1599 qlm-mode = "0x010,sgmii";
1600 local-mac-address = [ 00 00 00 00 00 00 ];
1601 phy-handle = <&sgmii10>; /*"sgmmi"+bgx+no */
1602 };
1603 sgmii@1 {
1604 reg = <1>;
1605 qlm-mode = "0x011,sgmii";
1606 local-mac-address = [ 00 00 00 00 00 00 ];
1607 phy-handle = <&sgmii11>;
1608 };
1609 sgmii@2 {
1610 reg = <2>;
1611 qlm-mode = "0x012,sgmii";
1612 local-mac-address = [ 00 00 00 00 00 00 ];
1613 phy-handle = <&sgmii12>;
1614 };
1615 sgmii@3 {
1616 reg = <3>;
1617 qlm-mode = "0x013,sgmii";
1618 local-mac-address = [ 00 00 00 00 00 00 ];
1619 phy-handle = <&sgmii13>;
1620 };
1621 xfi@0 {
1622 reg = <0>;
1623 qlm-mode = "0x010,xfi";
1624 local-mac-address = [ 00 00 00 00 00 00 ];
1625 phy-handle = <&xfi10>;
1626 };
1627 xfi@1 {
1628 reg = <1>;
1629 qlm-mode = "0x011,xfi";
1630 local-mac-address = [ 00 00 00 00 00 00 ];
1631 phy-handle = <&xfi11>;
1632 };
1633 xfi@2 {
1634 reg = <2>;
1635 qlm-mode = "0x012,xfi";
1636 local-mac-address = [ 00 00 00 00 00 00 ];
1637 phy-handle = <&xfi12>;
1638 };
1639 xfi@3 {
1640 reg = <3>;
1641 qlm-mode = "0x013,xfi";
1642 local-mac-address = [ 00 00 00 00 00 00 ];
1643 phy-handle = <&xfi13>;
1644 };
1645 // 10g_kr
1646 xfi-10g-kr@0 {
1647 reg = <0>;
1648 qlm-mode = "0x010,xfi-10g-kr";
1649 local-mac-address = [ 00 00 00 00 00 00 ];
1650 phy-handle = <&xfi10>;
1651 };
1652 xfi-10g-kr@1 {
1653 reg = <1>;
1654 qlm-mode = "0x011,xfi-10g-kr";
1655 local-mac-address = [ 00 00 00 00 00 00 ];
1656 phy-handle = <&xfi11>;
1657 };
1658 xfi-10g-kr@2 {
1659 reg = <2>;
1660 qlm-mode = "0x012,xfi-10g-kr";
1661 local-mac-address = [ 00 00 00 00 00 00 ];
1662 phy-handle = <&xfi12>;
1663 };
1664 xfi-10g-kr@3 {
1665 reg = <3>;
1666 qlm-mode = "0x013,xfi-10g-kr";
1667 local-mac-address = [ 00 00 00 00 00 00 ];
1668 phy-handle = <&xfi13>;
1669 };
1670 xlaui@0 {
1671 reg = <0>;
1672 qlm-mode = "0x010,xlaui";
1673 local-mac-address = [ 00 00 00 00 00 00 ];
1674 phy-handle = <&xlaui10>;
1675 };
1676 xlaui-40g-kr-@0 {
1677 reg = <0>;
1678 qlm-mode = "0x010,xlaui-40g-kr";
1679 local-mac-address = [ 00 00 00 00 00 00 ];
1680 phy-handle = <&xlaui10>;
1681 };
1682 xaui@0 {
1683 reg = <0>;
1684 qlm-mode = "0x010,xaui";
1685 local-mac-address = [ 00 00 00 00 00 00 ];
1686 phy-handle = <&xaui10>;
1687 };
1688 rxaui@0 {
1689 reg = <0>;
1690 qlm-mode = "0x010,rxaui";
1691 local-mac-address = [ 00 00 00 00 00 00 ];
1692 phy-handle = <&rxaui10>;
1693 };
1694 rxaui@2 {
1695 reg = <2>;
1696 qlm-mode = "0x012,rxaui";
1697 local-mac-address = [ 00 00 00 00 00 00 ];
1698 phy-handle = <&rxaui12>;
1699 };
1700 };
1701 };
1702
1703// SPI configuration for EBB8800 testing
1704// spi@7,0 {
1705// compatible = "cavium,thunder-8890-spi";
1706// reg = <0x3800 0 0 0 0>; /* DEVFN = 0x38 (7:0) */
1707// #address-cells = <1>;
1708// #size-cells = <0>;
1709// clocks = <&sclk>;
1710//
1711// flash@0 {
1712// compatible = "jedec,spi-nor";
1713// reg = <0>;
1714// spi-max-frequency = <16000000>;
1715// #address-cells = <1>;
1716// #size-cells = <1>;
1717// };
1718// };
1719//
1720 };
1721
1722 ecam1: pci@849000000000 {
1723 compatible = "cavium,pci-host-thunder-ecam";
1724 device_type = "pci";
1725 msi-parent = <&its>;
1726 msi-map = <0 &its 0x10000 0x10000>;
1727 bus-range = <0 31>;
1728 #size-cells = <2>;
1729 #address-cells = <3>;
1730 #stream-id-cells = <1>;
1731 dma-coherent;
1732 reg = <0x8490 0x00000000 0 0x02000000>; /* Configuration space */
1733 ranges = <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>; /* mem ranges */
1734 };
1735
1736 ecam2: pci@84a000000000 {
1737 compatible = "cavium,pci-host-thunder-ecam";
1738 device_type = "pci";
1739 msi-parent = <&its>;
1740 msi-map = <0 &its 0x20000 0x10000>;
1741 bus-range = <0 31>;
1742 #size-cells = <2>;
1743 #address-cells = <3>;
1744 #stream-id-cells = <1>;
1745 dma-coherent;
1746 reg = <0x84a0 0x00000000 0 0x02000000>; /* Configuration space */
1747 ranges = <0x03000000 0x8420 0x00000000 0x8420 0x00000000 0x20 0x00000000>; /* mem ranges */
1748 };
1749
1750 ecam3: pci@84b000000000 {
1751 compatible = "cavium,pci-host-thunder-ecam";
1752 device_type = "pci";
1753 msi-parent = <&its>;
1754 msi-map = <0 &its 0x30000 0x10000>;
1755 bus-range = <0 31>;
1756 #size-cells = <2>;
1757 #address-cells = <3>;
1758 #stream-id-cells = <1>;
1759 dma-coherent;
1760 reg = <0x84b0 0x00000000 0 0x02000000>; /* Configuration space */
1761 ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */
1762 };
1763
1764 pem0: pci@87e0c0000000 {
1765
1766 /* "cavium,pci-host-thunder-pem" implies that
1767 the first bus in bus-range has config access
1768 via the "PEM space", subsequent buses have
1769 config assess via the "Configuration space".
1770 The "mem64 PEM" range is used to map the PEM
1771 BAR0, which is used by the AER and PME MSI-X
1772 sources. UEFI and Linux must assign the same
1773 bus number to each device, otherwise Linux
1774 enumeration gets confused. Because UEFI
1775 skips the PEM bus and its PCIe-RC bridge it
1776 uses a numbering that starts 1 bus higher.
1777 */
1778
1779 compatible = "cavium,pci-host-thunder-pem";
1780 device_type = "pci";
1781 msi-parent = <&its>;
1782 msi-map = <0 &its 0x10000 0x10000>;
1783 bus-range = <0x1f 0x57>;
1784 #size-cells = <2>;
1785 #address-cells = <3>;
1786 #stream-id-cells = <1>;
1787 dma-coherent;
1788 reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */
1789 <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */
1790 ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */
1791 <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */
1792 <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */
1793 <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */
1794
1795 #interrupt-cells = <1>;
1796 interrupt-map-mask = <0 0 0 7>;
1797 interrupt-map = <0 0 0 1 &gic0 0 0 0 16 4>, /* INTA */
1798 <0 0 0 2 &gic0 0 0 0 17 4>, /* INTB */
1799 <0 0 0 3 &gic0 0 0 0 18 4>, /* INTC */
1800 <0 0 0 4 &gic0 0 0 0 19 4>; /* INTD */
1801 };
1802
1803 pem1: pci@87e0c1000000 {
1804 compatible = "cavium,pci-host-thunder-pem";
1805 device_type = "pci";
1806 msi-parent = <&its>;
1807 msi-map = <0 &its 0x10000 0x10000>;
1808 bus-range = <0x57 0x8f>;
1809 #size-cells = <2>;
1810 #address-cells = <3>;
1811 #stream-id-cells = <1>;
1812 dma-coherent;
1813 reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */
1814 <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */
1815 ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */
1816 <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */
1817 <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */
1818 <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */
1819
1820 #interrupt-cells = <1>;
1821 interrupt-map-mask = <0 0 0 7>;
1822 interrupt-map = <0 0 0 1 &gic0 0 0 0 20 4>, /* INTA */
1823 <0 0 0 2 &gic0 0 0 0 21 4>, /* INTB */
1824 <0 0 0 3 &gic0 0 0 0 22 4>, /* INTC */
1825 <0 0 0 4 &gic0 0 0 0 23 4>; /* INTD */
1826 };
1827
1828 pem2: pci@87e0c2000000 {
1829 compatible = "cavium,pci-host-thunder-pem";
1830 device_type = "pci";
1831 msi-parent = <&its>;
1832 msi-map = <0 &its 0x10000 0x10000>;
1833 bus-range = <0x8f 0xc7>;
1834 #size-cells = <2>;
1835 #address-cells = <3>;
1836 #stream-id-cells = <1>;
1837 dma-coherent;
1838 reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */
1839 <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */
1840 ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */
1841 <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */
1842 <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
1843 <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */
1844
1845 #interrupt-cells = <1>;
1846 interrupt-map-mask = <0 0 0 7>;
1847 interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */
1848 <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */
1849 <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */
1850 <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */
1851 };
1852
1853 pem3: pci@87e0c3000000 {
1854 compatible = "cavium,pci-host-thunder-pem";
1855 device_type = "pci";
1856 msi-parent = <&its>;
1857 msi-map = <0 &its 0x30000 0x10000>;
1858 bus-range = <0x1f 0x57>;
1859 #size-cells = <2>;
1860 #address-cells = <3>;
1861 #stream-id-cells = <1>;
1862 dma-coherent;
1863 reg = <0x8900 0x1f000000 0x0 0x39000000>, /* Configuration space */
1864 <0x87e0 0xc3000000 0x0 0x01000000>; /* PEM space */
1865 ranges = <0x01000000 0x00 0x00030000 0x8930 0x00030000 0x00 0x00010000>, /* I/O */
1866 <0x03000000 0x00 0x10000000 0x8910 0x10000000 0x0f 0xf0000000>, /* mem64 */
1867 <0x43000000 0x10 0x00000000 0x8920 0x00000000 0x10 0x00000000>, /* mem64-pref */
1868 <0x03000000 0x87e0 0xc3000000 0x87e0 0xc3000000 0x00 0x01000000>; /* mem64 PEM */
1869
1870 #interrupt-cells = <1>;
1871 interrupt-map-mask = <0 0 0 7>;
1872 interrupt-map = <0 0 0 1 &gic0 0 0 0 28 4>, /* INTA */
1873 <0 0 0 2 &gic0 0 0 0 29 4>, /* INTB */
1874 <0 0 0 3 &gic0 0 0 0 30 4>, /* INTC */
1875 <0 0 0 4 &gic0 0 0 0 31 4>; /* INTD */
1876 };
1877
1878 pem4: pci@87e0c4000000 {
1879 compatible = "cavium,pci-host-thunder-pem";
1880 device_type = "pci";
1881 msi-parent = <&its>;
1882 msi-map = <0 &its 0x30000 0x10000>;
1883 bus-range = <0x57 0x8f>;
1884 #size-cells = <2>;
1885 #address-cells = <3>;
1886 #stream-id-cells = <1>;
1887 dma-coherent;
1888 reg = <0x8940 0x57000000 0x0 0x39000000>, /* Configuration space */
1889 <0x87e0 0xc4000000 0x0 0x01000000>; /* PEM space */
1890 ranges = <0x01000000 0x00 0x00040000 0x8970 0x00040000 0x00 0x00010000>, /* I/O */
1891 <0x03000000 0x00 0x10000000 0x8950 0x10000000 0x0f 0xf0000000>, /* mem64 */
1892 <0x43000000 0x10 0x00000000 0x8960 0x00000000 0x10 0x00000000>, /* mem64-pref */
1893 <0x03000000 0x87e0 0xc4000000 0x87e0 0xc4000000 0x00 0x01000000>; /* mem64 PEM */
1894
1895 #interrupt-cells = <1>;
1896 interrupt-map-mask = <0 0 0 7>;
1897 interrupt-map = <0 0 0 1 &gic0 0 0 0 32 4>, /* INTA */
1898 <0 0 0 2 &gic0 0 0 0 33 4>, /* INTB */
1899 <0 0 0 3 &gic0 0 0 0 34 4>, /* INTC */
1900 <0 0 0 4 &gic0 0 0 0 35 4>; /* INTD */
1901 };
1902
1903 pem5: pci@87e0c5000000 {
1904 compatible = "cavium,pci-host-thunder-pem";
1905 device_type = "pci";
1906 msi-parent = <&its>;
1907 msi-map = <0 &its 0x30000 0x10000>;
1908 bus-range = <0x8f 0xc7>;
1909 #size-cells = <2>;
1910 #address-cells = <3>;
1911 #stream-id-cells = <1>;
1912 dma-coherent;
1913 reg = <0x8980 0x8f000000 0x0 0x39000000>, /* Configuration space */
1914 <0x87e0 0xc5000000 0x0 0x01000000>; /* PEM space */
1915 ranges = <0x01000000 0x00 0x00050000 0x89b0 0x00050000 0x00 0x00010000>, /* I/O */
1916 <0x03000000 0x00 0x10000000 0x8990 0x10000000 0x0f 0xf0000000>, /* mem64 */
1917 <0x43000000 0x10 0x00000000 0x89a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
1918 <0x03000000 0x87e0 0xc5000000 0x87e0 0xc5000000 0x00 0x01000000>; /* mem64 PEM */
1919
1920 #interrupt-cells = <1>;
1921 interrupt-map-mask = <0 0 0 7>;
1922 interrupt-map = <0 0 0 1 &gic0 0 0 0 36 4>, /* INTA */
1923 <0 0 0 2 &gic0 0 0 0 37 4>, /* INTB */
1924 <0 0 0 3 &gic0 0 0 0 38 4>, /* INTC */
1925 <0 0 0 4 &gic0 0 0 0 39 4>; /* INTD */
1926 };
1927
1928 };
1929
1930 soc@100000000000 {
1931 compatible = "simple-bus";
1932 #address-cells = <2>;
1933 #size-cells = <2>;
1934 ranges = <0x8000 0 0x9000 0x00000000 0x1000 0x00000000>;
1935 numa-node-id = <1>;
1936
1937 smmu4@830000000000 {
1938 compatible = "cavium,smmu-v2";
1939 reg = <0x8300 0x0 0x0 0x2000000>;
1940 #global-interrupts = <1>;
1941 interrupts = <0 76 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1942 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1943 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1944 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1945 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1946 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1947 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1948 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1949 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1950 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1951 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1952 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1953 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1954 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1955 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1956 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1957 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1958 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1959 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1960 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1961 <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>, <0 77 4>,
1962 <0 77 4>, <0 77 4>, <0 77 4>;
1963
1964 mmu-masters = <&ecam4 0x100>;
1965 };
1966
1967 smmu5@831000000000 {
1968 compatible = "cavium,smmu-v2";
1969 reg = <0x8310 0x0 0x0 0x2000000>;
1970 #global-interrupts = <1>;
1971 interrupts = <0 78 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1972 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1973 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1974 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1975 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1976 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1977 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1978 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1979 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1980 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1981 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1982 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1983 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1984 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1985 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1986 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1987 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1988 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1989 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1990 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1991 <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>, <0 79 4>,
1992 <0 79 4>, <0 79 4>, <0 79 4>;
1993
1994 mmu-masters = <&ecam5 0x100>,
1995 <&pem6 0x200>,
1996 <&pem7 0x300>,
1997 <&pem8 0x400>;
1998 };
1999
2000 smmu6@832000000000 {
2001 compatible = "cavium,smmu-v2";
2002 reg = <0x8320 0x0 0x0 0x2000000>;
2003 #global-interrupts = <1>;
2004 interrupts = <0 80 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2005 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2006 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2007 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2008 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2009 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2010 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2011 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2012 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2013 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2014 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2015 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2016 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2017 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2018 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2019 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2020 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2021 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2022 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2023 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2024 <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>, <0 81 4>,
2025 <0 81 4>, <0 81 4>, <0 81 4>;
2026
2027 mmu-masters = <&ecam6 0x100>;
2028 };
2029
2030 smmu7@833000000000 {
2031 compatible = "cavium,smmu-v2";
2032 reg = <0x8330 0x0 0x0 0x2000000>;
2033 #global-interrupts = <1>;
2034
2035 interrupts = <0 82 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2036 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2037 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2038 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2039 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2040 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2041 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2042 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2043 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2044 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2045 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2046 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2047 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2048 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2049 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2050 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2051 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2052 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2053 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2054 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2055 <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>, <0 83 4>,
2056 <0 83 4>, <0 83 4>, <0 83 4>;
2057
2058 mmu-masters = <&ecam7 0x100>,
2059 <&pem9 0x200>,
2060 <&pem10 0x300>,
2061 <&pem11 0x400>;
2062 };
2063
2064
2065 ecam4: pci@848000000000 {
2066 compatible = "cavium,pci-host-thunder-ecam";
2067 device_type = "pci";
2068 msi-parent = <&its1>;
2069 msi-map = <0 &its1 0x80000 0x10000>;
2070 bus-range = <0 31>;
2071 #size-cells = <2>;
2072 #address-cells = <3>;
2073 #stream-id-cells = <1>;
2074 dma-coherent;
2075 reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */
2076 ranges = <0x03000000 0x8020 0x00000000 0x8020 0x00000000 0x060 0x00000000>, /* mem ranges */
2077 <0x03000000 0x8380 0x00000000 0x8380 0x00000000 0x0a0 0x00000000>, /* ZIP et al. */
2078 <0x03000000 0x8460 0x00000000 0x8460 0x00000000 0x020 0x00000000>, /* DFA et al. */
2079 <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x24000000>, /* hole for UARTs */
2080 <0x03000000 0x87e0 0x26000000 0x87e0 0x26000000 0x000 0x9a000000>, /* hole for PEMs */
2081 <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>;
2082
2083 mrml-bridge@1,0 {
2084 compatible = "cavium,thunder-8890-mrml-bridge";
2085 device_type = "pci";
2086 #size-cells = <2>;
2087 #address-cells = <3>;
2088 ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>;
2089 reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */
2090
2091 mdio-nexus@1,3 {
2092 compatible = "cavium,thunder-8890-mdio-nexus";
2093 #address-cells = <2>;
2094 #size-cells = <2>;
2095 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
2096 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
2097 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
2098
2099 mdio@87e05003800 {
2100 compatible = "cavium,thunder-8890-mdio";
2101 #address-cells = <1>;
2102 #size-cells = <0>;
2103 reg = <0x87e0 0x05003800 0x0 0x30>;
2104
2105 sgmii20: sgmii@0 {
2106 qlm-mode = "0x100,sgmii";
2107 reg = <0> ;
2108 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2109 /* LED[2,1]: Speed, LED[3]: RX, LED[0]: TX, all open-drain */
2110 marvell,reg-init = <3 0x10 0 0x8665>,
2111 <3 0x11 0 0x00aa>,
2112 <3 0x12 0 0x4105>,
2113 <3 0x13 0 0x8a08>;
2114 };
2115 sgmii21: sgmii@1 {
2116 qlm-mode = "0x101,sgmii";
2117 reg = <1> ;
2118 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2119 marvell,reg-init = <3 0x10 0 0x8665>,
2120 <3 0x11 0 0x00aa>,
2121 <3 0x12 0 0x4105>,
2122 <3 0x13 0 0x8a08>;
2123 };
2124 sgmii22: sgmii@2 {
2125 qlm-mode = "0x102,sgmii";
2126 reg = <2> ;
2127 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2128 marvell,reg-init = <3 0x10 0 0x8665>,
2129 <3 0x11 0 0x00aa>,
2130 <3 0x12 0 0x4105>,
2131 <3 0x13 0 0x8a08>;
2132 };
2133 sgmii23: sgmii@3 {
2134 qlm-mode = "0x103,sgmii";
2135 reg = <3> ;
2136 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2137 marvell,reg-init = <3 0x10 0 0x8665>,
2138 <3 0x11 0 0x00aa>,
2139 <3 0x12 0 0x4105>,
2140 <3 0x13 0 0x8a08>;
2141 };
2142 xfi20: xfi@0 {
2143 qlm-mode = "0x100,xfi","0x100,xfi-10g-kr";
2144 reg = <0> ;
2145 compatible = "cortina,cs4223-slice";
2146 };
2147 xfi21: xfi@1 {
2148 qlm-mode = "0x101,xfi","0x101,xfi-10g-kr";
2149 reg = <1> ;
2150 compatible = "cortina,cs4223-slice";
2151 };
2152 xfi22: xfi@2 {
2153 qlm-mode = "0x102,xfi","0x102,xfi-10g-kr";
2154 reg = <2> ;
2155 compatible = "cortina,cs4223-slice";
2156 };
2157 xfi23: xfi@3 {
2158 qlm-mode = "0x103,xfi","0x103,xfi-10g-kr";
2159 reg = <3> ;
2160 compatible = "cortina,cs4223-slice";
2161 };
2162 xlaui20: xlaui@0 {
2163 qlm-mode = "0x100,xlaui","0x100,xlaui-40g-kr";
2164 reg = <0> ;
2165 compatible = "cortina,cs4223-slice";
2166 };
2167 xaui20: xaui@0 {
2168 qlm-mode = "0x100,xaui";
2169 reg = <0> ;
2170 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
2171 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
2172 };
2173 rxaui20: rxaui@0 {
2174 qlm-mode = "0x100,rxaui";
2175 reg = <0> ;
2176 compatible = "marvell,88x3120", "ethernet-phy-ieee802.3-c45";
2177 };
2178 rxaui22: rxaui@1 {
2179 qlm-mode = "0x102,rxaui";
2180 reg = <1> ;
2181 compatible = "marvell,88x3120", "ethernet-phy-ieee802.3-c45";
2182 };
2183 };
2184
2185 mdio@87e005003880 {
2186 compatible = "cavium,thunder-8890-mdio";
2187 #address-cells = <1>;
2188 #size-cells = <0>;
2189 reg = <0x87e0 0x05003880 0x0 0x30>;
2190
2191 sgmii30: sgmii@4 {
2192 qlm-mode = "0x110,sgmii";
2193 reg = <4> ;
2194 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2195 marvell,reg-init = <3 0x10 0 0x8665>,
2196 <3 0x11 0 0x00aa>,
2197 <3 0x12 0 0x4105>,
2198 <3 0x13 0 0x8a08>;
2199 };
2200 sgmii31: sgmii@5 {
2201 qlm-mode = "0x111,sgmii";
2202 reg = <5> ;
2203 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2204 marvell,reg-init = <3 0x10 0 0x8665>,
2205 <3 0x11 0 0x00aa>,
2206 <3 0x12 0 0x4105>,
2207 <3 0x13 0 0x8a08>;
2208
2209 };
2210 sgmii32: sgmii@6 {
2211 qlm-mode = "0x112,sgmii";
2212 reg = <6> ;
2213 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2214 marvell,reg-init = <3 0x10 0 0x8665>,
2215 <3 0x11 0 0x00aa>,
2216 <3 0x12 0 0x4105>,
2217 <3 0x13 0 0x8a08>;
2218 };
2219 sgmii33: sgmii@7 {
2220 qlm-mode = "0x113,sgmii";
2221 reg = <7> ;
2222 compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
2223 marvell,reg-init = <3 0x10 0 0x8665>,
2224 <3 0x11 0 0x00aa>,
2225 <3 0x12 0 0x4105>,
2226 <3 0x13 0 0x8a08>;
2227 };
2228 xfi30: xfi@0 {
2229 qlm-mode = "0x110,xfi","0x110,xfi-10g-kr";
2230 reg = <0> ;
2231 compatible = "cortina,cs4223-slice";
2232 };
2233 xfi31: xfi@1 {
2234 qlm-mode = "0x111,xfi","0x111,xfi-10g-kr";
2235 reg = <1> ;
2236 compatible = "cortina,cs4223-slice";
2237 };
2238 xfi32: xfi@2 {
2239 qlm-mode = "0x112,xfi","0x112,xfi-10g-kr";
2240 reg = <2> ;
2241 compatible = "cortina,cs4223-slice";
2242 };
2243 xfi33: xfi@3 {
2244 qlm-mode = "0x113,xfi","0x113,xfi-10g-kr";
2245 reg = <3> ;
2246 compatible = "cortina,cs4223-slice";
2247 };
2248 xlaui30: xlaui@0 {
2249 qlm-mode = "0x110,xlaui","0x110,xlaui-40g-kr";
2250 reg = <0> ;
2251 compatible = "cortina,cs4223-slice";
2252 };
2253 xaui30: xaui@4 {
2254 qlm-mode = "0x110,xaui";
2255 reg = <4> ;
2256 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
2257 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
2258 };
2259 rxaui30: rxaui@0 {
2260 qlm-mode = "0x110,rxaui";
2261 reg = <0> ;
2262 compatible = "marvell,88x3120", "ethernet-phy-ieee802.3-c45";
2263 };
2264 rxaui32: rxaui@1 {
2265 qlm-mode = "0x112,rxaui";
2266 reg = <1> ;
2267 compatible = "marvell,88x3120", "ethernet-phy-ieee802.3-c45";
2268 };
2269 };
2270 };
2271
2272
2273
2274 bgx2 {
2275 #address-cells = <1>;
2276 #size-cells = <0>;
2277 reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */
2278 /* typename+qlm+typenumber eg :
2279 sgmii+bgx0+sgmmi0
2280 */
2281 // SGMII
2282 sgmii@0 {
2283 reg = <0>;
2284 qlm-mode = "0x100,sgmii";
2285 local-mac-address = [ 00 00 00 00 00 00 ];
2286 phy-handle = <&sgmii20>;
2287 };
2288 sgmii@1 {
2289 reg = <1>;
2290 qlm-mode = "0x101,sgmii";
2291 local-mac-address = [ 00 00 00 00 00 00 ];
2292 phy-handle = <&sgmii21>;
2293 };
2294 sgmii@2 {
2295 reg = <2>;
2296 qlm-mode = "0x102,sgmii";
2297 local-mac-address = [ 00 00 00 00 00 00 ];
2298 phy-handle = <&sgmii22>;
2299 };
2300 sgmii@3 {
2301 reg = <3>;
2302 qlm-mode = "0x103,sgmii";
2303 local-mac-address = [ 00 00 00 00 00 00 ];
2304 phy-handle = <&sgmii23>;
2305 };
2306 xfi@0 {
2307 reg = <0>;
2308 qlm-mode = "0x100,xfi";
2309 local-mac-address = [ 00 00 00 00 00 00 ];
2310 phy-handle = <&xfi20>;
2311 };
2312 xfi@1 {
2313 reg = <1>;
2314 qlm-mode = "0x101,xfi";
2315 local-mac-address = [ 00 00 00 00 00 00 ];
2316 phy-handle = <&xfi21>;
2317 };
2318 xfi@2 {
2319 reg = <2>;
2320 qlm-mode = "0x102,xfi";
2321 local-mac-address = [ 00 00 00 00 00 00 ];
2322 phy-handle = <&xfi22>;
2323 };
2324 xfi@3 {
2325 reg = <3>;
2326 qlm-mode = "0x103,xfi";
2327 local-mac-address = [ 00 00 00 00 00 00 ];
2328 phy-handle = <&xfi23>;
2329 };
2330 // 10g-kr
2331 xfi-10g-kr@0 {
2332 reg = <0>;
2333 qlm-mode = "0x100,xfi-10g-kr";
2334 local-mac-address = [ 00 00 00 00 00 00 ];
2335 phy-handle = <&xfi20>;
2336 };
2337 xfi-10g-kr@1 {
2338 reg = <1>;
2339 qlm-mode = "0x101,xfi-10g-kr";
2340 local-mac-address = [ 00 00 00 00 00 00 ];
2341 phy-handle = <&xfi21>;
2342 };
2343 xfi-10g-kr@2 {
2344 reg = <2>;
2345 qlm-mode = "0x102,xfi-10g-kr";
2346 local-mac-address = [ 00 00 00 00 00 00 ];
2347 phy-handle = <&xfi22>;
2348 };
2349 xfi-10g-kr@3 {
2350 reg = <3>;
2351 qlm-mode = "0x103,xfi-10g-kr";
2352 local-mac-address = [ 00 00 00 00 00 00 ];
2353 phy-handle = <&xfi23>;
2354 };
2355 xlaui@0 {
2356 reg = <0>;
2357 qlm-mode = "0x100,xlaui";
2358 local-mac-address = [ 00 00 00 00 00 00 ];
2359 phy-handle = <&xlaui20>;
2360 };
2361 xlaui-40g-kr@0 {
2362 reg = <0>;
2363 qlm-mode = "0x100,xlaui-40g-kr";
2364 local-mac-address = [ 00 00 00 00 00 00 ];
2365 phy-handle = <&xlaui20>;
2366 };
2367 xaui@0 {
2368 reg = <0>;
2369 qlm-mode = "0x100,xaui";
2370 local-mac-address = [ 00 00 00 00 00 00 ];
2371 phy-handle = <&xaui20>;
2372 };
2373 rxaui@0 {
2374 reg = <0>;
2375 qlm-mode = "0x100,rxaui";
2376 local-mac-address = [ 00 00 00 00 00 00 ];
2377 phy-handle = <&rxaui20>;
2378 };
2379 rxaui@2 {
2380 reg = <2>;
2381 qlm-mode = "0x102,rxaui";
2382 local-mac-address = [ 00 00 00 00 00 00 ];
2383 phy-handle = <&rxaui22>;
2384 };
2385 };
2386
2387 bgx3 {
2388 #address-cells = <1>;
2389 #size-cells = <0>;
2390 reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */
2391
2392 sgmii@0 {
2393 reg = <0>;
2394 qlm-mode = "0x110,sgmii";
2395 local-mac-address = [ 00 00 00 00 00 00 ];
2396 phy-handle = <&sgmii30>; /*"sgmmi"+bgx+no */
2397 };
2398 sgmii@1 {
2399 reg = <1>;
2400 qlm-mode = "0x111,sgmii";
2401 local-mac-address = [ 00 00 00 00 00 00 ];
2402 phy-handle = <&sgmii31>;
2403 };
2404 sgmii@2 {
2405 reg = <2>;
2406 qlm-mode = "0x112,sgmii";
2407 local-mac-address = [ 00 00 00 00 00 00 ];
2408 phy-handle = <&sgmii32>;
2409 };
2410 sgmii@3 {
2411 reg = <3>;
2412 qlm-mode = "0x113,sgmii";
2413 local-mac-address = [ 00 00 00 00 00 00 ];
2414 phy-handle = <&sgmii33>;
2415 };
2416 xfi@0 {
2417 reg = <0>;
2418 qlm-mode = "0x110,xfi";
2419 local-mac-address = [ 00 00 00 00 00 00 ];
2420 phy-handle = <&xfi30>;
2421 };
2422 xfi@1 {
2423 reg = <1>;
2424 qlm-mode = "0x111,xfi";
2425 local-mac-address = [ 00 00 00 00 00 00 ];
2426 phy-handle = <&xfi31>;
2427 };
2428 xfi@2 {
2429 reg = <2>;
2430 qlm-mode = "0x112,xfi";
2431 local-mac-address = [ 00 00 00 00 00 00 ];
2432 phy-handle = <&xfi32>;
2433 };
2434 xfi@3 {
2435 reg = <3>;
2436 qlm-mode = "0x113,xfi";
2437 local-mac-address = [ 00 00 00 00 00 00 ];
2438 phy-handle = <&xfi33>;
2439 };
2440 // 10g_kr
2441 xfi-10g-kr@0 {
2442 reg = <0>;
2443 qlm-mode = "0x110,xfi-10g-kr";
2444 local-mac-address = [ 00 00 00 00 00 00 ];
2445 phy-handle = <&xfi30>;
2446 };
2447 xfi-10g-kr@1 {
2448 reg = <1>;
2449 qlm-mode = "0x111,xfi-10g-kr";
2450 local-mac-address = [ 00 00 00 00 00 00 ];
2451 phy-handle = <&xfi31>;
2452 };
2453 xfi-10g-kr@2 {
2454 reg = <2>;
2455 qlm-mode = "0x112,xfi-10g-kr";
2456 local-mac-address = [ 00 00 00 00 00 00 ];
2457 phy-handle = <&xfi32>;
2458 };
2459 xfi-10g-kr@3 {
2460 reg = <3>;
2461 qlm-mode = "0x113,xfi-10g-kr";
2462 local-mac-address = [ 00 00 00 00 00 00 ];
2463 phy-handle = <&xfi33>;
2464 };
2465 xlaui@0 {
2466 reg = <0>;
2467 qlm-mode = "0x110,xlaui";
2468 local-mac-address = [ 00 00 00 00 00 00 ];
2469 phy-handle = <&xlaui30>;
2470 };
2471 xlaui-40g-kr@0 {
2472 reg = <0>;
2473 qlm-mode = "0x110,xlaui-40g-kr";
2474 local-mac-address = [ 00 00 00 00 00 00 ];
2475 phy-handle = <&xlaui30>;
2476 };
2477 xaui@0 {
2478 reg = <0>;
2479 qlm-mode = "0x110,xaui";
2480 local-mac-address = [ 00 00 00 00 00 00 ];
2481 phy-handle = <&xaui30>;
2482 };
2483 rxaui@0 {
2484 reg = <0>;
2485 qlm-mode = "0x110,rxaui";
2486 local-mac-address = [ 00 00 00 00 00 00 ];
2487 phy-handle = <&rxaui30>;
2488 };
2489 rxaui@2 {
2490 reg = <2>;
2491 qlm-mode = "0x112,rxaui";
2492 local-mac-address = [ 00 00 00 00 00 00 ];
2493 phy-handle = <&rxaui32>;
2494 };
2495 };
2496 };
2497 };
2498
2499 ecam5: pci@849000000000 {
2500 compatible = "cavium,pci-host-thunder-ecam";
2501 device_type = "pci";
2502 msi-parent = <&its1>;
2503 msi-map = <0 &its1 0x90000 0x10000>;
2504 bus-range = <0 31>;
2505 #size-cells = <2>;
2506 #address-cells = <3>;
2507 #stream-id-cells = <1>;
2508 dma-coherent;
2509 reg = <0x8490 0x00000000 0 0x02000000>; /* Configuration space */
2510 ranges = <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>; /* mem ranges */
2511 };
2512
2513 ecam6: pci@84a000000000 {
2514 compatible = "cavium,pci-host-thunder-ecam";
2515 device_type = "pci";
2516 msi-parent = <&its1>;
2517 msi-map = <0 &its1 0xa0000 0x10000>;
2518 bus-range = <0 31>;
2519 #size-cells = <2>;
2520 #address-cells = <3>;
2521 #stream-id-cells = <1>;
2522 dma-coherent;
2523 reg = <0x84a0 0x00000000 0 0x02000000>; /* Configuration space */
2524 ranges = <0x03000000 0x8420 0x00000000 0x8420 0x00000000 0x20 0x00000000>; /* mem ranges */
2525 };
2526
2527 ecam7: pci@84b000000000 {
2528 compatible = "cavium,pci-host-thunder-ecam";
2529 device_type = "pci";
2530 msi-parent = <&its1>;
2531 msi-map = <0 &its1 0xb0000 0x10000>;
2532 bus-range = <0 31>;
2533 #size-cells = <2>;
2534 #address-cells = <3>;
2535 #stream-id-cells = <1>;
2536 dma-coherent;
2537 reg = <0x84b0 0x00000000 0 0x02000000>; /* Configuration space */
2538 ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */
2539 };
2540
2541 pem6: pci@87e0c0000000 {
2542 compatible = "cavium,pci-host-thunder-pem";
2543 device_type = "pci";
2544 msi-parent = <&its1>;
2545 msi-map = <0 &its1 0x90000 0x10000>;
2546 bus-range = <0x1f 0x57>;
2547 #size-cells = <2>;
2548 #address-cells = <3>;
2549 #stream-id-cells = <1>;
2550 dma-coherent;
2551 reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */
2552 <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */
2553 ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */
2554 <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */
2555 <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */
2556 <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */
2557
2558 #interrupt-cells = <1>;
2559 interrupt-map-mask = <0 0 0 7>;
2560 interrupt-map = <0 0 0 1 &gic0 0 0 0 40 4>, /* INTA */
2561 <0 0 0 2 &gic0 0 0 0 41 4>, /* INTB */
2562 <0 0 0 3 &gic0 0 0 0 42 4>, /* INTC */
2563 <0 0 0 4 &gic0 0 0 0 43 4>; /* INTD */
2564 };
2565
2566 pem7: pci@87e0c1000000 {
2567 compatible = "cavium,pci-host-thunder-pem";
2568 device_type = "pci";
2569 msi-parent = <&its1>;
2570 msi-map = <0 &its1 0x90000 0x10000>;
2571 bus-range = <0x57 0x8f>;
2572 #size-cells = <2>;
2573 #address-cells = <3>;
2574 #stream-id-cells = <1>;
2575 dma-coherent;
2576 reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */
2577 <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */
2578 ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */
2579 <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */
2580 <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */
2581 <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */
2582
2583 #interrupt-cells = <1>;
2584 interrupt-map-mask = <0 0 0 7>;
2585 interrupt-map = <0 0 0 1 &gic0 0 0 0 44 4>, /* INTA */
2586 <0 0 0 2 &gic0 0 0 0 45 4>, /* INTB */
2587 <0 0 0 3 &gic0 0 0 0 46 4>, /* INTC */
2588 <0 0 0 4 &gic0 0 0 0 47 4>; /* INTD */
2589 };
2590
2591 pem8: pci@87e0c2000000 {
2592 compatible = "cavium,pci-host-thunder-pem";
2593 device_type = "pci";
2594 msi-parent = <&its1>;
2595 msi-map = <0 &its1 0x90000 0x10000>;
2596 bus-range = <0x8f 0xc7>;
2597 #size-cells = <2>;
2598 #address-cells = <3>;
2599 #stream-id-cells = <1>;
2600 dma-coherent;
2601 reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */
2602 <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */
2603 ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */
2604 <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */
2605 <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
2606 <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */
2607
2608 #interrupt-cells = <1>;
2609 interrupt-map-mask = <0 0 0 7>;
2610 interrupt-map = <0 0 0 1 &gic0 0 0 0 48 4>, /* INTA */
2611 <0 0 0 2 &gic0 0 0 0 49 4>, /* INTB */
2612 <0 0 0 3 &gic0 0 0 0 50 4>, /* INTC */
2613 <0 0 0 4 &gic0 0 0 0 51 4>; /* INTD */
2614 };
2615
2616 pem9: pci@87e0c3000000 {
2617 compatible = "cavium,pci-host-thunder-pem";
2618 device_type = "pci";
2619 msi-parent = <&its1>;
2620 msi-map = <0 &its1 0xb0000 0x10000>;
2621 bus-range = <0x1f 0x57>;
2622 #size-cells = <2>;
2623 #address-cells = <3>;
2624 #stream-id-cells = <1>;
2625 dma-coherent;
2626 reg = <0x8900 0x1f000000 0x0 0x39000000>, /* Configuration space */
2627 <0x87e0 0xc3000000 0x0 0x01000000>; /* PEM space */
2628 ranges = <0x01000000 0x00 0x00030000 0x8930 0x00030000 0x00 0x00010000>, /* I/O */
2629 <0x03000000 0x00 0x10000000 0x8910 0x10000000 0x0f 0xf0000000>, /* mem64 */
2630 <0x43000000 0x10 0x00000000 0x8920 0x00000000 0x10 0x00000000>, /* mem64-pref */
2631 <0x03000000 0x87e0 0xc3000000 0x87e0 0xc3000000 0x00 0x01000000>; /* mem64 PEM */
2632
2633 #interrupt-cells = <1>;
2634 interrupt-map-mask = <0 0 0 7>;
2635 interrupt-map = <0 0 0 1 &gic0 0 0 0 52 4>, /* INTA */
2636 <0 0 0 2 &gic0 0 0 0 53 4>, /* INTB */
2637 <0 0 0 3 &gic0 0 0 0 54 4>, /* INTC */
2638 <0 0 0 4 &gic0 0 0 0 55 4>; /* INTD */
2639 };
2640
2641 pem10: pci@87e0c4000000 {
2642 compatible = "cavium,pci-host-thunder-pem";
2643 device_type = "pci";
2644 msi-parent = <&its1>;
2645 msi-map = <0 &its1 0xb0000 0x10000>;
2646 bus-range = <0x57 0x8f>;
2647 #size-cells = <2>;
2648 #address-cells = <3>;
2649 #stream-id-cells = <1>;
2650 dma-coherent;
2651 reg = <0x8940 0x57000000 0x0 0x39000000>, /* Configuration space */
2652 <0x87e0 0xc4000000 0x0 0x01000000>; /* PEM space */
2653 ranges = <0x01000000 0x00 0x00040000 0x8970 0x00040000 0x00 0x00010000>, /* I/O */
2654 <0x03000000 0x00 0x10000000 0x8950 0x10000000 0x0f 0xf0000000>, /* mem64 */
2655 <0x43000000 0x10 0x00000000 0x8960 0x00000000 0x10 0x00000000>, /* mem64-pref */
2656 <0x03000000 0x87e0 0xc4000000 0x87e0 0xc4000000 0x00 0x01000000>; /* mem64 PEM */
2657
2658 #interrupt-cells = <1>;
2659 interrupt-map-mask = <0 0 0 7>;
2660 interrupt-map = <0 0 0 1 &gic0 0 0 0 56 4>, /* INTA */
2661 <0 0 0 2 &gic0 0 0 0 57 4>, /* INTB */
2662 <0 0 0 3 &gic0 0 0 0 58 4>, /* INTC */
2663 <0 0 0 4 &gic0 0 0 0 59 4>; /* INTD */
2664 };
2665
2666 pem11: pci@87e0c5000000 {
2667 compatible = "cavium,pci-host-thunder-pem";
2668 device_type = "pci";
2669 msi-parent = <&its1>;
2670 msi-map = <0 &its1 0xb0000 0x10000>;
2671 bus-range = <0x8f 0xc7>;
2672 #size-cells = <2>;
2673 #address-cells = <3>;
2674 #stream-id-cells = <1>;
2675 dma-coherent;
2676 reg = <0x8980 0x8f000000 0x0 0x39000000>, /* Configuration space */
2677 <0x87e0 0xc5000000 0x0 0x01000000>; /* PEM space */
2678 ranges = <0x01000000 0x00 0x00050000 0x89b0 0x00050000 0x00 0x00010000>, /* I/O */
2679 <0x03000000 0x00 0x10000000 0x8990 0x10000000 0x0f 0xf0000000>, /* mem64 */
2680 <0x43000000 0x10 0x00000000 0x89a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
2681 <0x03000000 0x87e0 0xc5000000 0x87e0 0xc5000000 0x00 0x01000000>; /* mem64 PEM */
2682
2683 #interrupt-cells = <1>;
2684 interrupt-map-mask = <0 0 0 7>;
2685 interrupt-map = <0 0 0 1 &gic0 0 0 0 60 4>, /* INTA */
2686 <0 0 0 2 &gic0 0 0 0 61 4>, /* INTB */
2687 <0 0 0 3 &gic0 0 0 0 62 4>, /* INTC */
2688 <0 0 0 4 &gic0 0 0 0 63 4>; /* INTD */
2689 };
2690 };
2691
2692 aliases {
2693 serial0 = &uaa0;
2694 serial1 = &uaa1;
2695 };
2696
2697 chosen {
2698 stdout-path = "serial0:115200n8";
2699 };
2700
2701 memory@0 {
2702 device_type = "memory";
2703 reg = <0x0 0x01400000 0x3 0xFEC00000>;
2704 /* socket 0 */
2705 numa-node-id = <0>;
2706 };
2707
2708 memory@10000000000 {
2709 device_type = "memory";
2710 reg = <0x100 0x00400000 0x3 0xFFC00000>;
2711 /* socket 1 */
2712 numa-node-id = <1>;
2713 };
2714
2715 distance-map {
2716 compatible = "numa-distance-map-v1";
2717 distance-matrix = <0 0 10>,
2718 <0 1 20>,
2719 <1 1 10>;
2720 };
2721};
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-18 03:16:42 +0000