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1/*
2 * Cavium Thunder DTS file - Thunder SoC description
3 *
4 * Copyright (C) 2016, Cavium Inc.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/ {
51 model = "Cavium ThunderX CN83XX board";
52 compatible = "cavium,thunder-83xx";
53 interrupt-parent = <&gic0>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 cpus {
63 #address-cells = <2>;
64 #size-cells = <0>;
65
66 cpu-map {
67 cluster0 {
68 core0 {
69 cpu = <&CPU0>;
70 };
71 core1 {
72 cpu = <&CPU1>;
73 };
74 core2 {
75 cpu = <&CPU2>;
76 };
77 core3 {
78 cpu = <&CPU3>;
79 };
80 core4 {
81 cpu = <&CPU4>;
82 };
83 core5 {
84 cpu = <&CPU5>;
85 };
86 core6 {
87 cpu = <&CPU6>;
88 };
89 core7 {
90 cpu = <&CPU7>;
91 };
92 core8 {
93 cpu = <&CPU8>;
94 };
95 core9 {
96 cpu = <&CPU9>;
97 };
98 core10 {
99 cpu = <&CPU10>;
100 };
101 core11 {
102 cpu = <&CPU11>;
103 };
104 core12 {
105 cpu = <&CPU12>;
106 };
107 core13 {
108 cpu = <&CPU13>;
109 };
110 core14 {
111 cpu = <&CPU14>;
112 };
113 core15 {
114 cpu = <&CPU15>;
115 };
116 core16 {
117 cpu = <&CPU16>;
118 };
119 core17 {
120 cpu = <&CPU17>;
121 };
122 core18 {
123 cpu = <&CPU18>;
124 };
125 core19 {
126 cpu = <&CPU19>;
127 };
128 core20 {
129 cpu = <&CPU20>;
130 };
131 core21 {
132 cpu = <&CPU21>;
133 };
134 core22 {
135 cpu = <&CPU22>;
136 };
137 core23 {
138 cpu = <&CPU23>;
139 };
140 };
141 };
142
143 CPU0: cpu@0 {
144 device_type = "cpu";
145 compatible = "cavium,thunder", "arm,armv8";
146 reg = <0x0 0x000>;
147 enable-method = "psci";
148 /* socket 0 */
149 numa-node-id = <0>;
150 next-level-cache = <&thunderx_L2_0>;
151 };
152 CPU1: cpu@1 {
153 device_type = "cpu";
154 compatible = "cavium,thunder", "arm,armv8";
155 reg = <0x0 0x001>;
156 enable-method = "psci";
157 numa-node-id = <0>;
158 next-level-cache = <&thunderx_L2_0>;
159 };
160 CPU2: cpu@2 {
161 device_type = "cpu";
162 compatible = "cavium,thunder", "arm,armv8";
163 reg = <0x0 0x002>;
164 enable-method = "psci";
165 numa-node-id = <0>;
166 next-level-cache = <&thunderx_L2_0>;
167 };
168 CPU3: cpu@3 {
169 device_type = "cpu";
170 compatible = "cavium,thunder", "arm,armv8";
171 reg = <0x0 0x003>;
172 enable-method = "psci";
173 numa-node-id = <0>;
174 next-level-cache = <&thunderx_L2_0>;
175 };
176 CPU4: cpu@4 {
177 device_type = "cpu";
178 compatible = "cavium,thunder", "arm,armv8";
179 reg = <0x0 0x004>;
180 enable-method = "psci";
181 numa-node-id = <0>;
182 next-level-cache = <&thunderx_L2_0>;
183 };
184 CPU5: cpu@5 {
185 device_type = "cpu";
186 compatible = "cavium,thunder", "arm,armv8";
187 reg = <0x0 0x005>;
188 enable-method = "psci";
189 numa-node-id = <0>;
190 next-level-cache = <&thunderx_L2_0>;
191 };
192 CPU6: cpu@6 {
193 device_type = "cpu";
194 compatible = "cavium,thunder", "arm,armv8";
195 reg = <0x0 0x006>;
196 enable-method = "psci";
197 numa-node-id = <0>;
198 next-level-cache = <&thunderx_L2_0>;
199 };
200 CPU7: cpu@7 {
201 device_type = "cpu";
202 compatible = "cavium,thunder", "arm,armv8";
203 reg = <0x0 0x007>;
204 enable-method = "psci";
205 numa-node-id = <0>;
206 next-level-cache = <&thunderx_L2_0>;
207 };
208 CPU8: cpu@8 {
209 device_type = "cpu";
210 compatible = "cavium,thunder", "arm,armv8";
211 reg = <0x0 0x008>;
212 enable-method = "psci";
213 numa-node-id = <0>;
214 next-level-cache = <&thunderx_L2_0>;
215 };
216 CPU9: cpu@9 {
217 device_type = "cpu";
218 compatible = "cavium,thunder", "arm,armv8";
219 reg = <0x0 0x009>;
220 enable-method = "psci";
221 numa-node-id = <0>;
222 next-level-cache = <&thunderx_L2_0>;
223 };
224 CPU10: cpu@a {
225 device_type = "cpu";
226 compatible = "cavium,thunder", "arm,armv8";
227 reg = <0x0 0x00a>;
228 enable-method = "psci";
229 numa-node-id = <0>;
230 next-level-cache = <&thunderx_L2_0>;
231 };
232 CPU11: cpu@b {
233 device_type = "cpu";
234 compatible = "cavium,thunder", "arm,armv8";
235 reg = <0x0 0x00b>;
236 enable-method = "psci";
237 numa-node-id = <0>;
238 next-level-cache = <&thunderx_L2_0>;
239 };
240 CPU12: cpu@c {
241 device_type = "cpu";
242 compatible = "cavium,thunder", "arm,armv8";
243 reg = <0x0 0x00c>;
244 enable-method = "psci";
245 numa-node-id = <0>;
246 next-level-cache = <&thunderx_L2_0>;
247 };
248 CPU13: cpu@d {
249 device_type = "cpu";
250 compatible = "cavium,thunder", "arm,armv8";
251 reg = <0x0 0x00d>;
252 enable-method = "psci";
253 numa-node-id = <0>;
254 next-level-cache = <&thunderx_L2_0>;
255 };
256 CPU14: cpu@e {
257 device_type = "cpu";
258 compatible = "cavium,thunder", "arm,armv8";
259 reg = <0x0 0x00e>;
260 enable-method = "psci";
261 numa-node-id = <0>;
262 next-level-cache = <&thunderx_L2_0>;
263 };
264 CPU15: cpu@f {
265 device_type = "cpu";
266 compatible = "cavium,thunder", "arm,armv8";
267 reg = <0x0 0x00f>;
268 enable-method = "psci";
269 numa-node-id = <0>;
270 next-level-cache = <&thunderx_L2_0>;
271 };
272 CPU16: cpu@100 {
273 device_type = "cpu";
274 compatible = "cavium,thunder", "arm,armv8";
275 reg = <0x0 0x100>;
276 enable-method = "psci";
277 numa-node-id = <0>;
278 next-level-cache = <&thunderx_L2_0>;
279 };
280 CPU17: cpu@101 {
281 device_type = "cpu";
282 compatible = "cavium,thunder", "arm,armv8";
283 reg = <0x0 0x101>;
284 enable-method = "psci";
285 numa-node-id = <0>;
286 next-level-cache = <&thunderx_L2_0>;
287 };
288 CPU18: cpu@102 {
289 device_type = "cpu";
290 compatible = "cavium,thunder", "arm,armv8";
291 reg = <0x0 0x102>;
292 enable-method = "psci";
293 numa-node-id = <0>;
294 next-level-cache = <&thunderx_L2_0>;
295 };
296 CPU19: cpu@103 {
297 device_type = "cpu";
298 compatible = "cavium,thunder", "arm,armv8";
299 reg = <0x0 0x103>;
300 enable-method = "psci";
301 numa-node-id = <0>;
302 next-level-cache = <&thunderx_L2_0>;
303 };
304 CPU20: cpu@104 {
305 device_type = "cpu";
306 compatible = "cavium,thunder", "arm,armv8";
307 reg = <0x0 0x104>;
308 enable-method = "psci";
309 numa-node-id = <0>;
310 next-level-cache = <&thunderx_L2_0>;
311 };
312 CPU21: cpu@105 {
313 device_type = "cpu";
314 compatible = "cavium,thunder", "arm,armv8";
315 reg = <0x0 0x105>;
316 enable-method = "psci";
317 numa-node-id = <0>;
318 next-level-cache = <&thunderx_L2_0>;
319 };
320 CPU22: cpu@106 {
321 device_type = "cpu";
322 compatible = "cavium,thunder", "arm,armv8";
323 reg = <0x0 0x106>;
324 enable-method = "psci";
325 numa-node-id = <0>;
326 next-level-cache = <&thunderx_L2_0>;
327 };
328 CPU23: cpu@107 {
329 device_type = "cpu";
330 compatible = "cavium,thunder", "arm,armv8";
331 reg = <0x0 0x107>;
332 enable-method = "psci";
333 numa-node-id = <0>;
334 next-level-cache = <&thunderx_L2_0>;
335 };
336 };
337
338 thunderx_L2_0: l2-cache0 {
339 compatible = "cache";
340 numa-node-id = <0>;
341 };
342
343 timer {
344 compatible = "arm,armv8-timer";
345 interrupts = <1 13 4>,
346 <1 14 4>,
347 <1 11 4>,
348 <1 10 4>;
349 };
350
351 pmu {
352 compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
353 interrupts = <1 7 4>;
354 };
355
356 gic0: interrupt-controller@801000000000 {
357 compatible = "arm,gic-v3";
358 #interrupt-cells = <3>;
359 #address-cells = <2>;
360 #size-cells = <2>;
361 #redistributor-regions = <1>;
362 ranges;
363 interrupt-controller;
364 reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
365 <0x8010 0x80000000 0x0 0x600000>; /* GICR */
366 interrupts = <1 9 4>;
367
368 its: gic-its@801000020000 {
369 compatible = "arm,gic-v3-its";
370 reg = <0x8010 0x20000 0x0 0x200000>;
371 msi-controller;
372 numa-node-id = <0>;
373 };
374 };
375
376 soc@0 {
377 compatible = "simple-bus";
378 #address-cells = <2>;
379 #size-cells = <2>;
380 ranges;
381 numa-node-id = <0>;
382
383 refclkuaa: refclkuaa {
384 compatible = "fixed-clock";
385 #clock-cells = <0>;
386 clock-frequency = <116640000>;
387 clock-output-names = "refclkuaa";
388 };
389
390 sclk: sclk {
391 compatible = "fixed-clock";
392 #clock-cells = <0>;
393 clock-frequency = <800000000>;
394 clock-output-names = "sclk";
395 };
396
397 uaa0: serial@87e028000000 {
398 compatible = "arm,pl011", "arm,primecell";
399 reg = <0x87e0 0x28000000 0x0 0x1000>;
400 interrupts = <0 5 4>;
401 clocks = <&refclkuaa>;
402 clock-names = "apb_pclk";
403 uboot,skip-init;
404 };
405
406 uaa1: serial@87e029000000 {
407 compatible = "arm,pl011", "arm,primecell";
408 reg = <0x87e0 0x29000000 0x0 0x1000>;
409 interrupts = <0 6 4>;
410 clocks = <&refclkuaa>;
411 clock-names = "apb_pclk";
412 uboot,skip-init;
413 };
414
415 watch-dog@8440000a0000 {
416 compatible = "arm,sbsa-gwdt";
417 reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>;
418 interrupts = <0 9 4>;
419 };
420
421 smmu0@830000000000 {
422 compatible = "cavium,smmu-v2";
423 reg = <0x8300 0x0 0x0 0x2000000>;
424 #global-interrupts = <1>;
425 interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
426 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
427 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
428 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
429 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
430 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
431 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
432 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
433 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
434 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
435 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
436 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
437 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
438 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
439 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
440 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
441 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
442 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
443 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
444 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
445 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
446 <0 69 4>, <0 69 4>, <0 69 4>;
447
448 mmu-masters = <&ecam0 0x100>,
449 <&pem0 0x200>,
450 <&pem1 0x300>,
451 <&pem2 0x400>,
452 <&pem3 0x500>;
453
454 };
455
456 smmu1@831000000000 {
457 compatible = "cavium,smmu-v2";
458 reg = <0x8310 0x0 0x0 0x2000000>;
459 #global-interrupts = <1>;
460 interrupts = <0 70 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
461 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
462 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
463 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
464 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
465 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
466 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
467 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
468 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
469 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
470 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
471 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
472 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
473 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
474 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
475 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
476 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
477 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
478 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
479 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
480 <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>, <0 71 4>,
481 <0 71 4>, <0 71 4>, <0 71 4>;
482
483 mmu-masters = <&ecam1 0x100>;
484 };
485
486
487 ecam0: pci@848000000000 {
488 compatible = "cavium,pci-host-octeontx-ecam";
489 device_type = "pci";
490 msi-parent = <&its>;
491 msi-map = <0 &its 0 0x10000>;
492 bus-range = <0x0 0xff>;
493 #size-cells = <2>;
494 #address-cells = <3>;
495 #stream-id-cells = <1>;
496 dma-coherent;
497 reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */
498 ranges = <0x03000000 0x8030 0x00000000 0x8030 0x00000000 0x050 0x00100000>, /* mem ranges */
499 <0x03000000 0x8280 0x00000000 0x8280 0x00000000 0x007 0x02000000>,
500 <0x03000000 0x8400 0x00800000 0x8400 0x00800000 0x00f 0xfc040000>,
501 <0x03000000 0x8580 0x00000000 0x8580 0x00000000 0x0a8 0x04000000>,
502 <0x03000000 0x86e0 0x00000000 0x86e0 0x00000000 0x100 0x28000000>,
503 <0x03000000 0x87e0 0x40000000 0x87e0 0x40000000 0x000 0x6c800000>,
504 <0x03000000 0x87e0 0xd0000000 0x87e0 0xd0000000 0x010 0xaf100000>,
505 <0x03000000 0x0000 0x01400000 0x0000 0x01400000 0x000 0x00A00000>; /* SSO mailbox */
506
507
508 mrml_bridge: mrml-bridge0@1,0 {
509 compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge";
510 #size-cells = <2>;
511 #address-cells = <3>;
512 ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>;
513 reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */
514 device_type = "pci";
515 u-boot,dm-pre-reloc;
516
517 mdio-nexus@1,3 {
518 compatible = "cavium,thunder-8890-mdio-nexus";
519 #address-cells = <2>;
520 #size-cells = <2>;
521 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
522 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
523 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
524
525 mdio0@87e005003800 {
526 compatible = "cavium,thunder-8890-mdio";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <0x87e0 0x05003800 0x0 0x30>;
530
531 };
532
533 mdio1@87e005003880 {
534 compatible = "cavium,thunder-8890-mdio";
535 #address-cells = <1>;
536 #size-cells = <0>;
537 reg = <0x87e0 0x05003880 0x0 0x30>;
538
539
540 };
541 };
542
543 mmc_1_4: mmc@1,4 {
544 compatible = "cavium,thunder-8890-mmc";
545 reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
546 #address-cells = <1>;
547 #size-cells = <0>;
548 clocks = <&sclk>;
549 };
550
551 i2c_9_0: i2c@9,0 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "cavium,thunder-8890-twsi", "cavium,thunderx-i2c";
555 reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */
556 clock-frequency = <100000>;
557 clocks = <&sclk>;
558 u-boot,dm-pre-reloc;
559 };
560
561 i2c_9_1: i2c@9,1 {
562 #address-cells = <1>;
563 #size-cells = <0>;
564 compatible = "cavium,thunder-8890-twsi", "cavium,thunderx-i2c";
565 reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */
566 clock-frequency = <100000>;
567 clocks = <&sclk>;
568 u-boot,dm-pre-reloc;
569 };
570
571 bgx0 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */
575 };
576 bgx1 {
577 #address-cells = <1>;
578 #size-cells = <0>;
579 reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */
580 };
581
582 bgx2 {
583 #address-cells = <1>;
584 #size-cells = <0>;
585 reg = <0x8200 0 0 0 0>; /* DEVFN = 0x82 (16:0) */
586 };
587
588 bgx3 {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 reg = <0x8300 0 0 0 0>; /* DEVFN = 0x83 (16:0) */
592 };
593 };
594
595 spi_7_0: spi@7,0 {
596 compatible = "cavium,thunder-8190-spi", "cavium,thunderx-spi";
597 reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */
598 #address-cells = <1>;
599 #size-cells = <0>;
600 clocks = <&sclk>;
601 };
602
603 gpio_6_0: gpio0@6,0 {
604 #gpio-cells = <2>;
605 compatible = "cavium,thunder-8890-gpio";
606 gpio-controller;
607 reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */
608 u-boot,dm-pre-reloc;
609 };
610 };
611
612 ecam1: pci@849000000000 {
613 compatible = "cavium,pci-host-octeontx-ecam";
614 device_type = "pci";
615 msi-parent = <&its>;
616 msi-map = <0 &its 0x10000 0x10000>;
617 bus-range = <0x0 0xff>;
618 #size-cells = <2>;
619 #address-cells = <3>;
620 #stream-id-cells = <1>;
621 dma-coherent;
622 reg = <0x8490 0x00000000 0 0x10000000>; /* Configuration space */
623 ranges = <0x03000000 0x8090 0x00000000 0x8090 0x00000000 0x0c0 0x00300000>, /* mem ranges */
624 <0x03000000 0x8380 0x00000000 0x8380 0x00000000 0x000 0x30800000>,
625 <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x000 0xf0000000>,
626 <0x03000000 0x8540 0x00000000 0x8540 0x00000000 0x004 0x02000000>,
627 <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x040 0x02000000>,
628 <0x03000000 0x87f1 0x80000000 0x87f1 0x80000000 0x000 0x80000000>, /* LMTLINE */
629 <0x03000000 0x0000 0x01E00000 0x0000 0x01E00000 0x000 0x00A00000>; /* PKI emulated VF space */
630 };
631
632 pem0: pci@87e0c0000000 {
633
634 /* "cavium,pci-host-thunder-pem" implies that
635 the first bus in bus-range has config access
636 via the "PEM space", subsequent buses have
637 config assess via the "Configuration space".
638 The "mem64 PEM" range is used to map the PEM
639 BAR0, which is used by the AER and PME MSI-X
640 sources. UEFI and Linux must assign the same
641 bus number to each device, otherwise Linux
642 enumeration gets confused. Because UEFI
643 skips the PEM bus and its PCIe-RC bridge it
644 uses a numbering that starts 1 bus higher.
645 */
646
647 compatible = "cavium,pci-host-thunder-pem";
648 device_type = "pci";
649 msi-parent = <&its>;
650 msi-map = <0 &its 0 0x10000>;
651 bus-range = <0x1f 0x57>;
652 #size-cells = <2>;
653 #address-cells = <3>;
654 #stream-id-cells = <1>;
655 dma-coherent;
656 reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */
657 <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */
658 ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */
659 <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */
660 <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */
661 <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */
662
663 #interrupt-cells = <1>;
664 interrupt-map-mask = <0 0 0 7>;
665 interrupt-map = <0 0 0 1 &gic0 0 0 0 16 4>, /* INTA */
666 <0 0 0 2 &gic0 0 0 0 17 4>, /* INTB */
667 <0 0 0 3 &gic0 0 0 0 18 4>, /* INTC */
668 <0 0 0 4 &gic0 0 0 0 19 4>; /* INTD */
669 };
670
671 pem1: pci@87e0c1000000 {
672 compatible = "cavium,pci-host-thunder-pem";
673 device_type = "pci";
674 msi-parent = <&its>;
675 msi-map = <0 &its 0 0x10000>;
676 bus-range = <0x57 0x8f>;
677 #size-cells = <2>;
678 #address-cells = <3>;
679 #stream-id-cells = <1>;
680 dma-coherent;
681 reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */
682 <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */
683 ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */
684 <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */
685 <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */
686 <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */
687
688 #interrupt-cells = <1>;
689 interrupt-map-mask = <0 0 0 7>;
690 interrupt-map = <0 0 0 1 &gic0 0 0 0 20 4>, /* INTA */
691 <0 0 0 2 &gic0 0 0 0 21 4>, /* INTB */
692 <0 0 0 3 &gic0 0 0 0 22 4>, /* INTC */
693 <0 0 0 4 &gic0 0 0 0 23 4>; /* INTD */
694 };
695
696 pem2: pci@87e0c2000000 {
697 compatible = "cavium,pci-host-thunder-pem";
698 device_type = "pci";
699 msi-parent = <&its>;
700 msi-map = <0 &its 0 0x10000>;
701 bus-range = <0x8f 0xc7>;
702 #size-cells = <2>;
703 #address-cells = <3>;
704 #stream-id-cells = <1>;
705 dma-coherent;
706 reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */
707 <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */
708 ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */
709 <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */
710 <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
711 <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */
712
713 #interrupt-cells = <1>;
714 interrupt-map-mask = <0 0 0 7>;
715 interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */
716 <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */
717 <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */
718 <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */
719 };
720
721 pem3: pci@87e0c3000000 {
722 compatible = "cavium,pci-host-thunder-pem";
723 device_type = "pci";
724 msi-parent = <&its>;
725 msi-map = <0 &its 0 0x10000>;
726 bus-range = <0xc7 0xff>;
727 #size-cells = <2>;
728 #address-cells = <3>;
729 #stream-id-cells = <1>;
730 dma-coherent;
731 reg = <0x88c0 0xc7000000 0x0 0x39000000>, /* Configuration space */
732 <0x87e0 0xc3000000 0x0 0x01000000>; /* PEM space */
733 ranges = <0x01000000 0x00 0x00030000 0x88f0 0x00030000 0x00 0x00010000>, /* I/O */
734 <0x03000000 0x00 0x10000000 0x88d0 0x10000000 0x0f 0xf0000000>, /* mem64 */
735 <0x43000000 0x10 0x00000000 0x88e0 0x00000000 0x10 0x00000000>, /* mem64-pref */
736 <0x03000000 0x87e0 0xc3000000 0x87e0 0xc3000000 0x00 0x01000000>; /* mem64 PEM */
737
738 #interrupt-cells = <1>;
739 interrupt-map-mask = <0 0 0 7>;
740 interrupt-map = <0 0 0 1 &gic0 0 0 0 28 4>, /* INTA */
741 <0 0 0 2 &gic0 0 0 0 29 4>, /* INTB */
742 <0 0 0 3 &gic0 0 0 0 30 4>, /* INTC */
743 <0 0 0 4 &gic0 0 0 0 31 4>; /* INTD */
744 };
745 };
746
747 aliases {
748 serial0 = &uaa0;
749 serial1 = &uaa1;
750 };
751
752 chosen {
753 stdout-path = &uaa0;
754 };
755
756 memory@00000000 {
757 device_type = "memory";
758 reg = <0x0 0x02800000 0x0 0x7EC00000>;
759 /* socket 0 */
760 numa-node-id = <0>;
761 };
762};
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-18 13:39:16 +0000