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1/*
2 * Cavium Thunder DTS file - Thunder SoC description
3 *
4 * Copyright (C) 2016, Cavium Inc.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/ {
51 model = "Cavium ThunderX CN81XX board";
52 compatible = "cavium,thunder-81xx";
53 interrupt-parent = <&gic0>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 cpus {
63 #address-cells = <2>;
64 #size-cells = <0>;
65
66 cpu-map {
67 cluster0 {
68 core0 {
69 cpu = <&CPU0>;
70 };
71 core1 {
72 cpu = <&CPU1>;
73 };
74 core2 {
75 cpu = <&CPU2>;
76 };
77 core3 {
78 cpu = <&CPU3>;
79 };
80 };
81 };
82
83 CPU0: cpu@0 {
84 device_type = "cpu";
85 compatible = "cavium,thunder", "arm,armv8";
86 reg = <0x0 0x000>;
87 enable-method = "psci";
88 /* socket 0 */
89 numa-node-id = <0>;
90 next-level-cache = <&thunderx_L2_0>;
91 };
92 CPU1: cpu@1 {
93 device_type = "cpu";
94 compatible = "cavium,thunder", "arm,armv8";
95 reg = <0x0 0x001>;
96 enable-method = "psci";
97 numa-node-id = <0>;
98 next-level-cache = <&thunderx_L2_0>;
99 };
100 CPU2: cpu@2 {
101 device_type = "cpu";
102 compatible = "cavium,thunder", "arm,armv8";
103 reg = <0x0 0x002>;
104 enable-method = "psci";
105 numa-node-id = <0>;
106 next-level-cache = <&thunderx_L2_0>;
107 };
108 CPU3: cpu@3 {
109 device_type = "cpu";
110 compatible = "cavium,thunder", "arm,armv8";
111 reg = <0x0 0x003>;
112 enable-method = "psci";
113 numa-node-id = <0>;
114 next-level-cache = <&thunderx_L2_0>;
115 };
116 };
117
118 thunderx_L2_0: l2-cache0 {
119 compatible = "cache";
120 numa-node-id = <0>;
121 };
122
123 timer {
124 compatible = "arm,armv8-timer";
125 interrupts = <1 13 4>,
126 <1 14 4>,
127 <1 11 4>,
128 <1 10 4>;
129 };
130
131 pmu {
132 compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
133 interrupts = <1 7 4>;
134 };
135
136 gic0: interrupt-controller@801000000000 {
137 compatible = "arm,gic-v3";
138 #interrupt-cells = <3>;
139 #address-cells = <2>;
140 #size-cells = <2>;
141 #redistributor-regions = <1>;
142 ranges;
143 interrupt-controller;
144 reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
145 <0x8010 0x80000000 0x0 0x600000>; /* GICR */
146 interrupts = <1 9 4>;
147
148 its: gic-its@801000020000 {
149 compatible = "arm,gic-v3-its";
150 reg = <0x8010 0x20000 0x0 0x200000>;
151 msi-controller;
152 numa-node-id = <0>;
153 };
154 };
155
156 soc@0 {
157 compatible = "simple-bus";
158 #address-cells = <2>;
159 #size-cells = <2>;
160 ranges;
161 numa-node-id = <0>;
162
163 refclkuaa: refclkuaa {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <116640000>;
167 clock-output-names = "refclkuaa";
168 };
169
170 sclk: sclk {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <800000000>;
174 clock-output-names = "sclk";
175 };
176
177 uaa0: serial@87e028000000 {
178 compatible = "arm,pl011", "arm,primecell";
179 reg = <0x87e0 0x28000000 0x0 0x1000>;
180 interrupts = <0 5 4>;
181 clocks = <&refclkuaa>;
182 clock-names = "apb_pclk";
183 uboot,skip-init;
184 };
185
186 uaa1: serial@87e029000000 {
187 compatible = "arm,pl011", "arm,primecell";
188 reg = <0x87e0 0x29000000 0x0 0x1000>;
189 interrupts = <0 6 4>;
190 clocks = <&refclkuaa>;
191 clock-names = "apb_pclk";
192 uboot,skip-init;
193 };
194
195 watch-dog@8440000a0000 {
196 compatible = "arm,sbsa-gwdt";
197 reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>;
198 interrupts = <0 9 4>;
199 };
200
201 pbus0: nor@0 {
202 compatible = "cfi-flash";
203 reg = <0x8000 0x0 0x0 0x800000>;
204 device-width = <1>;
205 bank-width = <1>;
206 clocks = <&sclk>;
207 };
208
209 smmu0@830000000000 {
210 compatible = "cavium,smmu-v2";
211 reg = <0x8300 0x0 0x0 0x2000000>;
212 #global-interrupts = <1>;
213 interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
214 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
215 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
216 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
217 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
218 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
219 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
220 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
221 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
222 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
223 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>;
224
225 mmu-masters = <&ecam0 0x100>,
226 <&pem0 0x200>,
227 <&pem1 0x300>,
228 <&pem2 0x400>;
229
230 };
231
232 ecam0: pci@848000000000 {
233 compatible = "pci-host-ecam-generic";
234 device_type = "pci";
235 msi-parent = <&its>;
236 msi-map = <0 &its 0 0x10000>;
237 bus-range = <0 31>;
238 #size-cells = <2>;
239 #address-cells = <3>;
240 #stream-id-cells = <1>;
241 u-boot,dm-pre-reloc;
242 dma-coherent;
243 reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */
244 ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x080 0x00000000>, /* mem ranges */
245 <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>, /* SATA */
246 <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x28000000>, /* UARTs */
247 <0x03000000 0x87e0 0x2a000000 0x87e0 0x2a000000 0x000 0x96000000>, /* PEMs */
248 <0x03000000 0x8400 0x00000000 0x8400 0x00000000 0x010 0x00000000>, /* RNM */
249 <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x02 0x00000000>, /* NIC0*/
250 <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>;
251
252 mrml_bridge: mrml-bridge0@1,0 {
253 compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge";
254 #size-cells = <2>;
255 #address-cells = <3>;
256 ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>;
257 reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */
258 device_type = "pci";
259 u-boot,dm-pre-reloc;
260
261 mdio-nexus@1,3 {
262 compatible = "cavium,thunder-8890-mdio-nexus";
263 #address-cells = <2>;
264 #size-cells = <2>;
265 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
266 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
267 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
268 mdio0@87e005003800 {
269 compatible = "cavium,thunder-8890-mdio";
270 #address-cells = <1>;
271 #size-cells = <0>;
272 reg = <0x87e0 0x05003800 0x0 0x30>;
273 };
274 mdio1@87e005003880 {
275 compatible = "cavium,thunder-8890-mdio";
276 #address-cells = <1>;
277 #size-cells = <0>;
278 reg = <0x87e0 0x05003880 0x0 0x30>;
279 };
280 };
281
282 mmc_1_4: mmc@1,4 {
283 compatible = "cavium,thunder-8890-mmc";
284 reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
285 #address-cells = <1>;
286 #size-cells = <0>;
287 clocks = <&sclk>;
288 };
289
290 i2c_9_0: i2c@9,0 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "cavium,thunder-8890-twsi", "cavium,thunderx-i2c";
294 reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */
295 clock-frequency = <100000>;
296 clocks = <&sclk>;
297 u-boot,dm-pre-reloc;
298 };
299
300 i2c_9_1: i2c@9,1 {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 compatible = "cavium,thunder-8890-twsi", "cavium,thunderx-i2c";
304 reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */
305 clock-frequency = <100000>;
306 clocks = <&sclk>;
307 u-boot,dm-pre-reloc;
308 };
309
310 rgx0 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <0x9000 0 0 0 0>; /* DEVFN = 0x90 (16:1) */
314 };
315 bgx0 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */
319 };
320 bgx1 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */
324 };
325 };
326
327 spi_7_0: spi@7,0 {
328 compatible = "cavium,thunder-8190-spi", "cavium,thunderx-spi";
329 reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */
330 #address-cells = <1>;
331 #size-cells = <0>;
332 clocks = <&sclk>;
333 };
334
335 gpio_6_0: gpio0@6,0 {
336 #gpio-cells = <2>;
337 compatible = "cavium,thunder-8890-gpio";
338 gpio-controller;
339 reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */
340 u-boot,dm-pre-reloc;
341 };
342
343 nfc: nand@b,0 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "cavium,cn8130-nand";
347 reg = <0x5800 0 0 0 0>; /* DEVFN = 0x58 (b:0) */
348 clocks = <&sclk>;
349 };
350 };
351
352 pem0: pci@87e0c0000000 {
353
354 /* "cavium,pci-host-thunder-pem" implies that
355 the first bus in bus-range has config access
356 via the "PEM space", subsequent buses have
357 config assess via the "Configuration space".
358 The "mem64 PEM" range is used to map the PEM
359 BAR0, which is used by the AER and PME MSI-X
360 sources. UEFI and Linux must assign the same
361 bus number to each device, otherwise Linux
362 enumeration gets confused. Because UEFI
363 skips the PEM bus and its PCIe-RC bridge it
364 uses a numbering that starts 1 bus higher.
365 */
366
367 compatible = "cavium,pci-host-thunder-pem";
368 device_type = "pci";
369 msi-parent = <&its>;
370 msi-map = <0 &its 0 0x10000>;
371 bus-range = <0x1f 0x57>;
372 #size-cells = <2>;
373 #address-cells = <3>;
374 #stream-id-cells = <1>;
375 dma-coherent;
376 reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */
377 <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */
378 ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */
379 <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */
380 <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */
381 <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */
382
383 #interrupt-cells = <1>;
384 interrupt-map-mask = <0 0 0 7>;
385 interrupt-map = <0 0 0 1 &gic0 0 0 0 16 4>, /* INTA */
386 <0 0 0 2 &gic0 0 0 0 17 4>, /* INTB */
387 <0 0 0 3 &gic0 0 0 0 18 4>, /* INTC */
388 <0 0 0 4 &gic0 0 0 0 19 4>; /* INTD */
389 };
390
391 pem1: pci@87e0c1000000 {
392 compatible = "cavium,pci-host-thunder-pem";
393 device_type = "pci";
394 msi-parent = <&its>;
395 msi-map = <0 &its 0 0x10000>;
396 bus-range = <0x57 0x8f>;
397 #size-cells = <2>;
398 #address-cells = <3>;
399 #stream-id-cells = <1>;
400 dma-coherent;
401 reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */
402 <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */
403 ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */
404 <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */
405 <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */
406 <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */
407
408 #interrupt-cells = <1>;
409 interrupt-map-mask = <0 0 0 7>;
410 interrupt-map = <0 0 0 1 &gic0 0 0 0 20 4>, /* INTA */
411 <0 0 0 2 &gic0 0 0 0 21 4>, /* INTB */
412 <0 0 0 3 &gic0 0 0 0 22 4>, /* INTC */
413 <0 0 0 4 &gic0 0 0 0 23 4>; /* INTD */
414 };
415
416 pem2: pci@87e0c2000000 {
417 compatible = "cavium,pci-host-thunder-pem";
418 device_type = "pci";
419 msi-parent = <&its>;
420 msi-map = <0 &its 0 0x10000>;
421 bus-range = <0x8f 0xc7>;
422 #size-cells = <2>;
423 #address-cells = <3>;
424 #stream-id-cells = <1>;
425 dma-coherent;
426 reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */
427 <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */
428 ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */
429 <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */
430 <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
431 <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */
432
433 #interrupt-cells = <1>;
434 interrupt-map-mask = <0 0 0 7>;
435 interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */
436 <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */
437 <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */
438 <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */
439 };
440
441 tdm: tdm@d,0 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 compatible = "cavium,thunder-8190-tdm";
445 reg = <0x6800 0 0 0>; /* DEVFN = 0x68 (d:0) */
446 clocks = <&sclk>;
447 };
448 };
449
450 aliases {
451 serial0 = &uaa0;
452 serial1 = &uaa1;
453 i2c0 = &i2c_9_0;
454 i2c1 = &i2c_9_1;
455 spi0 = &spi_7_0;
456 };
457
458 chosen {
459 stdout-path = "serial0:115200n8";
460 };
461
462
463 memory@0 {
464 device_type = "memory";
465 reg = <0x0 0x01400000 0x0 0x7EC00000>;
466 /* socket 0 */
467 numa-node-id = <0>;
468 };
469};
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-18 03:02:24 +0000