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author | Adrian Mangeac <Adrian.Mangeac@enea.com> | 2019-07-25 13:21:08 +0200 |
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committer | Adrian Mangeac <Adrian.Mangeac@enea.com> | 2019-07-26 11:31:08 +0200 |
commit | 28762038681c9158829c7586d6564446ef667c11 (patch) | |
tree | 1cfb481192a30e8091795d5116c29b656767f240 | |
parent | 3d96360e194421014d12c5f4e42d13574f2d4fe4 (diff) | |
download | meta-enea-bsp-arm-28762038681c9158829c7586d6564446ef667c11.tar.gz |
fpgautil: Add README file
Change-Id: Ib887c7633aa3273a4afdab01585fe5cea3ca004d
Signed-off-by: Adrian Mangeac <Adrian.Mangeac@enea.com>
-rw-r--r-- | recipes-apps/fpgautil/README | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/recipes-apps/fpgautil/README b/recipes-apps/fpgautil/README new file mode 100644 index 0000000..10ee047 --- /dev/null +++ b/recipes-apps/fpgautil/README | |||
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1 | The fpgautil command line tool provides an easy-to-use interface for FPGA | ||
2 | management. It allows the loading of fpga via overlay or through sysfs | ||
3 | interface, as well as reading fpga configurations using the Xilinx zynqMP fpga | ||
4 | manager. | ||
5 | |||
6 | Usage: fpgautil -b <bin file path> -o <dtbo file path> | ||
7 | |||
8 | Options: -b <binfile> (Bin file path) | ||
9 | -o <dtbofile> (DTBO file path) | ||
10 | -f <flags> Optional: <Bitstream type flags> | ||
11 | f := <Full | Partial > | ||
12 | Default: <Full> | ||
13 | -s <secure flags> Optional: <Secure flags> | ||
14 | s := <AuthDDR | AuthOCM | EnUsrKey | EnDevKey | AuthEnUsrKeyDDR | | ||
15 | AuthEnUsrKeyOCM | AuthEnDevKeyDDR | AuthEnDevKeyOCM> | ||
16 | -k <AesKey> Optional: <AES User Key> | ||
17 | -r <Readback> Optional: <file name> | ||
18 | Default: By default Read back contents will be stored in readback.bin | ||
19 | file | ||
20 | -t Optional: <Readback Type> | ||
21 | 0 - Configuration Register readback | ||
22 | 1 - Configuration Data Frames readback | ||
23 | Default: 0 (Configuration register readback) | ||
24 | -R Optional: Remove overlay from a live tree | ||
25 | |||
26 | Examples: | ||
27 | (Load Full bitstream using Overlay) | ||
28 | fpgautil -b top.bit.bin -o can.dtbo | ||
29 | (Load Partial bitstream through the sysfs interface) | ||
30 | fpgautil -b top.bit.bin -f Partial | ||
31 | (Load Authenticated bitstream through the sysfs interface) | ||
32 | fpgautil -b top.bit.bin -f Full -s AuthDDR | ||
33 | (Load Parital Encrypted Userkey bitstream using Overlay) | ||
34 | fpgautil -b top.bit.bin -o pl.dtbo -f Partial -s EnUsrKey -k <32byte | ||
35 | key value> | ||
36 | |||
37 | NOTE: | ||
38 | A binary file built for testing purposes can be downloaded from the | ||
39 | following location: | ||
40 | http://linux.enea.com/EneaLinux8.0/Xilinx-utils/fpga.bin.tar.bz2 | ||
41 | |||
42 | In order to load the fpga with the example file, do the following: | ||
43 | 1. Extract the binary file under /lib/firmware rootfs folder | ||
44 | $ tar -xpf system.bin.tar.bz2 -C <rootfs_nfs_path>/lib/firmware | ||
45 | |||
46 | 2. (Re)Boot the target | ||
47 | |||
48 | 3. Load the binary file | ||
49 | $ fpgautil -b /lib/firmware/system.bin | ||
50 | |||
51 | [ 39.243008] fpga_manager fpga0: writing system.bin to Xilinx ZynqMP FPGA | ||
52 | Manager | ||
53 | Time taken to load BIN is 15500.000000 Milli Seconds | ||
54 | BIN FILE loaded through zynqMP FPGA manager successfully | ||