From 59773576b7adb3129cf77d19442b5a83937b3c84 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Thu, 21 Sep 2017 15:17:57 -0700 Subject: clang/llvm: Backport aarch64 fix for bug 34674 Signed-off-by: Khem Raj --- ...4-Fix-bug-in-store-of-vector-0-DAGCombine.patch | 142 +++++++++++++++++++++ recipes-devtools/clang/common.inc | 1 + 2 files changed, 143 insertions(+) create mode 100644 recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch (limited to 'recipes-devtools/clang') diff --git a/recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch b/recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch new file mode 100644 index 0000000..d45c2e1 --- /dev/null +++ b/recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch @@ -0,0 +1,142 @@ +From 7946cf61b738bcad220710feb6208912e6a105e6 Mon Sep 17 00:00:00 2001 +From: Geoff Berry +Date: Thu, 21 Sep 2017 21:10:06 +0000 +Subject: [PATCH] [AArch64] Fix bug in store of vector 0 DAGCombine. + +Summary: +Avoid using XZR/WZR directly as operands to split stores of zero +vectors. Doing so can lead to the XZR/WZR being used by an instruction +that doesn't allow it (e.g. add). + +Fixes bug 34674. + +Reviewers: t.p.northover, efriedma, MatzeB + +Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls + +Differential Revision: https://reviews.llvm.org/D38146 + +git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313916 91177308-0d34-0410-b5e6-96231b3b80d8 +--- + lib/Target/AArch64/AArch64ISelLowering.cpp | 19 ++++++++++++++----- + test/CodeGen/AArch64/arm64-memset-inline.ll | 4 ++-- + test/CodeGen/AArch64/fastcc.ll | 12 +++++++++--- + test/CodeGen/AArch64/ldst-opt.ll | 15 ++++++++++++++- + 4 files changed, 39 insertions(+), 11 deletions(-) + +diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp +index cfee36d3477..ff9bf2a7daf 100644 +--- a/lib/Target/AArch64/AArch64ISelLowering.cpp ++++ b/lib/Target/AArch64/AArch64ISelLowering.cpp +@@ -9448,11 +9448,20 @@ static SDValue replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) { + return SDValue(); + } + +- // Use WZR/XZR here to prevent DAGCombiner::MergeConsecutiveStores from +- // undoing this transformation. +- SDValue SplatVal = VT.getVectorElementType().getSizeInBits() == 32 +- ? DAG.getRegister(AArch64::WZR, MVT::i32) +- : DAG.getRegister(AArch64::XZR, MVT::i64); ++ // Use a CopyFromReg WZR/XZR here to prevent ++ // DAGCombiner::MergeConsecutiveStores from undoing this transformation. ++ SDLoc DL(&St); ++ unsigned ZeroReg; ++ EVT ZeroVT; ++ if (VT.getVectorElementType().getSizeInBits() == 32) { ++ ZeroReg = AArch64::WZR; ++ ZeroVT = MVT::i32; ++ } else { ++ ZeroReg = AArch64::XZR; ++ ZeroVT = MVT::i64; ++ } ++ SDValue SplatVal = ++ DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT); + return splitStoreSplat(DAG, St, SplatVal, NumVecElts); + } + +diff --git a/test/CodeGen/AArch64/arm64-memset-inline.ll b/test/CodeGen/AArch64/arm64-memset-inline.ll +index 384aaa8541d..8c872cc6150 100644 +--- a/test/CodeGen/AArch64/arm64-memset-inline.ll ++++ b/test/CodeGen/AArch64/arm64-memset-inline.ll +@@ -12,9 +12,9 @@ entry: + define void @t2() nounwind ssp { + entry: + ; CHECK-LABEL: t2: ++; CHECK: stp xzr, xzr, [sp, #16] + ; CHECK: strh wzr, [sp, #32] +-; CHECK: stp xzr, xzr, [sp, #8] +-; CHECK: str xzr, [sp, #24] ++; CHECK: str xzr, [sp, #8] + %buf = alloca [26 x i8], align 1 + %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 + call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false) +diff --git a/test/CodeGen/AArch64/fastcc.ll b/test/CodeGen/AArch64/fastcc.ll +index fcc852263b4..3ea6df5be49 100644 +--- a/test/CodeGen/AArch64/fastcc.ll ++++ b/test/CodeGen/AArch64/fastcc.ll +@@ -21,9 +21,11 @@ define fastcc void @func_stack0() { + call fastcc void @func_stack8([8 x i32] undef, i32 42) + ; CHECK: bl func_stack8 + ; CHECK-NOT: sub sp, sp, ++; CHECK-NOT: [sp, #{{[-0-9]+}}]! ++; CHECK-NOT: [sp], #{{[-0-9]+}} + + ; CHECK-TAIL: bl func_stack8 +-; CHECK-TAIL: sub sp, sp, #16 ++; CHECK-TAIL: stp xzr, xzr, [sp, #-16]! + + + call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9) +@@ -72,10 +74,12 @@ define fastcc void @func_stack8([8 x i32], i32 %stacked) { + call fastcc void @func_stack8([8 x i32] undef, i32 42) + ; CHECK: bl func_stack8 + ; CHECK-NOT: sub sp, sp, ++; CHECK-NOT: [sp, #{{[-0-9]+}}]! ++; CHECK-NOT: [sp], #{{[-0-9]+}} + + + ; CHECK-TAIL: bl func_stack8 +-; CHECK-TAIL: sub sp, sp, #16 ++; CHECK-TAIL: stp xzr, xzr, [sp, #-16]! + + + call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9) +@@ -116,9 +120,11 @@ define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) { + call fastcc void @func_stack8([8 x i32] undef, i32 42) + ; CHECK: bl func_stack8 + ; CHECK-NOT: sub sp, sp, ++; CHECK-NOT: [sp, #{{[-0-9]+}}]! ++; CHECK-NOT: [sp], #{{[-0-9]+}} + + ; CHECK-TAIL: bl func_stack8 +-; CHECK-TAIL: sub sp, sp, #16 ++; CHECK-TAIL: stp xzr, xzr, [sp, #-16]! + + + call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9) +diff --git a/test/CodeGen/AArch64/ldst-opt.ll b/test/CodeGen/AArch64/ldst-opt.ll +index 9307b6a3e47..e416dcb0f16 100644 +--- a/test/CodeGen/AArch64/ldst-opt.ll ++++ b/test/CodeGen/AArch64/ldst-opt.ll +@@ -1667,4 +1667,17 @@ entry: + ret void + } + +- ++; Check for bug 34674 where invalid add of xzr was being generated. ++; CHECK-LABEL: bug34674: ++; CHECK: // %entry ++; CHECK-NEXT: mov [[ZREG:x[0-9]+]], xzr ++; CHECK-DAG: stp [[ZREG]], [[ZREG]], [x0] ++; CHECK-DAG: add x{{[0-9]+}}, [[ZREG]], #1 ++define i64 @bug34674(<2 x i64>* %p) { ++entry: ++ store <2 x i64> zeroinitializer, <2 x i64>* %p ++ %p2 = bitcast <2 x i64>* %p to i64* ++ %ld = load i64, i64* %p2 ++ %add = add i64 %ld, 1 ++ ret i64 %add ++} +-- +2.14.1 + diff --git a/recipes-devtools/clang/common.inc b/recipes-devtools/clang/common.inc index 1108747..75df1b2 100644 --- a/recipes-devtools/clang/common.inc +++ b/recipes-devtools/clang/common.inc @@ -7,6 +7,7 @@ LLVMPATCHES = "\ file://0001-llvm-TargetLibraryInfo-Undefine-libc-functions-if-th.patch \ file://0002-llvm-allow-env-override-of-exe-path.patch \ file://0003-llvm-ARM-Use-correct-calling-convention-for-libm.patch \ + file://0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch \ " # Fallback to no-PIE if not set GCCPIE ??= "" -- cgit v1.2.3-54-g00ecf