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-rw-r--r--recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch142
1 files changed, 142 insertions, 0 deletions
diff --git a/recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch b/recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch
new file mode 100644
index 0000000..d45c2e1
--- /dev/null
+++ b/recipes-devtools/clang/clang/0004-llvm-AArch64-Fix-bug-in-store-of-vector-0-DAGCombine.patch
@@ -0,0 +1,142 @@
1From 7946cf61b738bcad220710feb6208912e6a105e6 Mon Sep 17 00:00:00 2001
2From: Geoff Berry <gberry@codeaurora.org>
3Date: Thu, 21 Sep 2017 21:10:06 +0000
4Subject: [PATCH] [AArch64] Fix bug in store of vector 0 DAGCombine.
5
6Summary:
7Avoid using XZR/WZR directly as operands to split stores of zero
8vectors. Doing so can lead to the XZR/WZR being used by an instruction
9that doesn't allow it (e.g. add).
10
11Fixes bug 34674.
12
13Reviewers: t.p.northover, efriedma, MatzeB
14
15Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls
16
17Differential Revision: https://reviews.llvm.org/D38146
18
19git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313916 91177308-0d34-0410-b5e6-96231b3b80d8
20---
21 lib/Target/AArch64/AArch64ISelLowering.cpp | 19 ++++++++++++++-----
22 test/CodeGen/AArch64/arm64-memset-inline.ll | 4 ++--
23 test/CodeGen/AArch64/fastcc.ll | 12 +++++++++---
24 test/CodeGen/AArch64/ldst-opt.ll | 15 ++++++++++++++-
25 4 files changed, 39 insertions(+), 11 deletions(-)
26
27diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
28index cfee36d3477..ff9bf2a7daf 100644
29--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
30+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
31@@ -9448,11 +9448,20 @@ static SDValue replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) {
32 return SDValue();
33 }
34
35- // Use WZR/XZR here to prevent DAGCombiner::MergeConsecutiveStores from
36- // undoing this transformation.
37- SDValue SplatVal = VT.getVectorElementType().getSizeInBits() == 32
38- ? DAG.getRegister(AArch64::WZR, MVT::i32)
39- : DAG.getRegister(AArch64::XZR, MVT::i64);
40+ // Use a CopyFromReg WZR/XZR here to prevent
41+ // DAGCombiner::MergeConsecutiveStores from undoing this transformation.
42+ SDLoc DL(&St);
43+ unsigned ZeroReg;
44+ EVT ZeroVT;
45+ if (VT.getVectorElementType().getSizeInBits() == 32) {
46+ ZeroReg = AArch64::WZR;
47+ ZeroVT = MVT::i32;
48+ } else {
49+ ZeroReg = AArch64::XZR;
50+ ZeroVT = MVT::i64;
51+ }
52+ SDValue SplatVal =
53+ DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
54 return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
55 }
56
57diff --git a/test/CodeGen/AArch64/arm64-memset-inline.ll b/test/CodeGen/AArch64/arm64-memset-inline.ll
58index 384aaa8541d..8c872cc6150 100644
59--- a/test/CodeGen/AArch64/arm64-memset-inline.ll
60+++ b/test/CodeGen/AArch64/arm64-memset-inline.ll
61@@ -12,9 +12,9 @@ entry:
62 define void @t2() nounwind ssp {
63 entry:
64 ; CHECK-LABEL: t2:
65+; CHECK: stp xzr, xzr, [sp, #16]
66 ; CHECK: strh wzr, [sp, #32]
67-; CHECK: stp xzr, xzr, [sp, #8]
68-; CHECK: str xzr, [sp, #24]
69+; CHECK: str xzr, [sp, #8]
70 %buf = alloca [26 x i8], align 1
71 %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
72 call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
73diff --git a/test/CodeGen/AArch64/fastcc.ll b/test/CodeGen/AArch64/fastcc.ll
74index fcc852263b4..3ea6df5be49 100644
75--- a/test/CodeGen/AArch64/fastcc.ll
76+++ b/test/CodeGen/AArch64/fastcc.ll
77@@ -21,9 +21,11 @@ define fastcc void @func_stack0() {
78 call fastcc void @func_stack8([8 x i32] undef, i32 42)
79 ; CHECK: bl func_stack8
80 ; CHECK-NOT: sub sp, sp,
81+; CHECK-NOT: [sp, #{{[-0-9]+}}]!
82+; CHECK-NOT: [sp], #{{[-0-9]+}}
83
84 ; CHECK-TAIL: bl func_stack8
85-; CHECK-TAIL: sub sp, sp, #16
86+; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
87
88
89 call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
90@@ -72,10 +74,12 @@ define fastcc void @func_stack8([8 x i32], i32 %stacked) {
91 call fastcc void @func_stack8([8 x i32] undef, i32 42)
92 ; CHECK: bl func_stack8
93 ; CHECK-NOT: sub sp, sp,
94+; CHECK-NOT: [sp, #{{[-0-9]+}}]!
95+; CHECK-NOT: [sp], #{{[-0-9]+}}
96
97
98 ; CHECK-TAIL: bl func_stack8
99-; CHECK-TAIL: sub sp, sp, #16
100+; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
101
102
103 call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
104@@ -116,9 +120,11 @@ define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
105 call fastcc void @func_stack8([8 x i32] undef, i32 42)
106 ; CHECK: bl func_stack8
107 ; CHECK-NOT: sub sp, sp,
108+; CHECK-NOT: [sp, #{{[-0-9]+}}]!
109+; CHECK-NOT: [sp], #{{[-0-9]+}}
110
111 ; CHECK-TAIL: bl func_stack8
112-; CHECK-TAIL: sub sp, sp, #16
113+; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
114
115
116 call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
117diff --git a/test/CodeGen/AArch64/ldst-opt.ll b/test/CodeGen/AArch64/ldst-opt.ll
118index 9307b6a3e47..e416dcb0f16 100644
119--- a/test/CodeGen/AArch64/ldst-opt.ll
120+++ b/test/CodeGen/AArch64/ldst-opt.ll
121@@ -1667,4 +1667,17 @@ entry:
122 ret void
123 }
124
125-
126+; Check for bug 34674 where invalid add of xzr was being generated.
127+; CHECK-LABEL: bug34674:
128+; CHECK: // %entry
129+; CHECK-NEXT: mov [[ZREG:x[0-9]+]], xzr
130+; CHECK-DAG: stp [[ZREG]], [[ZREG]], [x0]
131+; CHECK-DAG: add x{{[0-9]+}}, [[ZREG]], #1
132+define i64 @bug34674(<2 x i64>* %p) {
133+entry:
134+ store <2 x i64> zeroinitializer, <2 x i64>* %p
135+ %p2 = bitcast <2 x i64>* %p to i64*
136+ %ld = load i64, i64* %p2
137+ %add = add i64 %ld, 1
138+ ret i64 %add
139+}
140--
1412.14.1
142
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