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-rw-r--r--recipes-devtools/clang/clang/0023-RISCV-Add-support-for-floating-point-registers-in-in.patch103
-rw-r--r--recipes-devtools/clang/common.inc1
2 files changed, 104 insertions, 0 deletions
diff --git a/recipes-devtools/clang/clang/0023-RISCV-Add-support-for-floating-point-registers-in-in.patch b/recipes-devtools/clang/clang/0023-RISCV-Add-support-for-floating-point-registers-in-in.patch
new file mode 100644
index 0000000..040980b
--- /dev/null
+++ b/recipes-devtools/clang/clang/0023-RISCV-Add-support-for-floating-point-registers-in-in.patch
@@ -0,0 +1,103 @@
1From 373a9051a614acd24d6fb1257001414aa50e95f2 Mon Sep 17 00:00:00 2001
2From: Simon Cook <simon.cook@embecosm.com>
3Date: Wed, 31 Jul 2019 09:12:00 +0000
4Subject: [PATCH] [RISCV] Add support for floating point registers in inlineasm
5
6This adds support for parsing/emitting in IR the floating-point RISC-V
7registers in inline assembly clobber lists.
8
9Differential Revision: https://reviews.llvm.org/D64737
10
11llvm-svn: 367399
12---
13 clang/lib/Basic/Targets/RISCV.cpp | 33 ++++++++++++++++++++++---------
14 clang/test/Sema/riscv-asm.c | 28 ++++++++++++++++++++++++++
15 2 files changed, 52 insertions(+), 9 deletions(-)
16 create mode 100644 clang/test/Sema/riscv-asm.c
17
18diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
19index 930b825e94d..d1166d90df4 100644
20--- a/clang/lib/Basic/Targets/RISCV.cpp
21+++ b/clang/lib/Basic/Targets/RISCV.cpp
22@@ -19,23 +19,38 @@ using namespace clang::targets;
23
24 ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
25 static const char *const GCCRegNames[] = {
26+ // Integer registers
27 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
28 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
29 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
30- "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"};
31+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
32+
33+ // Floating point registers
34+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
35+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
36+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
37+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
38 return llvm::makeArrayRef(GCCRegNames);
39 }
40
41 ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
42 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
43- {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
44- {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
45- {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
46- {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
47- {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
48- {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
49- {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
50- {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"}};
51+ {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
52+ {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
53+ {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
54+ {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
55+ {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
56+ {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
57+ {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
58+ {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"},
59+ {{"ft0"}, "f0"}, {{"ft1"}, "f1"}, {{"ft2"}, "f2"}, {{"ft3"}, "f3"},
60+ {{"ft4"}, "f4"}, {{"ft5"}, "f5"}, {{"ft6"}, "f6"}, {{"ft7"}, "f7"},
61+ {{"fs0"}, "f8"}, {{"fs1"}, "f9"}, {{"fa0"}, "f10"}, {{"fa1"}, "f11"},
62+ {{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"}, {{"fa5"}, "f15"},
63+ {{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"}, "f18"}, {{"fs3"}, "f19"},
64+ {{"fs4"}, "f20"}, {{"fs5"}, "f21"}, {{"fs6"}, "f22"}, {{"fs7"}, "f23"},
65+ {{"fs8"}, "f24"}, {{"fs9"}, "f25"}, {{"fs10"}, "f26"}, {{"fs11"}, "f27"},
66+ {{"ft8"}, "f28"}, {{"ft9"}, "f29"}, {{"ft10"}, "f30"}, {{"ft11"}, "f31"}};
67 return llvm::makeArrayRef(GCCRegAliases);
68 }
69
70diff --git a/clang/test/Sema/riscv-asm.c b/clang/test/Sema/riscv-asm.c
71new file mode 100644
72index 00000000000..82664c01317
73--- /dev/null
74+++ b/clang/test/Sema/riscv-asm.c
75@@ -0,0 +1,28 @@
76+// RUN: %clang_cc1 %s -triple riscv32 -verify -fsyntax-only
77+// RUN: %clang_cc1 %s -triple riscv64 -verify -fsyntax-only
78+
79+// expected-no-diagnostics
80+
81+void i (void) {
82+ asm volatile ("" ::: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7");
83+ asm volatile ("" ::: "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15");
84+ asm volatile ("" ::: "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23");
85+ asm volatile ("" ::: "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31");
86+
87+ asm volatile ("" ::: "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2");
88+ asm volatile ("" ::: "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5");
89+ asm volatile ("" ::: "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7");
90+ asm volatile ("" ::: "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6");
91+}
92+
93+void f (void) {
94+ asm volatile ("" ::: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7");
95+ asm volatile ("" ::: "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
96+ asm volatile ("" ::: "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23");
97+ asm volatile ("" ::: "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
98+
99+ asm volatile ("" ::: "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7");
100+ asm volatile ("" ::: "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5");
101+ asm volatile ("" ::: "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7");
102+ asm volatile ("" ::: "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11");
103+}
diff --git a/recipes-devtools/clang/common.inc b/recipes-devtools/clang/common.inc
index 9adeac8..0e5816c 100644
--- a/recipes-devtools/clang/common.inc
+++ b/recipes-devtools/clang/common.inc
@@ -30,6 +30,7 @@ SRC_URI = "\
30 file://0020-clang-default-to-lp64d-ABI-and-rv64gc-ISA.patch \ 30 file://0020-clang-default-to-lp64d-ABI-and-rv64gc-ISA.patch \
31 file://0021-lldb-Do-not-look-for-interpreter.patch \ 31 file://0021-lldb-Do-not-look-for-interpreter.patch \
32 file://0022-Driver-Prioritize-SYSROOT-usr-include-over-RESOURCE_.patch \ 32 file://0022-Driver-Prioritize-SYSROOT-usr-include-over-RESOURCE_.patch \
33 file://0023-RISCV-Add-support-for-floating-point-registers-in-in.patch \
33" 34"
34 35
35# Fallback to no-PIE if not set 36# Fallback to no-PIE if not set
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-16 11:39:15 +0000