1 files changed, 32 insertions, 0 deletions

diff --git a/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch
new file mode 100644
index 0000000..54fa812
--- /dev/null
+++ b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch
@@ -0,0 +1,32 @@
+From 8569e08a1a4b3bd810f60083058053a39b27534e Mon Sep 17 00:00:00 2001
+From: Chee Hong Ang <chee.hong.ang@intel.com>
+Date: Sat, 18 May 2019 16:42:10 +0800
+Subject: [PATCH 09/12] ARM: socfpga: Stratix10: Fix el3_exception_vectors
+ relocation issue
+
+New toolchain has issue relocating the 32-bit pointer to address of
+el3_exception_vectors in secure section. This patch make sure the
+address pointer to the secure section is 64-bit.
+
+Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
+---
+ arch/arm/mach-socfpga/lowlevel_init.S | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S
+index 832785a682..342d5190b5 100644
+--- a/arch/arm/mach-socfpga/lowlevel_init.S
++++ b/arch/arm/mach-socfpga/lowlevel_init.S
+@@ -12,8 +12,7 @@
+ #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI)
+ .align 3
+ _el3_exception_vectors:
+-       .word el3_exception_vectors;
+-       .word 0
++       .quad el3_exception_vectors;
+ #endif
+ 
+ ENTRY(lowlevel_init)
+-- 
+2.21.0
+