diff options
author | Dalon Westergreen <dwesterg@gmail.com> | 2019-05-22 12:13:15 -0700 |
---|---|---|
committer | Khem Raj <raj.khem@gmail.com> | 2019-06-10 10:09:43 -0700 |
commit | be96d3602f111c0332b8cbb0e0e975adaf817060 (patch) | |
tree | 8df0fc5610d83c67e392674007c39d7ce67ebe1e /recipes-bsp/u-boot | |
parent | 3b2e53a1c5cbfcffb02eeee53aa6cbd97f8e7439 (diff) | |
download | meta-altera-be96d3602f111c0332b8cbb0e0e975adaf817060.tar.gz |
Add 2019.07 u-boot
Initial mainline support for Arria10 and Stratix10. Stratix10
still requires some patches, also included in this recipe.
Arria10
-> uboot support is in mainline.
Stratix10
-> uboot mainlining is almost complete, add missing
patches.
-> Known issue at this time is that reset in u-boot
does not appear functional.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Diffstat (limited to 'recipes-bsp/u-boot')
14 files changed, 1613 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch new file mode 100644 index 0000000..e954ac0 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch | |||
@@ -0,0 +1,30 @@ | |||
1 | From 45dd1ac82881153c73bd4243cd20f3b13955ad21 Mon Sep 17 00:00:00 2001 | ||
2 | From: Chee Hong Ang <chee.hong.ang@intel.com> | ||
3 | Date: Sat, 11 May 2019 00:09:46 +0800 | ||
4 | Subject: [PATCH] ARM: socfpga: Stratix10: Disable CONFIG_PSCI_RESET | ||
5 | |||
6 | Avoid invoking 'SYSTEM_RESET' PSCI function because PSCI | ||
7 | function calls are not supported in u-boot running in EL3. | ||
8 | |||
9 | Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> | ||
10 | --- | ||
11 | arch/arm/cpu/armv8/Kconfig | 3 ++- | ||
12 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig | ||
15 | index 7405c3a4a1..409ee7ada0 100644 | ||
16 | --- a/arch/arm/cpu/armv8/Kconfig | ||
17 | +++ b/arch/arm/cpu/armv8/Kconfig | ||
18 | @@ -108,7 +108,8 @@ config PSCI_RESET | ||
19 | !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ | ||
20 | !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ | ||
21 | !TARGET_LX2160AQDS && \ | ||
22 | - !ARCH_UNIPHIER && !TARGET_S32V234EVB | ||
23 | + !ARCH_UNIPHIER && !TARGET_S32V234EVB && \ | ||
24 | + !TARGET_SOCFPGA_STRATIX10 | ||
25 | help | ||
26 | Most armv8 systems have PSCI support enabled in EL3, either through | ||
27 | ARM Trusted Firmware or other firmware. | ||
28 | -- | ||
29 | 2.13.0 | ||
30 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch new file mode 100644 index 0000000..a4b7857 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch | |||
@@ -0,0 +1,59 @@ | |||
1 | From 97f599b2a7b34d17067b4ccf6c468cdcc6805349 Mon Sep 17 00:00:00 2001 | ||
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | ||
3 | Date: Mon, 29 Apr 2019 23:35:30 -0700 | ||
4 | Subject: [PATCH 01/12] ARM: socfpga: stratix10: Enable PSCI system reset | ||
5 | |||
6 | Enable psci_system_reset support for Stratix10. This PSCI function | ||
7 | will eventually trigger the mailbox HPS_REBOOT to SDM. | ||
8 | |||
9 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | ||
10 | --- | ||
11 | arch/arm/mach-socfpga/Makefile | 3 +++ | ||
12 | arch/arm/mach-socfpga/psci.c | 21 +++++++++++++++++++++ | ||
13 | 2 files changed, 24 insertions(+) | ||
14 | create mode 100644 arch/arm/mach-socfpga/psci.c | ||
15 | |||
16 | diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile | ||
17 | index e66720447f..f77b229a38 100644 | ||
18 | --- a/arch/arm/mach-socfpga/Makefile | ||
19 | +++ b/arch/arm/mach-socfpga/Makefile | ||
20 | @@ -38,6 +38,9 @@ obj-y += system_manager_s10.o | ||
21 | obj-y += timer_s10.o | ||
22 | obj-y += wrap_pinmux_config_s10.o | ||
23 | obj-y += wrap_pll_config_s10.o | ||
24 | +ifndef CONFIG_SPL_BUILD | ||
25 | +obj-$(CONFIG_ARMV8_PSCI) += psci.o | ||
26 | +endif | ||
27 | endif | ||
28 | |||
29 | ifdef CONFIG_SPL_BUILD | ||
30 | diff --git a/arch/arm/mach-socfpga/psci.c b/arch/arm/mach-socfpga/psci.c | ||
31 | new file mode 100644 | ||
32 | index 0000000000..9ef393110d | ||
33 | --- /dev/null | ||
34 | +++ b/arch/arm/mach-socfpga/psci.c | ||
35 | @@ -0,0 +1,21 @@ | ||
36 | +/* | ||
37 | + * Copyright (C) 2017 Intel Corporation <www.intel.com> | ||
38 | + * | ||
39 | + * SPDX-License-Identifier: GPL-2.0 | ||
40 | + */ | ||
41 | + | ||
42 | +#include <common.h> | ||
43 | +#include <asm/io.h> | ||
44 | +#include <asm/psci.h> | ||
45 | +#include <errno.h> | ||
46 | +#include <asm/arch/mailbox_s10.h> | ||
47 | +#include <asm/secure.h> | ||
48 | + | ||
49 | +void __noreturn __secure psci_system_reset(void) | ||
50 | +{ | ||
51 | + mbox_send_cmd_psci(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, | ||
52 | + MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL); | ||
53 | + | ||
54 | + while (1) | ||
55 | + ; | ||
56 | +} | ||
57 | -- | ||
58 | 2.21.0 | ||
59 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch b/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch new file mode 100644 index 0000000..ebf6fe7 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch | |||
@@ -0,0 +1,67 @@ | |||
1 | From 257cff780ec1a50600a77cf361df27746801d684 Mon Sep 17 00:00:00 2001 | ||
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | ||
3 | Date: Mon, 14 Jan 2019 01:07:50 -0800 | ||
4 | Subject: [PATCH 02/12] ARM: socfpga: stratix10: Enable PSCI CPU_ON | ||
5 | |||
6 | Enable psci_cpu_on support for Stratix10. This PSCI function | ||
7 | will pass the cpu release address for CPU1-CPU3. Then send event | ||
8 | signal shall be triggered to get these CPUs running Linux code. | ||
9 | |||
10 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | ||
11 | --- | ||
12 | arch/arm/mach-socfpga/psci.c | 35 +++++++++++++++++++++++++++++++++++ | ||
13 | 1 file changed, 35 insertions(+) | ||
14 | |||
15 | diff --git a/arch/arm/mach-socfpga/psci.c b/arch/arm/mach-socfpga/psci.c | ||
16 | index 9ef393110d..0af3eb195c 100644 | ||
17 | --- a/arch/arm/mach-socfpga/psci.c | ||
18 | +++ b/arch/arm/mach-socfpga/psci.c | ||
19 | @@ -11,6 +11,9 @@ | ||
20 | #include <asm/arch/mailbox_s10.h> | ||
21 | #include <asm/secure.h> | ||
22 | |||
23 | +static u64 psci_cpu_on_64_cpuid __secure_data; | ||
24 | +static u64 psci_cpu_on_64_entry_point __secure_data; | ||
25 | + | ||
26 | void __noreturn __secure psci_system_reset(void) | ||
27 | { | ||
28 | mbox_send_cmd_psci(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, | ||
29 | @@ -19,3 +22,35 @@ void __noreturn __secure psci_system_reset(void) | ||
30 | while (1) | ||
31 | ; | ||
32 | } | ||
33 | + | ||
34 | +/* This function will handle multiple core release based PSCI */ | ||
35 | +void __secure psci_cpu_on_64_mpidr(void) | ||
36 | +{ | ||
37 | + asm volatile( | ||
38 | + ".align 5 \n" | ||
39 | + "1: wfe \n" | ||
40 | + " ldr x0, [%0] \n" | ||
41 | + " ldr x1, [%1] \n" | ||
42 | + " mrs x2, mpidr_el1 \n" | ||
43 | + " and x2, x2, #0xff \n" | ||
44 | + " cmp x0, x2 \n" | ||
45 | + " b.ne 1b \n" | ||
46 | + " br x1 \n" | ||
47 | + : : "r"(&psci_cpu_on_64_cpuid), "r"(&psci_cpu_on_64_entry_point) | ||
48 | + : "x0", "x1", "x2", "memory", "cc"); | ||
49 | +} | ||
50 | + | ||
51 | +int __secure psci_cpu_on_64(u32 function_id, u64 cpuid, u64 entry_point) | ||
52 | +{ | ||
53 | + /* Releases all secondary CPUs to jump into psci_cpu_on_64_mpidr */ | ||
54 | + writeq(0, &psci_cpu_on_64_cpuid); | ||
55 | + writeq(0, &psci_cpu_on_64_entry_point); | ||
56 | + writeq((u64)&psci_cpu_on_64_mpidr, CPU_RELEASE_ADDR); | ||
57 | + | ||
58 | + /* to store in global so psci_cpu_on_64_mpidr function can refer */ | ||
59 | + writeq(entry_point, &psci_cpu_on_64_entry_point); | ||
60 | + writeq(cpuid, &psci_cpu_on_64_cpuid); | ||
61 | + asm volatile("sev"); | ||
62 | + | ||
63 | + return ARM_PSCI_RET_SUCCESS; | ||
64 | +} | ||
65 | -- | ||
66 | 2.21.0 | ||
67 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch b/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch new file mode 100644 index 0000000..ed60cc0 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch | |||
@@ -0,0 +1,45 @@ | |||
1 | From 504f8bd14f703bfb2ffd5dccac7126d5fd22e0d1 Mon Sep 17 00:00:00 2001 | ||
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | ||
3 | Date: Mon, 29 Apr 2019 23:18:38 -0700 | ||
4 | Subject: [PATCH 03/12] ARM: socfpga: stratix10: Enable PSCI support for | ||
5 | Stratix 10 | ||
6 | |||
7 | The address of PSCI text, data and stack sections start at | ||
8 | 0x00001000 (SDRAM). | ||
9 | |||
10 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | ||
11 | --- | ||
12 | arch/arm/mach-socfpga/Kconfig | 9 ++++++++- | ||
13 | 1 file changed, 8 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig | ||
16 | index 48f02f08d4..755bab5dd2 100644 | ||
17 | --- a/arch/arm/mach-socfpga/Kconfig | ||
18 | +++ b/arch/arm/mach-socfpga/Kconfig | ||
19 | @@ -12,6 +12,12 @@ config SPL_SYS_MALLOC_F_LEN | ||
20 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE | ||
21 | default 0xa2 | ||
22 | |||
23 | +config ARMV8_SECURE_BASE | ||
24 | + default 0x00001000 if TARGET_SOCFPGA_STRATIX10 | ||
25 | + | ||
26 | +config SYS_HAS_ARMV8_SECURE_BASE | ||
27 | + default y if TARGET_SOCFPGA_STRATIX10 | ||
28 | + | ||
29 | config SYS_MALLOC_F_LEN | ||
30 | default 0x2000 if TARGET_SOCFPGA_ARRIA10 | ||
31 | default 0x2000 if TARGET_SOCFPGA_GEN5 | ||
32 | @@ -56,8 +62,9 @@ config TARGET_SOCFPGA_GEN5 | ||
33 | config TARGET_SOCFPGA_STRATIX10 | ||
34 | bool | ||
35 | select ARMV8_MULTIENTRY | ||
36 | + select ARMV8_PSCI | ||
37 | + select ARMV8_SEC_FIRMWARE_SUPPORT | ||
38 | select ARMV8_SET_SMPEN | ||
39 | - select ARMV8_SPIN_TABLE | ||
40 | select FPGA_STRATIX10 | ||
41 | |||
42 | choice | ||
43 | -- | ||
44 | 2.21.0 | ||
45 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch new file mode 100644 index 0000000..7d30706 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch | |||
@@ -0,0 +1,153 @@ | |||
1 | From a859bc214aa913be022a7aa8f03723079a325b07 Mon Sep 17 00:00:00 2001 | ||
2 | From: Chee Hong Ang <chee.hong.ang@intel.com> | ||
3 | Date: Fri, 20 Apr 2018 18:28:07 +0800 | ||
4 | Subject: [PATCH 04/12] ARM: socfpga: stratix10: Enable SMC/PSCI calls from | ||
5 | slave CPUs | ||
6 | |||
7 | Before this patch, only master CPU (CPU0) is able to | ||
8 | make SMC/PSCI calls to EL3 exception handler. This patch | ||
9 | allow SMC/PSCI calls from slave CPUs (CPU1/2/3) as well. | ||
10 | |||
11 | Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> | ||
12 | --- | ||
13 | arch/arm/mach-socfpga/Makefile | 1 + | ||
14 | arch/arm/mach-socfpga/lowlevel_init.S | 97 +++++++++++++++++++++++ | ||
15 | include/configs/socfpga_stratix10_socdk.h | 6 ++ | ||
16 | 3 files changed, 104 insertions(+) | ||
17 | create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S | ||
18 | |||
19 | diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile | ||
20 | index f77b229a38..d34198d159 100644 | ||
21 | --- a/arch/arm/mach-socfpga/Makefile | ||
22 | +++ b/arch/arm/mach-socfpga/Makefile | ||
23 | @@ -29,6 +29,7 @@ obj-y += reset_manager_arria10.o | ||
24 | endif | ||
25 | |||
26 | ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 | ||
27 | +obj-y += lowlevel_init.o | ||
28 | obj-y += clock_manager_s10.o | ||
29 | obj-y += mailbox_s10.o | ||
30 | obj-y += misc_s10.o | ||
31 | diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S | ||
32 | new file mode 100644 | ||
33 | index 0000000000..832785a682 | ||
34 | --- /dev/null | ||
35 | +++ b/arch/arm/mach-socfpga/lowlevel_init.S | ||
36 | @@ -0,0 +1,97 @@ | ||
37 | +/* | ||
38 | + * Copyright (C) 2018 Intel Corporation. All rights reserved | ||
39 | + * | ||
40 | + * SPDX-License-Identifier: GPL-2.0 | ||
41 | + */ | ||
42 | + | ||
43 | +#include <asm-offsets.h> | ||
44 | +#include <config.h> | ||
45 | +#include <linux/linkage.h> | ||
46 | +#include <asm/macro.h> | ||
47 | + | ||
48 | +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) | ||
49 | +.align 3 | ||
50 | +_el3_exception_vectors: | ||
51 | + .word el3_exception_vectors; | ||
52 | + .word 0 | ||
53 | +#endif | ||
54 | + | ||
55 | +ENTRY(lowlevel_init) | ||
56 | + mov x29, lr /* Save LR */ | ||
57 | + | ||
58 | +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) | ||
59 | + branch_if_slave x0, 1f | ||
60 | + ldr x0, =GICD_BASE | ||
61 | + bl gic_init_secure | ||
62 | +1: | ||
63 | +#if defined(CONFIG_GICV3) | ||
64 | + ldr x0, =GICR_BASE | ||
65 | + bl gic_init_secure_percpu | ||
66 | +#elif defined(CONFIG_GICV2) | ||
67 | + ldr x0, =GICD_BASE | ||
68 | + ldr x1, =GICC_BASE | ||
69 | + bl gic_init_secure_percpu | ||
70 | +#endif | ||
71 | +#endif | ||
72 | + | ||
73 | +#ifdef CONFIG_ARMV8_MULTIENTRY | ||
74 | + branch_if_master x0, x1, 2f | ||
75 | + | ||
76 | + /* | ||
77 | + * Slave should wait for master clearing spin table. | ||
78 | + * This sync prevent slaves observing incorrect | ||
79 | + * value of spin table and jumping to wrong place. | ||
80 | + */ | ||
81 | +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) | ||
82 | +#ifdef CONFIG_GICV2 | ||
83 | + ldr x0, =GICC_BASE | ||
84 | +#endif | ||
85 | + bl gic_wait_for_interrupt | ||
86 | +#endif | ||
87 | + | ||
88 | +#ifdef CONFIG_SPL_BUILD | ||
89 | + /* | ||
90 | + * Read the u-boot's PSCI exception handler's vector base | ||
91 | + * address from the sysmgr.boot_scratch_cold6 & 7 and update | ||
92 | + * their VBAR_EL3 respectively. | ||
93 | + */ | ||
94 | +wait_vbar_el3: | ||
95 | + ldr x4, =VBAR_EL3_BASE_ADDR | ||
96 | + ldr x5, [x4] | ||
97 | + cbz x5, wait_vbar_el3 | ||
98 | + msr vbar_el3, x5 | ||
99 | +#endif | ||
100 | + /* | ||
101 | + * All slaves will enter EL2 and optionally EL1. | ||
102 | + */ | ||
103 | + adr x4, lowlevel_in_el2 | ||
104 | + ldr x5, =ES_TO_AARCH64 | ||
105 | + bl armv8_switch_to_el2 | ||
106 | + | ||
107 | +lowlevel_in_el2: | ||
108 | +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 | ||
109 | + adr x4, lowlevel_in_el1 | ||
110 | + ldr x5, =ES_TO_AARCH64 | ||
111 | + bl armv8_switch_to_el1 | ||
112 | + | ||
113 | +lowlevel_in_el1: | ||
114 | +#endif | ||
115 | + | ||
116 | +#endif /* CONFIG_ARMV8_MULTIENTRY */ | ||
117 | + | ||
118 | +2: | ||
119 | +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) | ||
120 | + /* | ||
121 | + * Write the u-boot PSCI exception handler's vector base address | ||
122 | + * into a sysmgr.boot_scratch_cold6 & 7 so that other slave cpus | ||
123 | + * are able to get the vector base address and update their VBAR_EL3 | ||
124 | + * respectively. | ||
125 | + */ | ||
126 | + adr x0, _el3_exception_vectors | ||
127 | + ldr x5, [x0] | ||
128 | + ldr x4, =VBAR_EL3_BASE_ADDR | ||
129 | + str x5, [x4] | ||
130 | +#endif | ||
131 | + mov lr, x29 /* Restore LR */ | ||
132 | + ret | ||
133 | +ENDPROC(lowlevel_init) | ||
134 | diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h | ||
135 | index 8d2971c6e2..39d757d737 100644 | ||
136 | --- a/include/configs/socfpga_stratix10_socdk.h | ||
137 | +++ b/include/configs/socfpga_stratix10_socdk.h | ||
138 | @@ -19,6 +19,12 @@ | ||
139 | #define CONFIG_REMAKE_ELF | ||
140 | /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ | ||
141 | #define CPU_RELEASE_ADDR 0xFFD12210 | ||
142 | +/* | ||
143 | + * sysmgr.boot_scratch_cold6 & 7 (64bit) will be used by master CPU to | ||
144 | + * store its VBAR_EL3 value. Other slave CPUs will read from this | ||
145 | + * location and update their VBAR_EL3 respectively | ||
146 | + */ | ||
147 | +#define VBAR_EL3_BASE_ADDR 0xFFD12218 | ||
148 | #define CONFIG_SYS_CACHELINE_SIZE 64 | ||
149 | #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ | ||
150 | |||
151 | -- | ||
152 | 2.21.0 | ||
153 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch b/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch new file mode 100644 index 0000000..fd43dd2 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch | |||
@@ -0,0 +1,102 @@ | |||
1 | From 16460c05fe576050cf485282151fd5623d6e862a Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Wed, 22 May 2019 17:05:12 -0700 | ||
4 | Subject: [PATCH 05/12] ARM: socfpga: stratix10: Add SOCFPGA bridges reset | ||
5 | support for PSCI call | ||
6 | |||
7 | Add SOCFPGA bridges reset support for FPGA configuration SMC services | ||
8 | to disable/enable the bridges before and after the FPGA configuration | ||
9 | process. | ||
10 | |||
11 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | ||
12 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
13 | --- | ||
14 | .../include/mach/reset_manager_s10.h | 1 + | ||
15 | arch/arm/mach-socfpga/reset_manager_s10.c | 25 ++++++++++++++++++- | ||
16 | 2 files changed, 25 insertions(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | ||
19 | index 452147b017..1939ffa149 100644 | ||
20 | --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | ||
21 | +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | ||
22 | @@ -11,6 +11,7 @@ void reset_cpu(ulong addr); | ||
23 | int cpu_has_been_warmreset(void); | ||
24 | |||
25 | void socfpga_bridges_reset(int enable); | ||
26 | +void socfpga_bridges_reset_psci(int enable); | ||
27 | |||
28 | void socfpga_per_reset(u32 reset, int set); | ||
29 | void socfpga_per_reset_all(void); | ||
30 | diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c | ||
31 | index 499a84aff5..4494f6666f 100644 | ||
32 | --- a/arch/arm/mach-socfpga/reset_manager_s10.c | ||
33 | +++ b/arch/arm/mach-socfpga/reset_manager_s10.c | ||
34 | @@ -9,6 +9,7 @@ | ||
35 | #include <asm/arch/reset_manager.h> | ||
36 | #include <asm/arch/system_manager.h> | ||
37 | #include <dt-bindings/reset/altr,rst-mgr-s10.h> | ||
38 | +#include <asm/secure.h> | ||
39 | |||
40 | DECLARE_GLOBAL_DATA_PTR; | ||
41 | |||
42 | @@ -20,6 +21,8 @@ static const struct socfpga_system_manager *system_manager_base = | ||
43 | /* Assert or de-assert SoCFPGA reset manager reset. */ | ||
44 | void socfpga_per_reset(u32 reset, int set) | ||
45 | { | ||
46 | + static const struct socfpga_reset_manager *reset_manager_base = | ||
47 | + (void *)SOCFPGA_RSTMGR_ADDRESS; | ||
48 | const void *reg; | ||
49 | |||
50 | if (RSTMGR_BANK(reset) == 0) | ||
51 | @@ -46,6 +49,8 @@ void socfpga_per_reset(u32 reset, int set) | ||
52 | */ | ||
53 | void socfpga_per_reset_all(void) | ||
54 | { | ||
55 | + static const struct socfpga_reset_manager *reset_manager_base = | ||
56 | + (void *)SOCFPGA_RSTMGR_ADDRESS; | ||
57 | const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); | ||
58 | |||
59 | /* disable all except OCP and l4wd0. OCP disable later */ | ||
60 | @@ -55,8 +60,13 @@ void socfpga_per_reset_all(void) | ||
61 | writel(0xffffffff, &reset_manager_base->per1modrst); | ||
62 | } | ||
63 | |||
64 | -void socfpga_bridges_reset(int enable) | ||
65 | +static __always_inline void __socfpga_bridges_reset(int enable) | ||
66 | { | ||
67 | + static const struct socfpga_reset_manager *reset_manager_base = | ||
68 | + (void *)SOCFPGA_RSTMGR_ADDRESS; | ||
69 | + static const struct socfpga_system_manager *system_manager_base = | ||
70 | + (void *)SOCFPGA_SYSMGR_ADDRESS; | ||
71 | + | ||
72 | if (enable) { | ||
73 | /* clear idle request to all bridges */ | ||
74 | setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); | ||
75 | @@ -94,11 +104,24 @@ void socfpga_bridges_reset(int enable) | ||
76 | } | ||
77 | } | ||
78 | |||
79 | +void socfpga_bridges_reset(int enable) | ||
80 | +{ | ||
81 | + __socfpga_bridges_reset(enable); | ||
82 | +} | ||
83 | + | ||
84 | +void __secure socfpga_bridges_reset_psci(int enable) | ||
85 | +{ | ||
86 | + __socfpga_bridges_reset(enable); | ||
87 | +} | ||
88 | + | ||
89 | /* | ||
90 | * Return non-zero if the CPU has been warm reset | ||
91 | */ | ||
92 | int cpu_has_been_warmreset(void) | ||
93 | { | ||
94 | + static const struct socfpga_reset_manager *reset_manager_base = | ||
95 | + (void *)SOCFPGA_RSTMGR_ADDRESS; | ||
96 | + | ||
97 | return readl(&reset_manager_base->status) & | ||
98 | RSTMGR_L4WD_MPU_WARMRESET_MASK; | ||
99 | } | ||
100 | -- | ||
101 | 2.21.0 | ||
102 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch b/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch new file mode 100644 index 0000000..cc0be27 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch | |||
@@ -0,0 +1,833 @@ | |||
1 | From 04187fba93e6d359ebb4dd8e397dff282f53ec5a Mon Sep 17 00:00:00 2001 | ||
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | ||
3 | Date: Mon, 29 Apr 2019 23:42:39 -0700 | ||
4 | Subject: [PATCH 06/12] ARM: socfpga: stratix10: Add Stratix10 FPGA | ||
5 | configuration PSCI services | ||
6 | |||
7 | Allow PSCI layer to handle the S10 FPGA configuration (SiP) service | ||
8 | calls. All these services are also known as FPGA configuration service | ||
9 | layer for S10. This service layer support FPGA configuration service | ||
10 | requests from OS (EL1). It acts as the middle layer between SDM | ||
11 | (Secure Device Manager) and the OS. It enables OS (EL1) to invoke SMC | ||
12 | call to this service layer (EL3) and pass the FPGA bit stream to SDM | ||
13 | for FPGA configuration. | ||
14 | |||
15 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | ||
16 | --- | ||
17 | arch/arm/mach-socfpga/Makefile | 1 + | ||
18 | arch/arm/mach-socfpga/include/mach/smc_s10.h | 42 ++ | ||
19 | arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c | 422 ++++++++++++++++++ | ||
20 | include/linux/intel-smc.h | 311 +++++++++++++ | ||
21 | 4 files changed, 776 insertions(+) | ||
22 | create mode 100644 arch/arm/mach-socfpga/include/mach/smc_s10.h | ||
23 | create mode 100644 arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c | ||
24 | create mode 100644 include/linux/intel-smc.h | ||
25 | |||
26 | diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile | ||
27 | index d34198d159..88970e7555 100644 | ||
28 | --- a/arch/arm/mach-socfpga/Makefile | ||
29 | +++ b/arch/arm/mach-socfpga/Makefile | ||
30 | @@ -41,6 +41,7 @@ obj-y += wrap_pinmux_config_s10.o | ||
31 | obj-y += wrap_pll_config_s10.o | ||
32 | ifndef CONFIG_SPL_BUILD | ||
33 | obj-$(CONFIG_ARMV8_PSCI) += psci.o | ||
34 | +obj-$(CONFIG_FPGA_STRATIX10) += smc_fpga_reconfig_s10.o | ||
35 | endif | ||
36 | endif | ||
37 | |||
38 | diff --git a/arch/arm/mach-socfpga/include/mach/smc_s10.h b/arch/arm/mach-socfpga/include/mach/smc_s10.h | ||
39 | new file mode 100644 | ||
40 | index 0000000000..9c82d863e5 | ||
41 | --- /dev/null | ||
42 | +++ b/arch/arm/mach-socfpga/include/mach/smc_s10.h | ||
43 | @@ -0,0 +1,42 @@ | ||
44 | +/* | ||
45 | + * Copyright (C) 2018 Intel Corporation. All rights reserved | ||
46 | + * | ||
47 | + * SPDX-License-Identifier: GPL-2.0 | ||
48 | + */ | ||
49 | + | ||
50 | +#include <common.h> | ||
51 | + | ||
52 | +#define SMC_ARG0 0 | ||
53 | +#define SMC_ARG1 (SMC_ARG0 + 1) | ||
54 | +#define SMC_ARG2 (SMC_ARG1 + 1) | ||
55 | +#define SMC_ARG3 (SMC_ARG2 + 1) | ||
56 | +#define SMC_RETURN_ARGS_MAX (SMC_ARG3 + 1) | ||
57 | + | ||
58 | +/* Macro functions for allocation and read/write of | ||
59 | + variables to be assigned to registers */ | ||
60 | +/* Allocate memory for variable */ | ||
61 | +#define SMC_ALLOC_REG_MEM(var) unsigned long var[SMC_RETURN_ARGS_MAX] | ||
62 | +/* Clear variable */ | ||
63 | +#define SMC_INIT_REG_MEM(var) \ | ||
64 | + do { \ | ||
65 | + int i; \ | ||
66 | + for (i = 0; i < SMC_RETURN_ARGS_MAX; i++) \ | ||
67 | + var[i] = 0; \ | ||
68 | + } while (0) | ||
69 | +/* Read variable */ | ||
70 | +#define SMC_GET_REG_MEM(var, i) var[i] | ||
71 | +/* Write Variable */ | ||
72 | +#define SMC_ASSIGN_REG_MEM(var, i, val) \ | ||
73 | + do { \ | ||
74 | + var[i] = (val); \ | ||
75 | + } while (0) | ||
76 | +/* Assign variables back to registers */ | ||
77 | +#define SMC_RET_REG_MEM(var) \ | ||
78 | + do { \ | ||
79 | + asm volatile("ldr x0, %0\n" \ | ||
80 | + "ldr x1, %1\n" \ | ||
81 | + "ldr x2, %2\n" \ | ||
82 | + "ldr x3, %3\n" \ | ||
83 | + : : "m" (var[0]), "m" (var[1]), \ | ||
84 | + "m" (var[2]), "m" (var[3]) : ); \ | ||
85 | + } while (0) | ||
86 | diff --git a/arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c b/arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c | ||
87 | new file mode 100644 | ||
88 | index 0000000000..0ed12e16b4 | ||
89 | --- /dev/null | ||
90 | +++ b/arch/arm/mach-socfpga/smc_fpga_reconfig_s10.c | ||
91 | @@ -0,0 +1,422 @@ | ||
92 | +/* | ||
93 | + * Copyright (C) 2018 Intel Corporation. All rights reserved | ||
94 | + * | ||
95 | + * SPDX-License-Identifier: GPL-2.0 | ||
96 | + */ | ||
97 | + | ||
98 | +#include <common.h> | ||
99 | +#include <errno.h> | ||
100 | +#include <asm/io.h> | ||
101 | +#include <asm/psci.h> | ||
102 | +#include <asm/secure.h> | ||
103 | +#include <asm/arch/mailbox_s10.h> | ||
104 | +#include <asm/arch/smc_s10.h> | ||
105 | +#include <linux/intel-smc.h> | ||
106 | +#include <asm/arch/reset_manager.h> | ||
107 | + | ||
108 | +/* Start of reserved memory */ | ||
109 | +#define FPGA_CONFIG_RESEVED_MEM_START (CONFIG_SYS_SDRAM_BASE + \ | ||
110 | + 0x400000) | ||
111 | +/* End of reserved memory */ | ||
112 | +#define FPGA_CONFIG_RESERVED_MEM_END (CONFIG_SYS_SDRAM_BASE + \ | ||
113 | + 0xFFFFFF) | ||
114 | + | ||
115 | +#define FPGA_CONFIG_BUF_MAX 16 | ||
116 | + | ||
117 | +#define FPGA_BUF_STAT_IDLE 0 | ||
118 | +#define FPGA_BUF_STAT_PENDING 1 | ||
119 | +#define FPGA_BUF_STAT_COMPLETED 2 | ||
120 | +#define FPGA_BUF_STAT_SUCCESS 3 | ||
121 | +#define FPGA_BUF_STAT_ERROR 4 | ||
122 | + | ||
123 | +#define IS_BUF_FREE(x) (x.state == FPGA_BUF_STAT_IDLE) | ||
124 | +#define IS_BUF_PENDING(x) (x.state == FPGA_BUF_STAT_PENDING) | ||
125 | +#define IS_BUF_SUBMITTED(x) (x.state >= FPGA_BUF_STAT_PENDING && \ | ||
126 | + x.submit_count > 0) | ||
127 | +#define IS_BUF_COMPLETED(x) (x.state == FPGA_BUF_STAT_COMPLETED && \ | ||
128 | + x.submit_count > 0) | ||
129 | +#define IS_BUF_FULLY_COMPLETED(x) (x.state == FPGA_BUF_STAT_COMPLETED && \ | ||
130 | + x.submit_count == 0) | ||
131 | +#define IS_BUF_SUCCESS(x) (x.state == FPGA_BUF_STAT_SUCCESS) | ||
132 | +#define IS_BUF_ERROR(x) (x.state == FPGA_BUF_STAT_ERROR) | ||
133 | + | ||
134 | +static __secure_data struct fpga_buf_list { | ||
135 | + u32 state; | ||
136 | + u32 buf_id; | ||
137 | + u64 buf_addr; | ||
138 | + u64 buf_size; | ||
139 | + u32 buf_off; | ||
140 | + u32 submit_count; | ||
141 | +} fpga_buf_list[FPGA_CONFIG_BUF_MAX]; | ||
142 | + | ||
143 | +static u8 __secure_data fpga_error = 1; | ||
144 | +static u8 __secure_data is_partial_reconfig; | ||
145 | +static u8 __secure_data fpga_buf_id = 1; | ||
146 | +static u32 __secure_data fpga_xfer_max = 4; | ||
147 | +static u32 __secure_data fpga_buf_read_index; | ||
148 | +static u32 __secure_data fpga_buf_write_index; | ||
149 | +static u32 __secure_data fpga_buf_count; | ||
150 | +/* 20bits DMA size with 8 bytes alignment */ | ||
151 | +static u32 __secure_data fpga_buf_size_max = 0xFFFF8; | ||
152 | +/* Number of data blocks received from OS(EL1) */ | ||
153 | +static u32 __secure_data fpga_buf_rcv_count; | ||
154 | +/* Number of data blocks submitted to SDM */ | ||
155 | +static u32 __secure_data fpga_xfer_submitted_count; | ||
156 | + | ||
157 | +/* Check for any responses from SDM and update the status in buffer list */ | ||
158 | +static void __secure reclaim_completed_buf(void) | ||
159 | +{ | ||
160 | + u32 i, j; | ||
161 | + u32 resp_len; | ||
162 | + u32 buf[MBOX_RESP_BUFFER_SIZE]; | ||
163 | + | ||
164 | + /* If no buffer has been submitted to SDM */ | ||
165 | + if (!fpga_xfer_submitted_count) | ||
166 | + return; | ||
167 | + | ||
168 | + /* Read the SDM responses asynchronously */ | ||
169 | + resp_len = mbox_rcv_resp_psci(buf, MBOX_RESP_BUFFER_SIZE); | ||
170 | + | ||
171 | + for (i = 0; i < resp_len; i++) { | ||
172 | + /* Skip mailbox response headers which are not belong to us */ | ||
173 | + if (MBOX_RESP_LEN_GET(buf[i]) || | ||
174 | + MBOX_RESP_CLIENT_GET(buf[i]) != MBOX_CLIENT_ID_UBOOT) | ||
175 | + continue; | ||
176 | + | ||
177 | + for (j = 0; j < FPGA_CONFIG_BUF_MAX; j++) { | ||
178 | + /* Check buffer id */ | ||
179 | + if (fpga_buf_list[j].buf_id != | ||
180 | + MBOX_RESP_ID_GET(buf[i])) | ||
181 | + continue; | ||
182 | + | ||
183 | + if (IS_BUF_SUBMITTED(fpga_buf_list[j])) { | ||
184 | + if (fpga_buf_list[j].submit_count) | ||
185 | + fpga_buf_list[j].submit_count--; | ||
186 | + fpga_xfer_submitted_count--; | ||
187 | + /* Error occur in transaction */ | ||
188 | + if (MBOX_RESP_ERR_GET(buf[i])) { | ||
189 | + fpga_error = 1; | ||
190 | + fpga_buf_list[j].state = | ||
191 | + FPGA_BUF_STAT_ERROR; | ||
192 | + fpga_buf_list[j].submit_count = 0; | ||
193 | + } else if (IS_BUF_FULLY_COMPLETED( | ||
194 | + fpga_buf_list[j])) { | ||
195 | + /* Last chunk in buffer and no error */ | ||
196 | + fpga_buf_list[j].state = | ||
197 | + FPGA_BUF_STAT_SUCCESS; | ||
198 | + } | ||
199 | + break; | ||
200 | + } else if (IS_BUF_ERROR(fpga_buf_list[j])) { | ||
201 | + fpga_xfer_submitted_count--; | ||
202 | + break; | ||
203 | + } | ||
204 | + } | ||
205 | + } | ||
206 | +} | ||
207 | + | ||
208 | +static void __secure do_xfer_buf(void) | ||
209 | +{ | ||
210 | + u32 i = fpga_buf_read_index; | ||
211 | + u32 args[3]; | ||
212 | + int ret; | ||
213 | + | ||
214 | + /* No buffer found in buffer list or SDM can't handle xfer anymore */ | ||
215 | + if (!fpga_buf_rcv_count || | ||
216 | + fpga_xfer_submitted_count == fpga_xfer_max) | ||
217 | + return; | ||
218 | + | ||
219 | + while (fpga_xfer_submitted_count < fpga_xfer_max) { | ||
220 | + if (IS_BUF_FREE(fpga_buf_list[i]) || | ||
221 | + IS_BUF_ERROR(fpga_buf_list[i])) | ||
222 | + break; | ||
223 | + if (IS_BUF_PENDING(fpga_buf_list[i])) { | ||
224 | + /* | ||
225 | + * Argument descriptor for RECONFIG_DATA | ||
226 | + * must always be 1. | ||
227 | + */ | ||
228 | + args[0] = MBOX_ARG_DESC_COUNT(1); | ||
229 | + args[1] = (u32)(fpga_buf_list[i].buf_addr + | ||
230 | + fpga_buf_list[i].buf_off); | ||
231 | + if ((fpga_buf_list[i].buf_size - | ||
232 | + fpga_buf_list[i].buf_off) > fpga_buf_size_max) { | ||
233 | + args[2] = fpga_buf_size_max; | ||
234 | + fpga_buf_list[i].buf_off += fpga_buf_size_max; | ||
235 | + } else { | ||
236 | + args[2] = (u32)(fpga_buf_list[i].buf_size - | ||
237 | + fpga_buf_list[i].buf_off); | ||
238 | + fpga_buf_list[i].state = | ||
239 | + FPGA_BUF_STAT_COMPLETED; | ||
240 | + } | ||
241 | + | ||
242 | + ret = mbox_send_cmd_only_psci(fpga_buf_list[i].buf_id, | ||
243 | + MBOX_RECONFIG_DATA, MBOX_CMD_INDIRECT, 3, | ||
244 | + args); | ||
245 | + if (ret) { | ||
246 | + fpga_error = 1; | ||
247 | + fpga_buf_list[i].state = | ||
248 | + FPGA_BUF_STAT_ERROR; | ||
249 | + fpga_buf_list[i].submit_count = 0; | ||
250 | + break; | ||
251 | + } else { | ||
252 | + fpga_buf_list[i].submit_count++; | ||
253 | + fpga_xfer_submitted_count++; | ||
254 | + } | ||
255 | + | ||
256 | + if (fpga_xfer_submitted_count >= fpga_xfer_max) | ||
257 | + break; | ||
258 | + } | ||
259 | + | ||
260 | + if (IS_BUF_COMPLETED(fpga_buf_list[i]) || | ||
261 | + IS_BUF_SUCCESS(fpga_buf_list[i])) { | ||
262 | + i++; | ||
263 | + i %= FPGA_CONFIG_BUF_MAX; | ||
264 | + if (i == fpga_buf_write_index) | ||
265 | + break; | ||
266 | + } | ||
267 | + } | ||
268 | +} | ||
269 | + | ||
270 | +static void __secure smc_config_get_mem(unsigned long function_id) | ||
271 | +{ | ||
272 | + SMC_ALLOC_REG_MEM(r); | ||
273 | + | ||
274 | + SMC_INIT_REG_MEM(r); | ||
275 | + | ||
276 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_STATUS_OK); | ||
277 | + /* Start physical address of reserved memory */ | ||
278 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG1, FPGA_CONFIG_RESEVED_MEM_START); | ||
279 | + /* Size of reserved memory */ | ||
280 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG2, FPGA_CONFIG_RESERVED_MEM_END - | ||
281 | + FPGA_CONFIG_RESEVED_MEM_START + 1); | ||
282 | + | ||
283 | + SMC_RET_REG_MEM(r); | ||
284 | +} | ||
285 | + | ||
286 | +static void __secure smc_config_start(unsigned long function_id, | ||
287 | + unsigned long config_type) | ||
288 | +{ | ||
289 | + SMC_ALLOC_REG_MEM(r); | ||
290 | + int ret, i; | ||
291 | + u32 resp_len = 2; | ||
292 | + u32 resp_buf[2]; | ||
293 | + | ||
294 | + /* Clear any previous pending SDM reponses */ | ||
295 | + mbox_rcv_resp_psci(NULL, MBOX_RESP_BUFFER_SIZE); | ||
296 | + | ||
297 | + SMC_INIT_REG_MEM(r); | ||
298 | + | ||
299 | + fpga_error = 0; | ||
300 | + | ||
301 | + ret = mbox_send_cmd_psci(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, | ||
302 | + 0, NULL, 0, &resp_len, resp_buf); | ||
303 | + if (ret) { | ||
304 | + fpga_error = 1; | ||
305 | + goto ret; | ||
306 | + } | ||
307 | + | ||
308 | + /* Initialize the state of the buffer list */ | ||
309 | + for (i = 0; i < FPGA_CONFIG_BUF_MAX; i++) { | ||
310 | + fpga_buf_list[i].state = FPGA_BUF_STAT_IDLE; | ||
311 | + fpga_buf_list[i].buf_id = 0; | ||
312 | + } | ||
313 | + | ||
314 | + /* Read maximum transaction allowed by SDM */ | ||
315 | + fpga_xfer_max = resp_buf[0]; | ||
316 | + /* Read maximum buffer size allowed by SDM */ | ||
317 | + fpga_buf_size_max = resp_buf[1]; | ||
318 | + fpga_buf_count = 0; | ||
319 | + fpga_buf_rcv_count = 0; | ||
320 | + fpga_xfer_submitted_count = 0; | ||
321 | + fpga_buf_read_index = 0; | ||
322 | + fpga_buf_write_index = 0; | ||
323 | + fpga_buf_id = 1; | ||
324 | + | ||
325 | + is_partial_reconfig = (u8)config_type; | ||
326 | + | ||
327 | + /* Check whether config type is full reconfiguration */ | ||
328 | + if (!is_partial_reconfig) { | ||
329 | + /* Disable bridge */ | ||
330 | + socfpga_bridges_reset_psci(0); | ||
331 | + } | ||
332 | + | ||
333 | +ret: | ||
334 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_STATUS_OK); | ||
335 | + | ||
336 | + SMC_RET_REG_MEM(r); | ||
337 | +} | ||
338 | + | ||
339 | +static void __secure smc_config_write(unsigned long function_id, | ||
340 | + unsigned long phys_addr, | ||
341 | + unsigned long phys_size) | ||
342 | +{ | ||
343 | + SMC_ALLOC_REG_MEM(r); | ||
344 | + | ||
345 | + SMC_INIT_REG_MEM(r); | ||
346 | + | ||
347 | + reclaim_completed_buf(); | ||
348 | + | ||
349 | + if (fpga_error) { | ||
350 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
351 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); | ||
352 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG1, | ||
353 | + fpga_buf_list[fpga_buf_read_index]. | ||
354 | + buf_addr); | ||
355 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG2, | ||
356 | + fpga_buf_list[fpga_buf_read_index]. | ||
357 | + buf_size); | ||
358 | + goto ret; | ||
359 | + } | ||
360 | + | ||
361 | + do_xfer_buf(); | ||
362 | + | ||
363 | + if (fpga_buf_rcv_count == fpga_xfer_max || | ||
364 | + (fpga_buf_count == FPGA_CONFIG_BUF_MAX && | ||
365 | + fpga_buf_write_index == fpga_buf_read_index)) { | ||
366 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
367 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED); | ||
368 | + goto ret; | ||
369 | + } | ||
370 | + | ||
371 | + if (!phys_addr || !phys_size) { | ||
372 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
373 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); | ||
374 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG1, phys_addr); | ||
375 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG2, phys_size); | ||
376 | + goto ret; | ||
377 | + } | ||
378 | + | ||
379 | + /* Look for free buffer in buffer list */ | ||
380 | + if (IS_BUF_FREE(fpga_buf_list[fpga_buf_write_index])) { | ||
381 | + fpga_buf_list[fpga_buf_write_index].state = | ||
382 | + FPGA_BUF_STAT_PENDING; | ||
383 | + fpga_buf_list[fpga_buf_write_index].buf_addr = phys_addr; | ||
384 | + fpga_buf_list[fpga_buf_write_index].buf_size = phys_size; | ||
385 | + fpga_buf_list[fpga_buf_write_index].buf_off = 0; | ||
386 | + fpga_buf_list[fpga_buf_write_index].buf_id = fpga_buf_id++; | ||
387 | + /* Rollover buffer id */ | ||
388 | + if (fpga_buf_id > 15) | ||
389 | + fpga_buf_id = 1; | ||
390 | + fpga_buf_count++; | ||
391 | + fpga_buf_write_index++; | ||
392 | + fpga_buf_write_index %= FPGA_CONFIG_BUF_MAX; | ||
393 | + fpga_buf_rcv_count++; | ||
394 | + if (fpga_buf_rcv_count == fpga_xfer_max) | ||
395 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
396 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY); | ||
397 | + else | ||
398 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
399 | + INTEL_SIP_SMC_STATUS_OK); | ||
400 | + /* Attempt to submit new buffer to SDM */ | ||
401 | + do_xfer_buf(); | ||
402 | + } else { | ||
403 | + /* No free buffer available in buffer list */ | ||
404 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
405 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED); | ||
406 | + } | ||
407 | + | ||
408 | +ret: | ||
409 | + SMC_RET_REG_MEM(r); | ||
410 | +} | ||
411 | + | ||
412 | +static void __secure smc_config_completed_write(unsigned long function_id) | ||
413 | +{ | ||
414 | + SMC_ALLOC_REG_MEM(r); | ||
415 | + int i; | ||
416 | + int count = 3, r_index = 1; | ||
417 | + | ||
418 | + SMC_INIT_REG_MEM(r); | ||
419 | + | ||
420 | + reclaim_completed_buf(); | ||
421 | + do_xfer_buf(); | ||
422 | + | ||
423 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
424 | + INTEL_SIP_SMC_STATUS_OK); | ||
425 | + | ||
426 | + for (i = 0; i < FPGA_CONFIG_BUF_MAX; i++) { | ||
427 | + if (IS_BUF_SUCCESS(fpga_buf_list[fpga_buf_read_index])) { | ||
428 | + SMC_ASSIGN_REG_MEM(r, r_index++, | ||
429 | + fpga_buf_list[fpga_buf_read_index].buf_addr); | ||
430 | + fpga_buf_list[fpga_buf_read_index].state = | ||
431 | + FPGA_BUF_STAT_IDLE; | ||
432 | + fpga_buf_list[fpga_buf_read_index].buf_id = 0; | ||
433 | + fpga_buf_count--; | ||
434 | + fpga_buf_read_index++; | ||
435 | + fpga_buf_read_index %= FPGA_CONFIG_BUF_MAX; | ||
436 | + fpga_buf_rcv_count--; | ||
437 | + count--; | ||
438 | + if (!count) | ||
439 | + break; | ||
440 | + } else if (IS_BUF_ERROR(fpga_buf_list[fpga_buf_read_index]) && | ||
441 | + !fpga_buf_list[fpga_buf_read_index].submit_count) { | ||
442 | + SMC_INIT_REG_MEM(r); | ||
443 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
444 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); | ||
445 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG1, | ||
446 | + fpga_buf_list[fpga_buf_read_index].buf_addr); | ||
447 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG2, | ||
448 | + fpga_buf_list[fpga_buf_read_index].buf_size); | ||
449 | + goto ret; | ||
450 | + } | ||
451 | + } | ||
452 | + | ||
453 | + /* No completed buffers found */ | ||
454 | + if (r_index == 1 && fpga_xfer_submitted_count) | ||
455 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
456 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY); | ||
457 | + | ||
458 | +ret: | ||
459 | + SMC_RET_REG_MEM(r); | ||
460 | +} | ||
461 | + | ||
462 | +static void __secure smc_config_isdone(unsigned long function_id) | ||
463 | +{ | ||
464 | + SMC_ALLOC_REG_MEM(r); | ||
465 | + int ret; | ||
466 | + | ||
467 | + SMC_INIT_REG_MEM(r); | ||
468 | + | ||
469 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY); | ||
470 | + | ||
471 | + reclaim_completed_buf(); | ||
472 | + do_xfer_buf(); | ||
473 | + | ||
474 | + if (fpga_error) { | ||
475 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
476 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); | ||
477 | + goto ret; | ||
478 | + } | ||
479 | + | ||
480 | + if (fpga_xfer_submitted_count) | ||
481 | + goto ret; | ||
482 | + | ||
483 | + ret = mbox_get_fpga_config_status_psci(MBOX_RECONFIG_STATUS); | ||
484 | + if (ret) { | ||
485 | + if (ret != MBOX_CFGSTAT_STATE_CONFIG) { | ||
486 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, | ||
487 | + INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR); | ||
488 | + fpga_error = 1; | ||
489 | + } | ||
490 | + goto ret; | ||
491 | + } | ||
492 | + | ||
493 | + /* FPGA configuration completed successfully */ | ||
494 | + SMC_ASSIGN_REG_MEM(r, SMC_ARG0, INTEL_SIP_SMC_STATUS_OK); | ||
495 | + | ||
496 | + /* Check whether config type is full reconfiguration */ | ||
497 | + if (!is_partial_reconfig) | ||
498 | + socfpga_bridges_reset_psci(1); /* Enable bridge */ | ||
499 | +ret: | ||
500 | + SMC_RET_REG_MEM(r); | ||
501 | +} | ||
502 | + | ||
503 | +DECLARE_SECURE_SVC(config_get_mem, INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM, | ||
504 | + smc_config_get_mem); | ||
505 | +DECLARE_SECURE_SVC(config_start, INTEL_SIP_SMC_FPGA_CONFIG_START, | ||
506 | + smc_config_start); | ||
507 | +DECLARE_SECURE_SVC(config_write, INTEL_SIP_SMC_FPGA_CONFIG_WRITE, | ||
508 | + smc_config_write); | ||
509 | +DECLARE_SECURE_SVC(config_completed_write, | ||
510 | + INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE, | ||
511 | + smc_config_completed_write); | ||
512 | +DECLARE_SECURE_SVC(config_isdone, INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, | ||
513 | + smc_config_isdone); | ||
514 | diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h | ||
515 | new file mode 100644 | ||
516 | index 0000000000..5e4c156e42 | ||
517 | --- /dev/null | ||
518 | +++ b/include/linux/intel-smc.h | ||
519 | @@ -0,0 +1,311 @@ | ||
520 | +/* SPDX-License-Identifier: GPL-2.0 */ | ||
521 | +/* | ||
522 | + * Copyright (C) 2017-2018, Intel Corporation | ||
523 | + */ | ||
524 | + | ||
525 | +#ifndef __INTEL_SMC_H | ||
526 | +#define __INTEL_SMC_H | ||
527 | + | ||
528 | +#include <linux/arm-smccc.h> | ||
529 | +#include <linux/bitops.h> | ||
530 | + | ||
531 | +/* | ||
532 | + * This file defines the Secure Monitor Call (SMC) message protocol used for | ||
533 | + * service layer driver in normal world (EL1) to communicate with secure | ||
534 | + * monitor software in Secure Monitor Exception Level 3 (EL3). | ||
535 | + * | ||
536 | + * This file is shared with secure firmware (FW) which is out of kernel tree. | ||
537 | + * | ||
538 | + * An ARM SMC instruction takes a function identifier and up to 6 64-bit | ||
539 | + * register values as arguments, and can return up to 4 64-bit register | ||
540 | + * value. The operation of the secure monitor is determined by the parameter | ||
541 | + * values passed in through registers. | ||
542 | + | ||
543 | + * EL1 and EL3 communicates pointer as physical address rather than the | ||
544 | + * virtual address. | ||
545 | + */ | ||
546 | + | ||
547 | +/* | ||
548 | + * Functions specified by ARM SMC Calling convention: | ||
549 | + * | ||
550 | + * FAST call executes atomic operations, returns when the requested operation | ||
551 | + * has completed. | ||
552 | + * STD call starts a operation which can be preempted by a non-secure | ||
553 | + * interrupt. The call can return before the requested operation has | ||
554 | + * completed. | ||
555 | + * | ||
556 | + * a0..a7 is used as register names in the descriptions below, on arm32 | ||
557 | + * that translates to r0..r7 and on arm64 to w0..w7. | ||
558 | + */ | ||
559 | + | ||
560 | +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ | ||
561 | + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ | ||
562 | + ARM_SMCCC_OWNER_SIP, (func_num)) | ||
563 | + | ||
564 | +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ | ||
565 | + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ | ||
566 | + ARM_SMCCC_OWNER_SIP, (func_num)) | ||
567 | + | ||
568 | +/* | ||
569 | + * Return values in INTEL_SIP_SMC_* call | ||
570 | + * | ||
571 | + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: | ||
572 | + * Secure monitor software doesn't recognize the request. | ||
573 | + * | ||
574 | + * INTEL_SIP_SMC_STATUS_OK: | ||
575 | + * FPGA configuration completed successfully, | ||
576 | + * In case of FPGA configuration write operation, it means secure monitor | ||
577 | + * software can accept the next chunk of FPGA configuration data. | ||
578 | + * | ||
579 | + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: | ||
580 | + * In case of FPGA configuration write operation, it means secure monitor | ||
581 | + * software is still processing previous data & can't accept the next chunk | ||
582 | + * of data. Service driver needs to issue | ||
583 | + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the | ||
584 | + * completed block(s). | ||
585 | + * | ||
586 | + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: | ||
587 | + * There is error during the FPGA configuration process. | ||
588 | + * | ||
589 | + * INTEL_SIP_SMC_REG_ERROR: | ||
590 | + * There is error during a read or write operation of the protected | ||
591 | + * registers. | ||
592 | + */ | ||
593 | +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF | ||
594 | +#define INTEL_SIP_SMC_STATUS_OK 0x0 | ||
595 | +#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY 0x1 | ||
596 | +#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED 0x2 | ||
597 | +#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4 | ||
598 | +#define INTEL_SIP_SMC_REG_ERROR 0x5 | ||
599 | +#define INTEL_SIP_SMC_RSU_ERROR 0x7 | ||
600 | + | ||
601 | +/* | ||
602 | + * Request INTEL_SIP_SMC_FPGA_CONFIG_START | ||
603 | + * | ||
604 | + * Sync call used by service driver at EL1 to request the FPGA in EL3 to | ||
605 | + * be prepare to receive a new configuration. | ||
606 | + * | ||
607 | + * Call register usage: | ||
608 | + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. | ||
609 | + * a1: flag for full or partial configuration | ||
610 | + * 0 full reconfiguration. | ||
611 | + * 1 partial reconfiguration. | ||
612 | + * a2-7: not used. | ||
613 | + * | ||
614 | + * Return status: | ||
615 | + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. | ||
616 | + * a1-3: not used. | ||
617 | + */ | ||
618 | +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 | ||
619 | +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ | ||
620 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) | ||
621 | + | ||
622 | +/* | ||
623 | + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE | ||
624 | + * | ||
625 | + * Async call used by service driver at EL1 to provide FPGA configuration data | ||
626 | + * to secure world. | ||
627 | + * | ||
628 | + * Call register usage: | ||
629 | + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. | ||
630 | + * a1: 64bit physical address of the configuration data memory block | ||
631 | + * a2: Size of configuration data block. | ||
632 | + * a3-7: not used. | ||
633 | + * | ||
634 | + * Return status: | ||
635 | + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or | ||
636 | + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. | ||
637 | + * a1: 64bit physical address of 1st completed memory block if any completed | ||
638 | + * block, otherwise zero value. | ||
639 | + * a2: 64bit physical address of 2nd completed memory block if any completed | ||
640 | + * block, otherwise zero value. | ||
641 | + * a3: 64bit physical address of 3rd completed memory block if any completed | ||
642 | + * block, otherwise zero value. | ||
643 | + */ | ||
644 | +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2 | ||
645 | +#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \ | ||
646 | + INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE) | ||
647 | + | ||
648 | +/* | ||
649 | + * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE | ||
650 | + * | ||
651 | + * Sync call used by service driver at EL1 to track the completed write | ||
652 | + * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE | ||
653 | + * call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY. | ||
654 | + * | ||
655 | + * Call register usage: | ||
656 | + * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. | ||
657 | + * a1-7: not used. | ||
658 | + * | ||
659 | + * Return status: | ||
660 | + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or | ||
661 | + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. | ||
662 | + * a1: 64bit physical address of 1st completed memory block. | ||
663 | + * a2: 64bit physical address of 2nd completed memory block if | ||
664 | + * any completed block, otherwise zero value. | ||
665 | + * a3: 64bit physical address of 3rd completed memory block if | ||
666 | + * any completed block, otherwise zero value. | ||
667 | + */ | ||
668 | +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3 | ||
669 | +#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \ | ||
670 | +INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) | ||
671 | + | ||
672 | +/* | ||
673 | + * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE | ||
674 | + * | ||
675 | + * Sync call used by service driver at EL1 to inform secure world that all | ||
676 | + * data are sent, to check whether or not the secure world had completed | ||
677 | + * the FPGA configuration process. | ||
678 | + * | ||
679 | + * Call register usage: | ||
680 | + * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE. | ||
681 | + * a1-7: not used. | ||
682 | + * | ||
683 | + * Return status: | ||
684 | + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or | ||
685 | + * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. | ||
686 | + * a1-3: not used. | ||
687 | + */ | ||
688 | +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 | ||
689 | +#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \ | ||
690 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE) | ||
691 | + | ||
692 | +/* | ||
693 | + * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM | ||
694 | + * | ||
695 | + * Sync call used by service driver at EL1 to query the physical address of | ||
696 | + * memory block reserved by secure monitor software. | ||
697 | + * | ||
698 | + * Call register usage: | ||
699 | + * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM. | ||
700 | + * a1-7: not used. | ||
701 | + * | ||
702 | + * Return status: | ||
703 | + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. | ||
704 | + * a1: start of physical address of reserved memory block. | ||
705 | + * a2: size of reserved memory block. | ||
706 | + * a3: not used. | ||
707 | + */ | ||
708 | +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5 | ||
709 | +#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \ | ||
710 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM) | ||
711 | + | ||
712 | +/* | ||
713 | + * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK | ||
714 | + * | ||
715 | + * For SMC loop-back mode only, used for internal integration, debugging | ||
716 | + * or troubleshooting. | ||
717 | + * | ||
718 | + * Call register usage: | ||
719 | + * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK. | ||
720 | + * a1-7: not used. | ||
721 | + * | ||
722 | + * Return status: | ||
723 | + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. | ||
724 | + * a1-3: not used. | ||
725 | + */ | ||
726 | +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 | ||
727 | +#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \ | ||
728 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK) | ||
729 | + | ||
730 | +/* | ||
731 | + * Request INTEL_SIP_SMC_REG_READ | ||
732 | + * | ||
733 | + * Read a protected register using SMCCC | ||
734 | + * | ||
735 | + * Call register usage: | ||
736 | + * a0: INTEL_SIP_SMC_REG_READ. | ||
737 | + * a1: register address. | ||
738 | + * a2-7: not used. | ||
739 | + * | ||
740 | + * Return status: | ||
741 | + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. | ||
742 | + * a1: Value in the register | ||
743 | + * a2-3: not used. | ||
744 | + */ | ||
745 | +#define INTEL_SIP_SMC_FUNCID_REG_READ 7 | ||
746 | +#define INTEL_SIP_SMC_REG_READ \ | ||
747 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) | ||
748 | + | ||
749 | +/* | ||
750 | + * Request INTEL_SIP_SMC_REG_WRITE | ||
751 | + * | ||
752 | + * Write a protected register using SMCCC | ||
753 | + * | ||
754 | + * Call register usage: | ||
755 | + * a0: INTEL_SIP_SMC_REG_WRITE. | ||
756 | + * a1: register address | ||
757 | + * a2: value to program into register. | ||
758 | + * a3-7: not used. | ||
759 | + * | ||
760 | + * Return status: | ||
761 | + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. | ||
762 | + * a1-3: not used. | ||
763 | + */ | ||
764 | +#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 | ||
765 | +#define INTEL_SIP_SMC_REG_WRITE \ | ||
766 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) | ||
767 | + | ||
768 | +/* | ||
769 | + * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE | ||
770 | + * | ||
771 | + * Update one or more bits in a protected register using a | ||
772 | + * read-modify-write operation. | ||
773 | + * | ||
774 | + * Call register usage: | ||
775 | + * a0: INTEL_SIP_SMC_REG_UPDATE. | ||
776 | + * a1: register address | ||
777 | + * a2: Write Mask. | ||
778 | + * a3: Value to write. | ||
779 | + * a4-7: not used. | ||
780 | + * | ||
781 | + * Return status: | ||
782 | + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. | ||
783 | + * a1-3: Not used. | ||
784 | + */ | ||
785 | +#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9 | ||
786 | +#define INTEL_SIP_SMC_REG_UPDATE \ | ||
787 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE) | ||
788 | + | ||
789 | +/* | ||
790 | + * Request INTEL_SIP_SMC_RSU_STATUS | ||
791 | + * | ||
792 | + * Sync call used by service driver at EL1 to query the RSU status | ||
793 | + * | ||
794 | + * Call register usage: | ||
795 | + * a0 INTEL_SIP_SMC_RSU_STATUS | ||
796 | + * a1-7 not used | ||
797 | + * | ||
798 | + * Return status | ||
799 | + * a0: Current Image | ||
800 | + * a1: Last Failing Image | ||
801 | + * a2: Version [width 32 bit] | State [width 32 bit] | ||
802 | + * a3: Error details [width 32 bit] | Error location [width 32 bit] | ||
803 | + * | ||
804 | + * Or | ||
805 | + * | ||
806 | + * a0: INTEL_SIP_SMC_RSU_ERROR | ||
807 | + */ | ||
808 | +#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11 | ||
809 | +#define INTEL_SIP_SMC_RSU_STATUS \ | ||
810 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS) | ||
811 | + | ||
812 | +/* | ||
813 | + * Request INTEL_SIP_SMC_RSU_UPDATE | ||
814 | + * | ||
815 | + * Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE | ||
816 | + * | ||
817 | + * Call register usage: | ||
818 | + * a0 INTEL_SIP_SMC_RSU_UPDATE | ||
819 | + * a1 64bit physical address of the configuration data memory in flash | ||
820 | + * a2-7 not used | ||
821 | + * | ||
822 | + * Return status | ||
823 | + * a0 INTEL_SIP_SMC_STATUS_OK | ||
824 | + */ | ||
825 | +#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12 | ||
826 | +#define INTEL_SIP_SMC_RSU_UPDATE \ | ||
827 | + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE) | ||
828 | + | ||
829 | + | ||
830 | +#endif | ||
831 | -- | ||
832 | 2.21.0 | ||
833 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch b/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch new file mode 100644 index 0000000..8da5892 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch | |||
@@ -0,0 +1,60 @@ | |||
1 | From 17366d3b46cf70a8fa4d807519790ef4b1b03772 Mon Sep 17 00:00:00 2001 | ||
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | ||
3 | Date: Wed, 30 Jan 2019 21:47:36 -0800 | ||
4 | Subject: [PATCH 07/12] mmc: dwmmc: Enable small delay before returning error | ||
5 | |||
6 | 'SET_BLOCKLEN' may occasionally fail on first attempt. | ||
7 | This patch enable a small delay in dwmci_send_cmd() on | ||
8 | busy, I/O or CRC error to allow the MMC controller recovers | ||
9 | from the failure/error on subsequent retries. | ||
10 | |||
11 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | ||
12 | --- | ||
13 | drivers/mmc/dw_mmc.c | 14 ++++++++++---- | ||
14 | 1 file changed, 10 insertions(+), 4 deletions(-) | ||
15 | |||
16 | diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c | ||
17 | index 1992d61182..8b9c6a8e60 100644 | ||
18 | --- a/drivers/mmc/dw_mmc.c | ||
19 | +++ b/drivers/mmc/dw_mmc.c | ||
20 | @@ -294,8 +294,11 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, | ||
21 | if (data) | ||
22 | flags = dwmci_set_transfer_mode(host, data); | ||
23 | |||
24 | - if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) | ||
25 | - return -1; | ||
26 | + if ((cmd->resp_type & MMC_RSP_136) && | ||
27 | + (cmd->resp_type & MMC_RSP_BUSY)) { | ||
28 | + ret = -1; | ||
29 | + goto delay_ret; | ||
30 | + } | ||
31 | |||
32 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | ||
33 | flags |= DWMCI_CMD_ABORT_STOP; | ||
34 | @@ -344,11 +347,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, | ||
35 | return -ETIMEDOUT; | ||
36 | } else if (mask & DWMCI_INTMSK_RE) { | ||
37 | debug("%s: Response Error.\n", __func__); | ||
38 | - return -EIO; | ||
39 | + ret = -EIO; | ||
40 | + goto delay_ret; | ||
41 | } else if ((cmd->resp_type & MMC_RSP_CRC) && | ||
42 | (mask & DWMCI_INTMSK_RCRC)) { | ||
43 | debug("%s: Response CRC Error.\n", __func__); | ||
44 | - return -EIO; | ||
45 | + ret = -EIO; | ||
46 | + goto delay_ret; | ||
47 | } | ||
48 | |||
49 | |||
50 | @@ -387,6 +392,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, | ||
51 | } | ||
52 | } | ||
53 | |||
54 | +delay_ret: | ||
55 | udelay(100); | ||
56 | |||
57 | return ret; | ||
58 | -- | ||
59 | 2.21.0 | ||
60 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch b/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch new file mode 100644 index 0000000..91505b7 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch | |||
@@ -0,0 +1,41 @@ | |||
1 | From da0bd33c8c8f6a1b77ecaa4c676f8ee14997b9e9 Mon Sep 17 00:00:00 2001 | ||
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | ||
3 | Date: Wed, 30 Jan 2019 21:29:09 -0800 | ||
4 | Subject: [PATCH 08/12] ARM: socfpga: stratix10: Enable DMA330 DMA controller | ||
5 | |||
6 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | ||
7 | --- | ||
8 | arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 1 + | ||
9 | arch/arm/mach-socfpga/spl_s10.c | 4 ++++ | ||
10 | 2 files changed, 5 insertions(+) | ||
11 | |||
12 | diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | ||
13 | index 1939ffa149..85424c28a6 100644 | ||
14 | --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | ||
15 | +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | ||
16 | @@ -97,6 +97,7 @@ struct socfpga_reset_manager { | ||
17 | #define RSTMGR_DMA RSTMGR_DEFINE(1, 16) | ||
18 | #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) | ||
19 | #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) | ||
20 | +#define RSTMGR_DMA_OCP RSTMGR_DEFINE(1, 21) | ||
21 | #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) | ||
22 | #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) | ||
23 | #define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) | ||
24 | diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c | ||
25 | index ec65e1ce64..04fa1a5696 100644 | ||
26 | --- a/arch/arm/mach-socfpga/spl_s10.c | ||
27 | +++ b/arch/arm/mach-socfpga/spl_s10.c | ||
28 | @@ -158,6 +158,10 @@ void board_init_f(ulong dummy) | ||
29 | writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); | ||
30 | writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); | ||
31 | |||
32 | + /* enable DMA330 DMA */ | ||
33 | + socfpga_per_reset(SOCFPGA_RESET(DMA), 0); | ||
34 | + socfpga_per_reset(SOCFPGA_RESET(DMA_OCP), 0); | ||
35 | + | ||
36 | spl_disable_firewall_l4_per(); | ||
37 | |||
38 | spl_disable_firewall_l4_sys(); | ||
39 | -- | ||
40 | 2.21.0 | ||
41 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch new file mode 100644 index 0000000..54fa812 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch | |||
@@ -0,0 +1,32 @@ | |||
1 | From 8569e08a1a4b3bd810f60083058053a39b27534e Mon Sep 17 00:00:00 2001 | ||
2 | From: Chee Hong Ang <chee.hong.ang@intel.com> | ||
3 | Date: Sat, 18 May 2019 16:42:10 +0800 | ||
4 | Subject: [PATCH 09/12] ARM: socfpga: Stratix10: Fix el3_exception_vectors | ||
5 | relocation issue | ||
6 | |||
7 | New toolchain has issue relocating the 32-bit pointer to address of | ||
8 | el3_exception_vectors in secure section. This patch make sure the | ||
9 | address pointer to the secure section is 64-bit. | ||
10 | |||
11 | Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> | ||
12 | --- | ||
13 | arch/arm/mach-socfpga/lowlevel_init.S | 3 +-- | ||
14 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
15 | |||
16 | diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S | ||
17 | index 832785a682..342d5190b5 100644 | ||
18 | --- a/arch/arm/mach-socfpga/lowlevel_init.S | ||
19 | +++ b/arch/arm/mach-socfpga/lowlevel_init.S | ||
20 | @@ -12,8 +12,7 @@ | ||
21 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) | ||
22 | .align 3 | ||
23 | _el3_exception_vectors: | ||
24 | - .word el3_exception_vectors; | ||
25 | - .word 0 | ||
26 | + .quad el3_exception_vectors; | ||
27 | #endif | ||
28 | |||
29 | ENTRY(lowlevel_init) | ||
30 | -- | ||
31 | 2.21.0 | ||
32 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch b/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch new file mode 100644 index 0000000..113d767 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch | |||
@@ -0,0 +1,79 @@ | |||
1 | From 939875d39e56d6d2c965c2b63d5d2f20dff532e0 Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Wed, 20 Mar 2019 11:21:20 -0700 | ||
4 | Subject: [PATCH 10/12] Makefile: Add target to generate hex output for | ||
5 | combined spl and dtb | ||
6 | |||
7 | Some architectures, Stratix10, require a hex formatted spl that combines | ||
8 | the spl image and dtb. This adds a target to create said hex file with | ||
9 | and offset of SPL_TEXT_BASE. | ||
10 | |||
11 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
12 | --- | ||
13 | Makefile | 12 +++++++----- | ||
14 | scripts/Makefile.spl | 8 ++++++++ | ||
15 | 2 files changed, 15 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/Makefile b/Makefile | ||
18 | index 059978bfe6..62d85ff279 100644 | ||
19 | --- a/Makefile | ||
20 | +++ b/Makefile | ||
21 | @@ -1121,11 +1121,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ | ||
22 | $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ | ||
23 | $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) | ||
24 | |||
25 | -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) | ||
26 | - | ||
27 | -spl/u-boot-spl.hex: spl/u-boot-spl FORCE | ||
28 | - $(call if_changed,objcopy) | ||
29 | - | ||
30 | binary_size_check: u-boot-nodtb.bin FORCE | ||
31 | @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ | ||
32 | map_size=$(shell cat u-boot.map | \ | ||
33 | @@ -1704,6 +1699,13 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE | ||
34 | |||
35 | spl/u-boot-spl.bin: spl/u-boot-spl | ||
36 | @: | ||
37 | + | ||
38 | +spl/u-boot-spl-dtb.bin: spl/u-boot-spl | ||
39 | + @: | ||
40 | + | ||
41 | +spl/u-boot-spl-dtb.hex: spl/u-boot-spl | ||
42 | + @: | ||
43 | + | ||
44 | spl/u-boot-spl: tools prepare \ | ||
45 | $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ | ||
46 | $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) | ||
47 | diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl | ||
48 | index 7af6b120b6..3c90e2cd72 100644 | ||
49 | --- a/scripts/Makefile.spl | ||
50 | +++ b/scripts/Makefile.spl | ||
51 | @@ -216,6 +216,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) | ||
52 | ALL-y += $(obj)/$(SPL_BIN).sfp | ||
53 | endif | ||
54 | |||
55 | +ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl-dtb.hex | ||
56 | + | ||
57 | ifdef CONFIG_ARCH_SUNXI | ||
58 | ALL-y += $(obj)/sunxi-spl.bin | ||
59 | |||
60 | @@ -363,6 +365,11 @@ endif | ||
61 | $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE | ||
62 | $(call if_changed,mkimage) | ||
63 | |||
64 | +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) | ||
65 | + | ||
66 | +$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE | ||
67 | + $(call if_changed,objcopy) | ||
68 | + | ||
69 | quiet_cmd_mksunxiboot = MKSUNXI $@ | ||
70 | cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \ | ||
71 | --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@ | ||
72 | @@ -463,3 +470,4 @@ ifdef CONFIG_ARCH_K3 | ||
73 | tispl.bin: $(obj)/u-boot-spl-nodtb.bin $(SHRUNK_ARCH_DTB) $(SPL_ITS) FORCE | ||
74 | $(call if_changed,mkfitimage) | ||
75 | endif | ||
76 | + | ||
77 | -- | ||
78 | 2.21.0 | ||
79 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch b/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch new file mode 100644 index 0000000..21794d2 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch | |||
@@ -0,0 +1,52 @@ | |||
1 | From 37814e55403a9ec5f852b58576618ba9a1936a20 Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Fri, 10 May 2019 10:30:44 -0700 | ||
4 | Subject: [PATCH 11/12] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED | ||
5 | |||
6 | CONFIG_OF_EMBED was primarily enabled to support the stratix10 | ||
7 | spl hex file requirements. Since this option now produces a | ||
8 | warning during build, and the spl hex can be created using | ||
9 | alternate methods, CONFIG_OF_EMBED is no longer needed. | ||
10 | |||
11 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
12 | --- | ||
13 | configs/socfpga_stratix10_defconfig | 1 - | ||
14 | include/configs/socfpga_stratix10_socdk.h | 4 ++-- | ||
15 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
16 | |||
17 | diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig | ||
18 | index fbab388b43..f27180385d 100644 | ||
19 | --- a/configs/socfpga_stratix10_defconfig | ||
20 | +++ b/configs/socfpga_stratix10_defconfig | ||
21 | @@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y | ||
22 | CONFIG_CMD_EXT4=y | ||
23 | CONFIG_CMD_FAT=y | ||
24 | CONFIG_CMD_FS_GENERIC=y | ||
25 | -CONFIG_OF_EMBED=y | ||
26 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" | ||
27 | CONFIG_ENV_IS_IN_MMC=y | ||
28 | CONFIG_NET_RANDOM_ETHADDR=y | ||
29 | diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h | ||
30 | index 39d757d737..e93c598be9 100644 | ||
31 | --- a/include/configs/socfpga_stratix10_socdk.h | ||
32 | +++ b/include/configs/socfpga_stratix10_socdk.h | ||
33 | @@ -197,7 +197,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); | ||
34 | * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) | ||
35 | * | ||
36 | */ | ||
37 | -#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" | ||
38 | +#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" | ||
39 | #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE | ||
40 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR | ||
41 | #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ | ||
42 | @@ -210,6 +210,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); | ||
43 | |||
44 | /* SPL SDMMC boot support */ | ||
45 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 | ||
46 | -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" | ||
47 | +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" | ||
48 | |||
49 | #endif /* __CONFIG_H */ | ||
50 | -- | ||
51 | 2.21.0 | ||
52 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch new file mode 100644 index 0000000..c7f73ba --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch | |||
@@ -0,0 +1,31 @@ | |||
1 | From 97d491bda1dea7d2afe74a7c3fb4ea43a83a79ff Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Fri, 10 May 2019 10:31:15 -0700 | ||
4 | Subject: [PATCH 12/12] ARM: socfpga: stratix10: Temporarily revert to 2GB DRAM | ||
5 | |||
6 | The current shipping GHRD still has the DDR configured as a | ||
7 | 2GB DDR. This reverts the devicetree to use 2GB instead of | ||
8 | 4GB. | ||
9 | |||
10 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
11 | --- | ||
12 | arch/arm/dts/socfpga_stratix10_socdk.dts | 3 +-- | ||
13 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts | ||
16 | index 2745050810..1caae0ab6f 100755 | ||
17 | --- a/arch/arm/dts/socfpga_stratix10_socdk.dts | ||
18 | +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts | ||
19 | @@ -37,8 +37,7 @@ | ||
20 | memory { | ||
21 | device_type = "memory"; | ||
22 | /* 4GB */ | ||
23 | - reg = <0 0x00000000 0 0x80000000>, | ||
24 | - <1 0x80000000 0 0x80000000>; | ||
25 | + reg = <0 0x00000000 0 0x80000000>; | ||
26 | u-boot,dm-pre-reloc; | ||
27 | }; | ||
28 | }; | ||
29 | -- | ||
30 | 2.21.0 | ||
31 | |||
diff --git a/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb b/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb new file mode 100644 index 0000000..48a517d --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb | |||
@@ -0,0 +1,29 @@ | |||
1 | require u-boot-socfpga-common.inc | ||
2 | require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc | ||
3 | |||
4 | LICENSE = "GPLv2+" | ||
5 | LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" | ||
6 | |||
7 | PR = "2" | ||
8 | |||
9 | FILESEXTRAPATHS =. "${THISDIR}/files/v2019.07:" | ||
10 | |||
11 | SRCREV = "7e090b466c5ba874d31c1bf22c3a130d516cdc32" | ||
12 | |||
13 | SRC_URI_append = "\ | ||
14 | file://0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch \ | ||
15 | file://0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch \ | ||
16 | file://0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch \ | ||
17 | file://0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch \ | ||
18 | file://0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch \ | ||
19 | file://0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch \ | ||
20 | file://0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch \ | ||
21 | file://0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch \ | ||
22 | file://0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch \ | ||
23 | file://0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch \ | ||
24 | file://0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch \ | ||
25 | file://0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch \ | ||
26 | file://0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch \ | ||
27 | " | ||
28 | |||
29 | DEPENDS += "dtc-native bc-native bison-native u-boot-mkimage-native" | ||