From 102d3d2fa1ecd62f6ed940e754b929446fb19b6d Mon Sep 17 00:00:00 2001 From: Andreas Wellving Date: Fri, 12 Oct 2018 07:54:40 +0200 Subject: x86: CVE-2018-15572 x86/speculation: Protect against userspace-userspace spectreRSB References: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-4.9.y&id=6455f41db5206cf46b623be071a0aa308c183642 Change-Id: I431a85f8cf64c89107fbc537c8a94fc9dddee1da Signed-off-by: Andreas Wellving --- patches/cve/4.9.x.scc | 3 + ...tion-Protect-against-userspace-userspace-.patch | 95 ++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch diff --git a/patches/cve/4.9.x.scc b/patches/cve/4.9.x.scc index 7283a43..b4a473e 100644 --- a/patches/cve/4.9.x.scc +++ b/patches/cve/4.9.x.scc @@ -3,3 +3,6 @@ patch CVE-2018-14734-infiniband-fix-a-possible-use-after-free-bug.patch #CVEs fixed in 4.9.119: patch CVE-2018-12233-jfs-Fix-inconsistency-between-memory-allocation-and-.patch + +#CVEs fixed in 4.9.120: +patch CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch diff --git a/patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch b/patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch new file mode 100644 index 0000000..31c3de6 --- /dev/null +++ b/patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch @@ -0,0 +1,95 @@ +Date: Thu, 11 Oct 2018 05:34:10 +0200 +Subject: [PATCH] x86/speculation: Protect against userspace-userspace + spectreRSB + +The article "Spectre Returns! Speculation Attacks using the Return Stack +Buffer" [1] describes two new (sub-)variants of spectrev2-like attacks, +making use solely of the RSB contents even on CPUs that don't fallback to +BTB on RSB underflow (Skylake+). + +Mitigate userspace-userspace attacks by always unconditionally filling RSB on +context switch when the generic spectrev2 mitigation has been enabled. + +[1] https://arxiv.org/pdf/1807.07940.pdf + +CVE: CVE-2018-15572 +Upstream-Status: Backport + +Signed-off-by: Jiri Kosina +Signed-off-by: Thomas Gleixner +Reviewed-by: Josh Poimboeuf +Acked-by: Tim Chen +Cc: Konrad Rzeszutek Wilk +Cc: Borislav Petkov +Cc: David Woodhouse +Cc: Peter Zijlstra +Cc: Linus Torvalds +Cc: stable@vger.kernel.org +Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1807261308190.997@cbobk.fhfr.pm +Signed-off-by: Andreas Wellving +--- + arch/x86/kernel/cpu/bugs.c | 40 ++++++++-------------------------------- + 1 file changed, 8 insertions(+), 32 deletions(-) + +diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c +index 86af9b1..a416723 100644 +--- a/arch/x86/kernel/cpu/bugs.c ++++ b/arch/x86/kernel/cpu/bugs.c +@@ -310,23 +310,6 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) + return cmd; + } + +-/* Check for Skylake-like CPUs (for RSB handling) */ +-static bool __init is_skylake_era(void) +-{ +- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && +- boot_cpu_data.x86 == 6) { +- switch (boot_cpu_data.x86_model) { +- case INTEL_FAM6_SKYLAKE_MOBILE: +- case INTEL_FAM6_SKYLAKE_DESKTOP: +- case INTEL_FAM6_SKYLAKE_X: +- case INTEL_FAM6_KABYLAKE_MOBILE: +- case INTEL_FAM6_KABYLAKE_DESKTOP: +- return true; +- } +- } +- return false; +-} +- + static void __init spectre_v2_select_mitigation(void) + { + enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); +@@ -387,22 +370,15 @@ static void __init spectre_v2_select_mitigation(void) + pr_info("%s\n", spectre_v2_strings[mode]); + + /* +- * If neither SMEP nor PTI are available, there is a risk of +- * hitting userspace addresses in the RSB after a context switch +- * from a shallow call stack to a deeper one. To prevent this fill +- * the entire RSB, even when using IBRS. +- * +- * Skylake era CPUs have a separate issue with *underflow* of the +- * RSB, when they will predict 'ret' targets from the generic BTB. +- * The proper mitigation for this is IBRS. If IBRS is not supported +- * or deactivated in favour of retpolines the RSB fill on context +- * switch is required. ++ * If spectre v2 protection has been enabled, unconditionally fill ++ * RSB during a context switch; this protects against two independent ++ * issues: ++ * ++ * - RSB underflow (and switch to BTB) on Skylake+ ++ * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs + */ +- if ((!boot_cpu_has(X86_FEATURE_KAISER) && +- !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { +- setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); +- pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); +- } ++ setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); ++ pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); + + /* Initialize Indirect Branch Prediction Barrier if supported */ + if (boot_cpu_has(X86_FEATURE_IBPB)) { +-- + + -- cgit v1.2.3-54-g00ecf